GB2317761A - Clock generator with a low amplitude standby mode oscillation - Google Patents

Abstract

A crystal oscillator, which may be used as a clock generator in a microcomputer system, operates even during standby (though at reduced amplitude), so that a full output level may be restored quickly when standby ends. During standby, current sources 50,60 or impedances are placed in series with the power supplies to the inverter 20, and the oscillator output is decoupled 70 from the circuit 80 it normally drives. The oscillator may be tested by monitoring the recovery time from standby.

Description

OSCILLAWR CIRCUIT, METHOD AND SYSTEM Field of the Invention This invention relates to oscillator circuits and particularly but not exclusively to clock signal generating oscillators for use with microcontrollers.

Background of the Invention Many battery operated logic circuits use quartz crystal oscillators to generate a periodic clock signal for a microprocessor. In some applications, microprocessors are put into a so called sleep or standby mode where the majority of the circuitry is disconnected from its power source. An external wake up unit is typically employed to power up the unit up from time to time, the wake up unit being arranged to look for events that require constant power up for system operation. With the above arrangement the average power consumption of the circuit is reduced, since less power is consumed during sleep mode.

A relatively long start up time is required for a quartz oscillator to reach its final required oscillating amplitude for correct system operation. This is because quartz crystals are piezoelectric devices, relying on mechanical motion to generate electrical properties. Also, when driven in an oscillator arrangement an amount of static friction (stiction) has to be overcome in order for the oscillator to start up.

A problem with this arrangement is that by switching off the clock generating oscillator circuit during sleep mode and restarting again when woken up, the microprocessor has to wait until the oscillator has reached its filll clock signal generating operation. This is typically achieved by means of an added delay.

Furthermore the oscillator circuit has to deliver a maximum current until the circuit has reached its full amplitude. As a result a fair amount of energy is lost during each start-up period.

This invention seeks to provide an oscillator circuit, method and system which mitigates the above mentioned disadvantages.

Summary of the Invention According to a first aspect of the present invention there is provided an oscillator circuit comprising: an oscillator coupled to a power supply and arranged for oscillating in a first and a second mode; and, a switch arrangement connected between the oscillator and the power supply and arranged for selectively switching the power supply between first and second levels; wherein in the first mode power is supplied at the first level to provide an operational current to the oscillator sufficient to drive a clock signal output, and in the second mode power is supplied at the second level to provide a standby current to the oscillator sufficient to maintain oscillation and insufficient to drive the clock signal output.

The oscillator preferably comprises a logic gate inverter coupled to receive a resonant signal from a quartz crystal. Preferably the switch arrangement comprises first and second current sources coupled to positive and negative power supply terminals of the oscillator. Preferably the second power level provides substantially the minimum required current to maintain oscillation of the oscillator.

According to a second aspect of the present invention there is provided a method of testing an oscillator comprising the steps of: providing a first power supply level to the oscillator sufficient to drive a clock signal output; switching the power supply between the first level and a second level, the second level being sufficient to maintain oscillation of a normally operational oscillator and insufficient to provide the clock signal output thereof; determining whether the oscillator has achieved oscillation at the second level; and, producing a test result signal dependent upon said determination.

Preferably the step of determining is achieved by switching from the second to the first level and by measuring the time taken for the oscillator to provide the clock signal output.

According to a third aspect of the present invention there is provided a microprocessor system arranged for operating in a normal mode and in a standby mode, comprising a microprocessor arranged to receive a clock signal; an oscillator coupled to a power supply and arranged for oscillating in dependence upon the supply current; and, a switch arrangement connected between the oscillator and the power supply and arranged for selectively switching the power supply between first and second levels; wherein in the normal mode power is supplied at the first level to provide sufficient current to cause the oscillator to drive the clock signal to the microprocessor, and in the standby mode power is supplied at the second level to provide sufficient current to maintain oscillation and insufficient current to drive the clock signal to the microprocessor.

In this way the need for a microprocessor delay when waking up after sleep mode is avoided and the large start-up current is conserved.

Bnef Description of the Drawmg(s) An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIG.1 shows a preferred embodiment of an oscillator circuit in accordance with the invention.

FIG.2 shows a voltage-time graph of a prior art oscillator circuit.

FIG.3 shows a voltage-time graph of the oscillator circuit of FIG.1.

Iletraled Desc;nDton ofa Prefened Emboment Referring to FIG.1, there is shown an oscillator circuit 10, which uses a logic gate inverter 20 coupled to a quartz crystal 15. The quartz crystal 15 has two electrodes, each coupled to ground via capacitors 17 and 18 respectively, and further coupled to first and second nodes 12 and 13 of the oscillator circuit 10.

The inverter 20 of the circuit 10 has an input coupled to the first node 12, and has a positive power supply input coupled via a first switch 35 to a supply voltage node 30. The inverter 20 also has a negative power supply input coupled via a second switch 45 to a ground terminal 40 and an output coupled to the second node 13. The output of the inverter 20 is also coupled to a clock output terminal 80 via a third switch 70.

First and second current sources 50 and 60 are coupled in parallel to the first and second switches 35 and 45 respectively, so as to provide a second current path to power the inverter 20. An external resistor 5 determines the amount of current provided through the current sources 50 and 60.

In operation, the oscillator circuit 10 has two modes. In a first mode, with the first, second and third switches 35, 45 and 70 respectively closed, normal supply current is provided to the inverter 20 and full oscillation occurs, giving rise to a clock frequency at the output of the inverter 20 of sufficient amplitude to drive a clock signal input, such as that of a microcontroller.

In a second standby mode, the first, second and third switches 35, 45 and 70 are open, and the power supply current to the inverter 20 is now provided via the first and second current sources 50 and 60 respectively.

The inverter 20 is electrically disconnected from the clock output terminal 80. The value of the resistor 5 is chosen such that just enough current flows through the current sources 50 and 60 to maintain a non-zero oscillation of the quartz crystal 15, but it is to be understood that this amount of current does not provide an adequate amplitude of oscillation to provide a reliable periodic signal to drive a clock signal input of a microprocessor. The amount of current required in the standby mode will depend on the oscillating frequency of the quartz crystal 15, and is determined by the value of the external resistor 5.

Referring now also to FIG.2 there is shown a voltage-time graph of the typical start up behaviour for a standard microcontroller oscillator circuit.

As can be seen, such a circuit can take up to 0.8 milliseconds to achieve full oscillation. During this time any device coupled to receive a clock signal from the clock signal output terminal 80 (such as a microprocessor) has to wait in a delay loop until sufficient time has passed to ensure that a reliable clock signal is being provided. Furthermore, a large current has to be provided to the oscillator circuit during start-up.

Referring now also to FIG.3, the behaviour of the preferred embodiment is shown. The quartz crystal 15 continuously oscillates, but when in the second standby mode, this oscillation is at a minimum amplitude level.

When the circuit 10 is then switched from the second standby mode to the first mode, the voltage gain increases rapidly and the quartz crystal 15 achieves full steady-state oscillation almost instantaneously.

In this way the problems associated with the frequent switching of a quartz crystal oscillator are substantially reduced by the provision of the second standby mode of the oscillator, during which less power is consumed.

When the circuit 10 is switched from the second standby mode to the first mode, the circuit 10 will deliver full oscillation amplitude very quickly.

Therefore no delays have to be incorporated into any devices receiving the clock signal output.

In addition this circuit can be used to facilitate early failure diagnosis of a crystal oscillator. In case of a marginally operational crystal the oscillator circuit 10 might stop oscillating when switched to the second mode. As soon as the oscillator circuit 10 is switched to the first mode again, such a marginally operational crystal would start oscillating from zero, following the slow ramp profile of FIG. 2. Thus a device coupled to switch the oscillator circuit 10 and coupled to receive the clock signal (such as a microcontroller) can detect this slow ramp and take appropriate action (such as sending a signal to a diagnostic bus).

It will be appreciated that alternative embodiments to the one described above are possible. For example, the first and second current sources 50 and 60 could be replaced by resistors. Indeed only one of the two sources would be necessary to achieve the second mode functionality of the circuit 10.

Furthermore, in a more basic embodiment, one or both of the current sources 50 and 60 could be replaced by alternative impedance sources.

Claims (10)

Claims

1. An oscillator circuit comprising: an oscillator coupled to a power supply and arranged for oscillating in a first and a second mode; and, a switch arrangement connected between the oscillator and the power supply and arranged for selectively switching the power supply between first and second levels; wherein in the first mode power is supplied at the first level to provide an operational current to the oscillator sufficient to drive a clock signal output, and in the second mode power is supplied at the second level to provide a standby current to the oscillator sufficient to maintain oscillation and insufficient to drive the clock signal output.

2. The oscillator circuit of claim 1 wherein the oscillator comprises a logic gate inverter coupled to receive a resonant signal from a quartz crystal.

3. The oscillator circuit of claim 1 or claim 2 wherein the switch arrangement comprises first and second current sources coupled to positive and negative power supply terminals of the oscillator.

4. The oscillator circuit of claim 1 wherein the second power level provides substantially the minimum required current to maintain oscillation of the oscillator.

5. A method of testing an oscillator comprising the steps of: providing a first power supply level to the oscillator sufficient to drive a clock signal output; switching the power supply between the first level and a second level, the second level being sufficient to maintain oscillation of a normally operational oscillator and insufficient to provide the clock signal output thereof; determining whether the oscillator has achieved oscillation at the second level; and, producing a test result signal dependent upon said determination.

6. The method of claim 5 wherein the step of determining is achieved by switching from the second to the first level and by measuring the time taken for the oscillator to provide the clock signal output.

7. A microprocessor system arranged for operating in a normal mode and in a standby mode, comprising a microprocessor arranged to receive a clock signal; an oscillator coupled to a power supply and arranged for oscillating in dependence upon the supply current; and, a switch arrangement connected between the oscillator and the power supply and arranged for selectively switching the power supply between first and second levels; wherein in the normal mode power is supplied at the first level to provide sufficient current to cause the oscillator to drive the clock signal to the microprocessor, and in the standby mode power is supplied at the second level to provide sufficient current to maintain oscillation and insufficient current to drive the clock signal to the microprocessor.

8. An oscillator circuit substantially as hereinbefore described and with reference to the drawings of FIGs. 1 and 3.

9. A method substantially as hereinbefore described and with reference to the drawings of FIGs. 1 and 3.

10. A microprocessor system substantially as hereinbefore described and with reference to the drawings of FIGs. 1 and 3.