GB2315963A - Trace-back control for Viterbi decoding - Google Patents

Abstract

The present invention relates to a trace-back controlling system and method for Viterbi decoding. The object of the present invention is to provide a trace-back controlling system and method in Viterbi decoding, which eliminates redundancies in the path memory to create a more efficient memory. According to the present invention, a determining bit, which to be stored in a path memory, can be converted into a parallel form according to the relative usage. A write address is generated in order to determine the location of said determining bit in said path memory. Finally, a read address is also generated in order to read the determining bit stored in the path memory during the trace-back.

Description

TRACE-BACK CONTROL SYSTEMS AND METHOD FOR VITERBI DECODING The present invention relates to a trace-back control system for Viterbi decoding, and more particularly, to a trace-back control method that allows a more efficient path memory to be used more efficiently by eliminating redundancies in the path memory used in a Viterbi decoder and a Viterbi equalizer.

In the general field of digital processing, much effort has been made in order to correct any error, such as static noise, which compromises reliability of communication. Such errors in communication travel through a primary medium called, a channel. As a result, in order to decrease the error rate on a given noisy channel, an error control coding (ECC) method has been widely used. Such error control coding is usually divided into two categories, block control coding (BCC) and convolutional coding. BCC corrects the errors in data by adding a block of redundancies containing information codes. The convolutional coding method operates by coding input data sequentially according to a coding algorithm.

Examples of BCC include Cyclic control coding, Both Chaudhuri-Hocquenghem control coding, and Reed-Solomon control coding etc. In terms of the actual method, an error is corrected during a decoding stage by making a set of blocks containing transmitted data from a wireless communication channel or a stored means.

On the other hand, by making a certain relationship with a previous data, said convolutional coding method corrects error in the inputted data, based on a coding algorithm. Unlike said block decoding, rather than making a set of blocks, a transmitted or detected data is decoded in order for receiving. Viterbi decoding is the most widely used decoding method.

Viterbi decoding is based on determining an optimal path in a trellis diagram. The optimal path is determined by selecting a path having the smallest margin of error such that the decoded data is closely similar to the transmitted or stored data. Moreover, Viterbi decoding is not only applied in a data decoder but also applied in an equalizer that estimates a level of distorted signal, such as static noise. Such equalizer is called, a Viterbi equalizer.

The following is an outline of the process involving Viterbi decoding.

First of all, data in parallel form is received based on a code rate. Using the parallel data, a metric of each path, which appears in said trellis diagram, is then calculated. Based on the continuation of incoming data, calculated metrics from the previous path are repeatedly accumulated. During the repeated process, a state is formed by metrics from different paths. At this point, only the path corresponding to the smallest accumulated metric is kept. The chosen path, a survivor, is then processed for another repeating process, and the rest of other paths are eliminated.

As mentioned above, Viterbi decoding applies to a method of decoding data which has the highest possibility of transmission. Such decoding method is also known as the maximum likelihood of decoding. However, this decoding method requires a long constraint length (generally, about six times longer than that of : the trellis control code). Moreover, this method requires storing of all the metrics from every path to a certain extent. Consequently, the production process is very complicated and expensive. As a result, in reality, it is not feasible for Viterbi decoding to be implemented. In order for Viterbi decoding to be implemented, a trace-back method should be employed, such that not all metrics from every path are stored. Only the metrics of a present state and a state from a path which leads to the previous state are stored for decoding the data from the previous path.

The following describes a structure of a Viterbi decoder employing said trace-back method by referring to Figure 1.

Figure 1 is a block view which briefly shows a conventional Viterbi decoder employing the trace-back method.

The conventional Viterbi decoder includes a branch metric calculator 1 that calculates branch metrics of each path from input data. The metric calculator 1 sends the branch metrics and states to the respective path metric to be accumulated. An add compare selection unit (ACSU) 2, in order to find the path corresponding to the smallest metric, compares each state formed by the accumulated metrics from different paths. Afterwards, the ACSU 2 sends a determining bit that can differentiate between the present state and the previous state. A metric memory 3 is used to store the survivor from the ACSU 2. The metric memory sends information to enable the ACSU 2 to use the previous path metrics during a repeat process. A path memory 4 stores the determining bit sent by the ACSU 2.

Finally, the decoder includes a trace-back control device 5 that conducts a trace-back process by using the determining bit stored in the path memory 4. Afterwards, the transmitted or detected information from the original data are decoded.

In the trellis diagram, which is formed based on a coding algorithm, there is a path which indicates a state transition based on time. Branch metrics of each path are different from each other. At this pint, the paths which are inputted as a state, the branch metrics of each path should be calculated. Especially, in case of a data in binary code, a path, which is inputted as a present state, is either 0 or 1.

As mentioned above, the branch metric calculating unit 1 in the Viterbi decoder employing the trace-back method must control both the trellis and input data in order to proceed with the process as described above.

Afterwards, said ACSU 2 receives the calculated branch metrics to be accumulated along with previously accumulated path metrics in said path memory 3. These metrics will be used as previous path metrics in the next stage of data receiving. Finally, among the paths recorded as a state, the path having the smallest said path metric is selected to be outputted to said path memory 4.

In case of decoding the second data, the path memory 4 receives the determining bit from the ACSU 2 to be stored in the respective memory. It is necessary to point out that the determining bit itself is only one bit.

Therefore, memory 4 requires memory capacity that has one data length and as many addresses as a path length multiplied by a number of states. More specifically, the formula for the address is NxP in which a number of states is represented by a letter N, and a path length is represented by a letter P. However, such kind of form of memory is not realistic. Therefore, the conventional Viterbi decoder adds a set of redundancies which has an optional value in respect to the determining bit. As a result, a memory capacity, which has a similar number of addresses and a particular row, is created.

The above method can be explained by relating this theory into a realistic situation. In Europe, Global System for Mobile Communication (GSM) is used for the mobile communication. In GSM, the constraint length of trellis decoding is 5 and uses 16 states and 30 - 35 path length of the Viterbi decoder. Therefore, it requires an address having a size of either 16x30 or 16x35. On the other hand, in the system used in the US or in Korea called, Code Division Multiple Access (CDMA), the constraint length of trellis decoding is 7, and it uses 64 states and 40 - 45 path length of the Viterbi decoder.

Therefore, it requires an address a size of either 64x40 or 64x45.

Figure 2a and Figure 2b illustrate a determining bit stored in each memory having one row. In the drawing, 4bit redundancies are added to the determining bit in the conventional Viterbi decoder. Moreover, in order to decode the transmitted data, the trace-back control device 5 uses the present state sent by the ACSU 2 to the path memory 4. Moreover, the determining bit stored in the path memory 4 for a repeated process of tracing the previous path is also used.

The following describes a conventional Viterbi decoding method, which employs the trace-back method.

The first step of the conventional Viterbi decoding method is calculating branch metrics step, in which branch metrics are calculated by using the input data. In the next step, the branch metrics and states are sent to the respective previous path metrics to be accumulated. In the next step called, add and compare selection step, in order to find a path corresponding to the smallest metric, each state made out of the accumulated metrics from different paths are compared. Afterwards, the selected path is outputted simultaneously. A metric storing step is to store the survivor from the add compare selecting step. Moreover, during the repeating process of data inputting, in order to use the previous path metrics during the repeating process of data inputting, the metrics are then sent back to the add-compare selection step. A path storing step is for storing the determining bit sent during the add compare selection step. The final step is called, a trace-back controlling step. During this step, the trace-back process is conducted to decode the originally transmitted data by using the determining bit stored during the path storing step.

In the metric calculating step of the Viterbi decoding method employing the trace-back as mentioned above, branch metrics of each path are calculated by using the input data. In the add-compare selecting step, the calculated path metrics from the path metric calculating step are received to be accumulated along with the previous path metrics accumulated from the metric storing step. Afterwards, in the path in which each state is received, the path corresponding to the smallest accumulated metrics is kept; then the survivor is sent for the path storing step. Finally, in the trace-back controlling step, transmitted data are decoded by searching the previous path repeatedly. During this step, present states, which were transferred from the addcompare selecting step to the path storing step, and the determining bit, which was stored from the path storing step, are used.

According to a conventional Viterbi decoder using the trace-back method, in order to store the determining bit, the path memory must have an appropriate form. Therefore, a series of redundancies must be assigned. Since these redundancies are not required fro the actual path searching, there is a decrease in efficiency of memory usage. Especially, in case of decoding the trellis codes, since addresses contain a large number of states and long paths, it is very difficult to execute decoding with only one chip.

It is an aim of embodiments of the present invention to relieve the draw backs as mentioned above by storing an appropriate determining bit in the path memory 4 where redundancies are located. Moreover, in order to process a trace-back process, an address is created for reading the determining bit stored in the path memory 4. As a result, embodiments of the present invention aim to provide a trace-back control system and method in Viterbi decoding, which increases the efficiency in memory usage.

In order to avoid a trace-back controlling system to have one data length memory, conventionally, redundancies are added to a path memory. According to aspects of the present invention, said appropriate determining bits are stored where redundancies are located.

Moreover, in order to use the trace-back method, an address is created for reading the determining bit stored in the path memory. As a result, usage of memory becomes more efficient.

According to a first aspect of the invention, there is provided a trace-back control system for a Viterbi decoder, which is characterized in that a determining bit received from an add-compare selection unit (ACSU) is stored in a path memory for conducting a trace-back in order to decode the original information, the system comprising: a) a data control device that either transfers or converts said determining bit received from said ACSU into a parallel form; b) an address control device that creates a write address for storing the data received from said data control device and creating a read address for processing a trace-back to output the decoded data; and c) a main control device that generates a control signal, which is sent to said data control device and to said address control device, for controlling their functions.

Preferably, said address control device comprises: a) a trace-back processing device that receives a state from said ACSU according to a control signal received from said main control device and then generates a previous state after receiving a determining bit stored in said path memory for outputting decoded data after repeating said steps as much as the path length; b) a write address creating device that determines a location in said path memory for storing the determining bit received from said ACSU either to be transferred unchanged or to be converted into a parallel form; and c) a read address generator that receives the previous state and the path length from said trace-back processing device and said write address creating device, respectively, in order to read said determining bit stored in said path memory to generate a read address.

Preferably, said trace-back processing device comprises: a) a determining bit control device that only selects and then outputs the desired determining bit in a determining vector which was read from said path memory; b) a state creating device that selects a path after repeating a process of receiving said determining bit and a state from said determining bit control device and said ACSU respectively as much as the path length to determine and to out a previous state to said determining bit control device; and c) a multiplexing device that decodes data relative to the path selected during said state creating step.

Said write address creating device may comprise: a) a state counter that generates an address corresponding to a state in said path memory address according to a signal from said main control device; and b) a path address counter that generates an address corresponding to the path length.

Said path address counter preferably adds a carryout, which was generated after said state counter finishes counting, to a clock.

Said read address creating device preferably comprises: a) a less significant read address creating device that receives a previous state from said state creating device f said trace-back processing device in order to determine a less significant bit in said read address; and b) a more significant read address creating device that receives a path length from said path address counter of said write address creating device in order to determine a more significant bit in said read address.

According to a second aspect of the invention, there is provided a trace-back control method for a viterbi decoder, wherein in order to process the trace-back and to send information a determining bit is received from an ACSU, and stored in a path memory to be used, the method comprising: a) a data controlling step wherein a determining bit received from said ACSU is either transferred unchanged or converted into a parallel form; b) an address controlling step wherein in order to store the received data in said storing step or to process the trace-back, a write address and a read address are created respectively, and decoded data is outputted; and c) a main controlling step wherein a control signal is generated and sent to said data controlling step or said address controlling step to control each function.

Said address controlling step preferably comprises: a) a trace-back processing step in which a state and said determining bit are received from said ACSU and said path storing step respectively according to a control signal sent by said main controlling step in order to generate the previous state and to output decoded data after repeating said process as much as the path length; b) a write address creating step in which a location of a data, which was either transferred unchanged or converted into a parallel form according to a control signal from said main controlling step, is determined in the path memory; and c) a read address generating step in which a previous state and a path length are received from said trace-back processing step and said write address creating step respectively, in order to generate a read address to read the determining bit stored in said path memory.

Said trace-back processing step preferably comprises: a) a determining bit controlling step in which only the desired determining bit is selected in the determining vector which was read from the path memory and then outputted; b) a state creating step in which said determining bit and a state are received from said determining bit controlling step and said ACSU respectively in order to determine and then to output the previous state to said determined bit controlling step for selecting a path after repeating said process as much as the path length; and c) a multiplexing step in which data in need of decoding in the path selected during said state creating step is decoded and then outputted.

Said write address creating step preferably comprises: a) a state counting step in which an address corresponding to an address from said path storing step is generated according to said control signal; and b) a path address counting step in which an address corresponding to the path length is generated.

In said path address counting step a carry out which is generated after the completion of one segment of counting during said state counting step, is -preferably used for counting.

Said read address creating step preferably comprises: a) a less significant read address creating step in which a previous state is received from said state creating step of said trace-back processing step in order to determine a less significant bit to a read address; and b) a more significant read address creating step in which a path length is received from said path address counting step of said write address creating step in order to determine a more significant read bit of a read address.

For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a block diagram of a conventional Viterbi decoding; Figure 2a is a schematic view of a conventional data stored in a path memory based on the first preferred embodiment; Figure 2b is a schematic view of a conventional data stored in a path memory based on the second preferred embodiment; Figure 3 is a block diagram of a path memory controlling system in Viterbi decoding according to an embodiment of the present invention; Figure 4 is a detailed block diagram of the address control device illustrated in Figure 3; Figure 5a is a schematic view of a data stored in a path memory according to a first preferred embodiment of the present invention; Figure 5b is a schematic view of a data stored in a path memory according to a second preferred embodiment of the present invention; and Figure 6 is a bit map of a write address and a read address in the memory which corresponds to the data stored in Figure 5b.

A trace-back controlling system in Viterbi decoding according to an embodiment of the present invention can be explained better by referring to Figure 3 and Figure 4.

Figure 3 is a block diagram showing, according to the present invention, only a trace-back control device 100 and a path memory device 40 which were illustrated as parts of the Viterbi decoder in Figure 1. Otherwise, all other blocks of the Viterbi decoder illustrated in Figure 3 are very similar to Figure 1.

The trace-back control system of the Viterbi decoder includes a data control device 110. The data control device 110 receives a determining bit from ACSU 2 of figure 1 for either transferring unchanged or converting into a parallel form. An address control device 120 creates a write address in order to store data received by the data control device to the data path memory 40, and a read address is also created in order to process a traceback. Afterwards, the control device 120 processes a trace-back and then outputs the decoded data. The system also includes a main control device 130, which sends a control signal to the data control device 110 and the address control device 120 to control each function block.

The main control device 130 feeds a control signal to the address control device 120 as shown in Figure 4.

Based on the control signal, the address control device 120 receives the states from the ACSU 2 and the determining bit stored in the path memory 40 to generate a previous state. A trace-back processing device 121 repeats the process as much as the path length for sending the decoded data. A write address creating device 122 is for determining the location for the determining bit, which was either transferred unchanged or converted into a parallel form by the data control device 110 of Figure 3, in the path memory 40. A read address creating device 123 receives the path length from the write address creating device 122 to create a read address for reading the determining bit stored in the path memory 40.

The trace-back processing device 121 includes a determining bit control device 121-1. The determining bit control device 121-1 selects a desired determining bit from a determining vector, which was read from the path memory 40. A state creating device 121-2 receives the determining bit from the determining bit control device 121-1 and a state from the ACSU 2. Afterwards, the determined previous state are sent to the determining bit control device 121-1. The state creating device 121-2 then selects a path after repeating the process as many times as required according to the path length. Finally, a multiplexer 121-3 is included to output the decoded data after the completion of decoding in the path selected by the state creating device 121-2.

The write address creating device 122 includes a state counter 122-1 and a path address counter 122-2. The state counter 122-1 generates an address corresponding to a state in the path memory 40. The path address counter 122-2 generates an address within the path length in the path memory 40 by using the carry-out generated after the state counter 122-1 finished counting one segment.

The read address creating device 123 includes a less significant read address creating device 123-1 and a more significant read address creating device 123-2. The less significant read address creating device 123-1 determines a less significant bit from the read address after receiving the previous state from the state creating device 121-2. The more significant read address creating device 123-2 determines a more significant bit from the read address after receiving a path length from the path address counter 122-2.

The following describes a process involving the trace-back controlling system of the Viterbi decoder according to the present invention by referring to the block diagrams of Figure 3 and Figure 4 and the examples of Figure 5 and Figure 6.

The data control device 110, as shown in figure 3, receives a determining bit in a linear form or a parallel form the ACSU 2 of Figure 1 to send the bit to the path memory 40 of Figure 3. At this moment, whether to convert the determining bit into a parallel form is solely determined by a field in which said data control device is involved.

In other words, when the data control device 110 is able to decode transmitted code just by using a determining bit having a predetermined value, as is the case in the Viterbi decoder, then the determining bit, which is received from ACSU 2, is converted into a parallel form. However, when the soft bits, which are used to enhance a reliability of the determining bit, are needed as in a Viterbi equalizer, then the determining bit and soft bits both must be stored in the path memory 40, simultaneously. As a result, said bits are transferred unchanged (in the same form as received).

In the address control device 120, in order to store the data which passed through the data control device 110 in the path memory 40, a write address is generated.

Moreover, a read address and decoded data are generated for processing a trace-back.

More specifically, the determining bit control device 121-1 of the trace-back processing device 121 shown in Figure 4 receives a determining vector which was stored in the path memory 40 by means of a read address generated by the read address creating device 123. Afterwards, a necessary determining bit is selected and sent to the state creating device 121-2.

The state creating device 121-2 receives the determining bit from the bit control device 121-1.

Moreover, the present state from the ACSU 2 is received and sent to the previous state. This process, which is repeated as much as the length of the path, depicts the necessary process to conduct the trace-back of the previous state.

The multiplexer 121-3 conducts the trace-back based on the previous state generated in the state creating device 121-2. Afterwards, by using the terminal state of the selected path, the data is decoded. The decoding process mentioned above is conducted on the trellis diagram, which relies on the code generating algorithm.

On the other hand, in the write address generator 122, shown in Figure 4, a write address is generated. The write address is generated in order to store the data that was transferred to the path memory 40 through the ACSU 2.

In other words, in order to store the data in the path memory 40, the write address state counter 122-1 determines a less significant bit in the write address.

Moreover, the path address counter 122-2 of the write address generator 122 determines a more significant bit in the write address.

The following describes a process of the Viterbi decoder generating a 16-state or 64-state write address.

The determining bit and the corresponding write address, which are stored in the path memory 40, are illustrated in Figure 5a and 5b.

First of all, as shown in Figure 5a, in case of a 16state Viterbi decoder, 16x4 memory form is used; 16x1 is not realistically feasible for storing the determining bit in the path memory 40. As a result, the data is stored in the most significant bit of the row, and a series of redundancies is added to the rest of bits.

Similarly, in case of a 64-state Viterbi decoder, 16x4 memory form is also used to store the determining bits. However, according to Figure 5, unlike the 16-state Viterbi decoding, the 64-state Viterbi decoding can store four determining bits to the corresponding write address.

At this point, the state counter 122-1 of the write address creating device 122 counts the 6-bit binary code from 000000b to llllllb. When counting is completed, the write address creating device 122 generates a carry out to the path address counter 122-2. As a result, the output from the path address counter 122-2 is increased by lb.

Simultaneously, only the middle 4* bit of the 6-bit binary code in the state counter 122-1 is used to determine the write address of the path memory 40 having a size of 16x4.

Moreover, the bit corresponding to the write address is determined by counting backwards from the most significant bit to the least significant bit. When the determined bit of the 19 state (01001lb) is stored in the path memory 40, a write address of the middle 4* bit (1001b) is generated.

Therefore, the most significant bit is 0, and the least significant bit is 1. By using the inverse parallel technique as mentioned above, 10b is generated. As a result, in the path memory, the determining bit of the 19th state is stored in the third row of 1001b.

For the path address counter which determines a more significant write address, the counting starts when a carry-out is received from the state counter 122-1. For the Viterbi decoder having 6-bit path length, the path address counter 122-2 begins to count from 000b to 101b.

Afterwards, the process is repeated back by counting again from 000b. Such trace-back is processed as much as the path length of the path address counter 122-2. Therefore, any previous bit exceeding the path length stored in the path memory 40, is deleted. Meanwhile, a new determining bit can be stored in the location formerly occupied by the deleted bits.

In the read address creating device 123, in order to ensure a previous state, which is necessary for-processing a trace-back, an address is generated to a location in which a determining bit is stored. The determining bit is for reading the previous state from the path memory 40.

When the less significant read address creating device 123-1 receives states from the state creating device 1212, a less significant 3-bit of the read address is generated. Simultaneously, when the more significant read address creating device 123-2 receives an address of the path memory from the path address counter 122-2, a more significant 3-bit of the read address is generated.

The following describes the process involving the read address creating device 123 by

At some point, if the state generated by the state creating device 121-2 is 10b, then the less significant 3bit, which was generated by the less significant read address creating device 123-1, remains as 010b. On the other hand, if the present path sent by the path address count 122-2 is from the third path, then the read address creating device 123-2 outputs more significant 3-bit of read address of Ollb. As a result, the read address (cntmp (5:0)), which parallels a less significant 3-bit and a more significant 3-bit, has a value of 011l01b. The most significant bit cntmp 5 of cntmp 5:0 and the least significant bit cntmp 0 is formed inversely. Afterwards, a control signal sbd 1:0 is generated for determining a necessary determining bit for the memory corresponding to the same address. A read data, which is sent from the path memory 40 to a determining bit input device 121-1, is the 29* read data.

At this moment, if the read data is 1, the state creating device 121-2 will output the previous state of Olb. However, if the read data is 0, then the state of 0Ob will be outputted. The previous state, which was generated in the state creating device 121-2, and the path address of the path memory 40, which was formed when the path address counter 122-2 performs down counting, are used to generate a new read address. This process is then repeated.

In order for all the operations mentioned above to function properly, the main control device 30, as illustrated in Figure 3 and 4, generates a clock signal and other necessary control signals.

The following describes the trace-back controlling method in Viterbi decoding according to the present invention.

The trace-back controlling method in Viterbi decoding according to the present invention includes several steps.

In a data controlling step, a determining bit is sent from an add-compare selecting step either to transfer the data unchanged or to convert the data into a parallel form. In an address controlling step, a write address, which is needed to store the data that transferred from the data controlling step during said path storing step, and a read address, which is necessary for processing the trace-back, are created. After the trace-back, a decoded data is outputted. The method includes a final step called, a main controlling step, in which a controlling signal is generated to the data controlling step and the address controlling step for controlling each function properly.

The address controlling step includes several steps as well. The first step is a trace-back processing step, in which a state is received from the add-compare selecting step according to the control signal sent from the main controlling step. When a determining bit stored in the path storing step is received, a previous state is generated. Moreover, this process is repeated as much as the length of the path in order to output decoded data.

During a next step called, a write address creating step, the determining bit is either transferred through the data controlling step or converted into a parallel form according to the control signal sent from the main controlling step. In order for this determining bit to be stored during the path storing step, a write address is created to determine a location of storage. The final step is called a read address generating step, in which, a previous state is received from the trace-back processing step. Moreover, a path length is received from the write address creating step and stored in the path storing step. Afterwards, a read address, which is necessary for reading the determining bit stored in the above step, is generated.

The trace-back processing step consists of a number of steps. The first step is called, a determining bit controlling step, in which only the determining bit required by the determining vector, which was read in the path storing step, is selected and then outputted. During the next step, called a state creating step, the determining bit received from the path storing step and the state received from the add-compare selecting step are used for determining and then generating a previous state.

Again, this process is repeated as much as the path length in order to select a path properly. The final step is called, a multiplexing step, in which the data in need of decoding is decoded and outputted to the path selected during the state creating step.

The write address creating step includes two steps.

In a state counting step, an address, which corresponds to the state of the address from the path storing step, is generated. Another step is called a path address counting step, in which the carry out from the state counting step is used to generate an address of the path storing step within the path length.

The read address creating step also includes two steps. A less significant read address creating step is one step, in which a less significant bit of the read address is determined by using an input of the previous state received from the state creating step of the trace back processing step. Another step is called, a more significant read address creating step, in which a more significant bit of the read address is determined by using an input of the path length received from the path address counting step of the write address creating step.

The following describes the trace-back controlling method in Viterbi decoding according to the present invention in more specific detail.

First of all, in the trace-back controlling method mentioned above based on the usable space, the data controlling step determines which form of the data should be sent to the path storing step. Therefore, the data is either transferred unchanged as in the same serial form received from the add-compare selecting step or converted into a parallel form.

Additionally, during the address controlling step, in order to store the data, which was transferred through from the controlling step to the path storing step, a necessary write address is generated. Moreover, in order to process the trace-back, a read address and decoded data are generated.

More specifically, during the determining bit controlling step of the trace-back processing step, a necessary determining bit is selected and then sent to the state creating step. This is processed by using the determining vector received from the path storing step; the vector corresponds to a read address is generated during the read address creating step. During the state creating step, the determining bit is received from the path bit controlling step. A present state is also received from the add-compare selecting step to generate a previous state. Again, this process is repeated as much as the path length. Finally, during the multiplexing step, the trace-back is processed based on the previous state generated during the state creating step.

Afterwards, the final state of the path selected from the trace-back is used to decode at the point of decoding.

On the other hand, during the write address generating step, in order to store the data, which was transferred from the add-compare selecting step and the path storing step, a parallel form is used. The less significant bit generated from the state counting step and the more significant bit generated from the path address counting step are formed in parallel. As shown in figure 5, the more/less significant bits have formed a write address of the path storing step having a size of 16x4.

This write address is then outputted.

Finally, during the read address creating step, in order to gain a previous state, which is necessary for processing the trace-back, an address corresponding to the location of the determining bit, which is for reading the previous state from the storing step is generated. In the less significant read address creating step, a state is received from the state creating step. Afterwards, a less significant bit (3-bit) of the read address is generated.

Simultaneously, in the more significant read address creating step, an address of the path storing step generated from the path address counting step.

Afterwards, a more significant bit (3-bit) is generated.

In the main control step, as illustrated in Figure 3 and Figure 4, a clock signal and other necessary controlling signals are generated for proficiently processing the trace-back controlling step.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (14)

1. A trace-back control system for a Viterbi decoder, which is characterized in that a determining bit received from an add-compare selection unit (ACSU) is stored in a path memory for conducting a trace-back in order to decode the original information, the system comprising: a) a data control device that either transfers or converts said determining bit received from said ACSU into a parallel form; b) an address control device that creates a write address for storing the data received from said data control device and creating a read address for processing a trace-back to output the decoded data; and c) a main control device that generates a control signal, which is sent to said data control device and to said address control device, for controlling their functions.

2. The trace-back controlling system according to claim 1, wherein said address control device comprises: a) a trace-back processing device that receives a state from said ACSU according to a control signal received from said main control device and then generates a previous state after receiving a determining bit stored in said path memory for outputting decoded data after repeating said steps as much as the path length; b) a write address creating device that determines a location in said path memory for storing the determining bit received from said ACSU either to be transferred unchanged or to be converted into a parallel form; and c) a read address generator that receives the previous state and the path length from said trace-back processing device and said write address creating device, respectively, in order to read said determining bit stored in said path memory to generate a read address.

3. The trace-back controlling system according to claim 2, wherein said trace-back processing device comprises: a) a determining bit control device that only selects and then outputs the desired determining bit in a determining vector which was read from said path memory; b) a state creating device that selects a path after repeating a process of receiving said determining bit and a state from said determining bit control device and said ACSU respectively as much as the path length to determine and to out a previous state to said determining bit control device; and c) a multiplexing device that decodes data relative to the path selected during said state creating step.

4. The trace-back controlling system according to claim 2 or 3, wherein said write address creating device comprises: a) a state counter that generates an address corresponding to a state in said path memory address according to a signal from said main control device; and b) a path address counter that generates an address corresponding to the path length.

5. The trace-back controlling system according to claim 4 wherein said path address counter adds a carry-out, which was generated after said state counter finishes counting, to a clock.

6. The trace-back controlling system according to claim 2, 3, 4 or 5, wherein said read address creating device comprises: a) a less significant read address creating device that receives a previous state from said state creating device of said trace-back processing device in order to determine a less significant bit in said read address; and b) a more significant read address creating device that receives a path length from said path address counter of said write address creating device in order to determine a more significant bit in said read address.

7. A trace-back control method for a Viterbi decoder, wherein in order to process the trace-back and to send information a determining bit is received from an ACSU, and stored in a path memory to be used, the method comprising: a) a data controlling step wherein a determining bit received from said ACSU is either transferred unchanged or converted into a parallel form; b) an address controlling step wherein in order to store the received data in said storing step or to process the trace-back, a write address and a read address are created respectively, and decoded data is outputted; and c) a main controlling step wherein a control signal is generated and sent to said data controlling step or said address controlling step to control each function.

8. The trace-back controlling method according to claim 7 wherein said address controlling step comprises: a) a trace-back processing step in which a state and said determining bit are received from said ACSU and said path storing step respectively according to a control signal sent by said main controlling step in order to generate the previous state and to output decoded data after repeating said process as much as the path length; b) a write address creating step in which a location of a data, which was either transferred unchanged or converted into a parallel form according to a control signal from said main controlling step, is determined in the path memory; and c) a read address generating step in which a previous state and a path length are received- from said trace-back processing step and said write address creating step respectively, in order to generate a read address to read the determining bit stored in said path memory.

9. The trace-back controlling system according to claim 8 wherein said trace-back processing step comprises: a) a determining bit controlling step in which only the desired determining bit is selected in the determining vector which was read from the path memory and then outputted; b) a state creating step in which said determining bit and a state are received from said determining bit controlling step and said ACSU respectively in order to determine and then to output the previous state to said determined bit controlling step for selecting a path after repeating said process as much as the path length; and c) a multiplexing step in which data in need of decoding in the path selected during said state creating step is decoded and then outputted.

10. The trace-back controlling method according to claim 8 or 9, wherein said write address creating step comprises: a) a state counting step in which an address corresponding to an address from said path storing step is generated according to said control signal; and b) a path address counting step in which an address corresponding to the path length is generated.

11. The trace-back controlling method according to claim 10, in which in said path address counting step a carry out which is generated after the completion of one segment of counting during said state counting step, is used for counting.

12. The trace-back controlling method according to claim 8, 9, 10 or 11, wherein said read address creating step comprises: a) a less significant read address creating step in which a previous state is received from said state creating step of said trace-back processing step in order to determine a less significant bit to a read address; and b) a more significant read address creating step in which a path length is received from said path address counting step of said write address creating step in order to determine a more significant read bit of a read address.

13. A trace-back controlling system substantially as herein described with reference to Figures 3 to 6.

14. A trace-back controlling method substantially as herein described with reference to Figures 3 to 6.