GB2313990A - Detecting errors in virtual paths with POH. - Google Patents

Abstract

Apparatus detects errors caused along a detection section within a communication network for a plurality of virtual paths established along the entire length of the detection section POH interface circuit (53) when connected at one end of the detection section to first- and second-direction lines of one of the virtual paths, detects errors in the connected virtual path within the detection section by using a path overhead of the connected virtual path; a first selector (51) selects one of the virtual paths and connects the first-direction line of the selected virtual path to the path overhead interface circuit; and a second selector (52) connects the seconddirection line of the virtual path selected by the first selector, to the path overhead interface circuit (53).

Description

DETECTING ERRORS WITHIN A C3 fEICCN NEn(RK The present invention relates to an apparatus for detecting errors for each of a plurality of virtual paths established along a designated section within a communication network, and for example to - an apparatus for performing tandem connection maintenance (TCM) for each lower-order path, such as VC-1, in a synchronous digital hierarchy (SDH) transmission path.

With recent progress in digital communication networks based on synchronous network design, the use of SDH apparatus has been increasing.

When constructing a network using SDH apparatus, the provision of a TCM facility becomes practically an essential requirement.

When there is a service path extending over different network suppliers, the TCM facility is used to monitor network communication quality in the section served by each individual network supplier.

TCM is performed, for example, by detecting reception errors in each virtual container (VC) at both ends of a virtual path established along a monitoring section, and by comparing the detection results obtained at both ends, thereby determining the presence or absence of new errors caused along the monitoring section and the number of such errors. More specifically, when the virtual container exiting from the monitoring section contains a certain number of errors, for example, if it is found that the virtual container entering the monitoring section contains the same number of errors, it is shown that the control section itself is free from errors. On the other hand, when the virtual container exiting from the monitoring section contains errors despite no errors being contained in the virtual container entering it, this means that there is some sort of fault in the monitoring section. In this way, when a fault occurs in a path established extending over different network elements served by different network suppliers, it is possible to distinguish the responsible network supplier from other suppliers.

To accomplish this processing, it is necessary to transmit the error detection result at one end of the path in the monitoring section to the other end either by using a path overhead of a VC being carried in the same direction as the transporting direction of the VC under inspection or by using a path overhead of a VC being carried in the opposite direction to the transporting direction of the VC under inspection. For higher-order paths such as the VC3/VC4 paths conforming to CCITT recommendations and the STS-1 path used in SONET under ANSI standards in North America, work is in progress for the standardization of TCM for transmission of detection results by a data link method using an overhead bit, conforming to the LAPD protocol.

However, for lower-order paths, since the number of paths accommodated in one transmission path is large (for example, one VC-4 contains 21 VC-12's), the same technique as used for higher-order paths would require extremely large circuitry, and is therefore impracticable. Under such circumstances, work on standardization has so far seen little progress.

On the other hand, in the lower-order path TCM method currently under study by CCITT, the Z6 byte of a lower-order path is assigned to TCM bits, with the more significant three bits defined as the incoming error count (IEC) and the less significant five bits as the tandem connection data channel, for transmission of the IEC. This method is simple compared to the technique used for higher-order paths.

However, with the lower-order path TCM method under study by CCITT, each time the 26 byte is changed for transmission of IEC when performing TCM on a path, the result of BIP (Bit Interleave Parity) -2 indicating the parity calculation result also changes, requiring recalculation and reinsertion, and hence the problem of increased circuit complexity.

It is desirable to provide a TCM method and apparatus, wherein the need for recalculation of BIP-2 is eliminated even when performing TCM on a lower-order path, thereby providing inexpensive TCM for an SDH apparatus while achieving a reduction in circuit complexity.

According to a first aspect of the invention, there is provided an apparatus for detecting errors caused along a detection section within a communication network for a plurality of virtual paths established along the entire length of the detection section, comprising: a path overhead interface circuit which, when connected at one end of the detection section to first- and second-direction lines of one of said plurality of virtual paths, detects errors in said connected virtual path within said detection section by using a path overhead of said connected virtual path; a first selector for selecting one of said plurality of virtual paths and connecting said first-direction line of said selected virtual path to said path overhead interface circuit; and a second selector for connecting said second-direction line of said virtual path selected by said first selector to said path overhead interface circuit.

According to a second aspect of the present invention there is provided an apparatus for detecting errors caused along a detection section within a communication network for a plurality of virtual paths established along the entire length of the detection section, comprising: a plurality of path overhead interface circuits each of which, when connected at one end of a detection section to first- and seconddirection lines of one virtual path, detects errors in said connected virtual path within said detection section; a first matrix switch for selecting a number of virtual paths from among said plurality of virtual paths and connecting the first-direction lines of said selected virtual paths respectively to said path overhead interface circuits; and a second matrix switch for connecting the second-direction lines of said virtual paths selected by said first matrix switch respectively to said path overhead interface circuits.

Reference will now be made, by way of example to the accompanying drawings, in which: Fig. 1 is a diagram showing an example of a network configuration to which an embodiment of the present invention is applicable; Fig. 2 is a block diagram showing a detailed configuration of a POH (path overhead) interface circuit 13, 14 useful for understanding the invention; Fig. 3 is a diagram showing an example of a POHa format useful for understanding the invention; Fig. 4 is a diagram for explaining the operation of the circuit of Fig. 2; Fig. 5 is a block diagram showing another configuration of the POH interface circuit 13, 14; Fig. 6 is a diagram showing an example of the POHa format applicable to the circuit of Fig. 5; Fig. 7 is a diagram showing an example of another POHa format; Fig. 8 is a diagram showing an example of a switch select method in a first eixdimfflt of the invention; Fig. 9 is a diagram showing an example of a switch select method in a second eixdissk of the invention; and Fig. 10 is a block diagram of an SDH apparatus to which an embodiment of the present invention is applied.

Fig. 1 shows an example of a network configuration, in which reference numerals 11 and 12 designate network elements belonging to different networks A and B and having POH interface circuits 13 and 14, respectively. With a TCM section set up between the network elements 11 and 12, the POH interface circuits 13 and 14, monitor errors occurring along this section by using a POHa byter a path overhead byte (including the Z6 byte) undefined by CCITT recommendations.

In the network element 11, a received lower-order virtual container LOVC-RlA intended in a first direction from network A to network B enters the POH interface 13, where it undergoes POHa byte processing and is converted into a transmit lower order virtual container LOVC-S1A for transmission to the network element 12. In the network element 12, a received lower-order virtual container LOVC-R1B enters the POH interface 14, where it undergoes POHa byte processing and is converted into a transmit lowerorder virtual container LOVC-S1B for transmission onto the network B.

Likewise, a received lower-order virtual container LOVC-R2B intended in a second direction from network B to network A undergoes POHa processing in the network element 12 for conversion into a transmit lower-order virtual container LOVC-S2B, and in the network element 11, a received lower-order virtual container LOVC-R2A undergoes POHa processing for conversion into a transmit lower-order virtual container LOVC-S2A.

Fig. 2 is useful for understanding the present invention. A detailed configuration of the POH interface circuit 13, 14 in Fig. 1 is shown here.

In Fig. 2, POHa extractors 21 and 22 extract received path overheads R-POHal and R-POHa2 from the received lower-order virtual containers LOVC-R1 and LOVC-R2, respectively.

POHa inserters 23 and 24 insert transmit path overheads S-POHal and S-POHa2 into the transmit lowerorder virtual containers LOVC-S1 and LOVC-S2, respectively.

BIP-2 error detectors 25 and 26 detect received error counts R-ERR1 and R-ERR2 by using the bit interleave parity (BIP-2) of V5 byte in the path overheads (POH) of the received lower-order virtual containers LOVC-R1 and LOVC-R2, respectively.

IEC detectors 27 and 28 extract incoming error counts (IEC) from the received path overheads R-POHal and R-POHa2, respectively.

Arithmetic circuits 29 and 30, respectively, perform arithmetic operations to calculate the number of errors (F-IEC) caused along the TCM section by reference to the reception error counts R-ERR1, R-ERR2 detected from the received lower-order virtual containers LOVC-Rl, LOVC-R2 and the IECs extracted from the received path overheads R-POHal1 R-POHa2.

Combiners 31 and 32, respectively, combine the reception error counts R-EER1, R-ERR2 in the received lower-order virtual containers LOVC-Rl, LOVC-R2 with the respective F-IECs in the received lower-order virtual containers LOVC-R2, LOVC-R1 transported in the opposite direction, to obtain a POHa format.

Compensators 33 and 34, respectively, compare the received path overheads R-POHal, R-POHa2 with the POHa's fed from the respective combiners; each compensator generates a parity compensation bit COMP and appends it to the POHa fed from the associated combiners so that the parity of the POHa fed from the associated combiners becomes equal to the parity of the received POHa. The transmit path overheads S-POHal, S-POHa2 are thus produced.

F-IEC detectors 35 and 36 extract F-IECs from the received path overheads R-POHal and R-POHa2, respectively. Counters 37 and 38 totalize the F-IEC values being fed from the F-IEC detectors 35 and 36, respectively.

Fig. 3 shows an example of the POHa format. As shown, three bits are assigned to the incoming error count (IEC), two bits to the parity compensation bits (COMP), and three bits to the TCM section error count (F-IEC).

Fig. 4 is a diagram for explaining the TCM operation of the POH interface circuits 13, 14 shown in Figs. 1 and 2.

In Fig. 4, the BIP-2 error detector 25 detects the reception error count R-ERR1 from LOVC of the received lower-order virtual container LOVC-R1A intended in the first direction. The reception error count, R-ERR1, is fed to the combiner 31 as the incoming error count IEC. At the same time, the error count F-IEC (to be described later), which represents the number of errors caused along the TCM section in the second direction, is supplied to the combiner 31.

The combiner 31 passes the incoming error count IEC and the error count F-IEC to the compensator 33.

By reference to the parity of the received path overhead R-POHal extracted by the POHa extractor 21, the compensator 33 sets the fifth bit to 0 or 1, whichever makes the parity for the odd-numbered bits (bit 1, 3, 5 and 7) in the input from the combiner 31 equal to the parity for the odd bits in R-POHa1, and sets the fourth bit to 0 or 1, whichever makes the parity for the even-numbered bits (bit 2, 4, 6 and 8) equal to the parity for the even bits in the R-POHa1, thereby forming the transmit path overhead S-POHal The POHa inserter 23 inserts the S-POHal into the signal transferred from the POHa extractor 21, to form LOVC of the transmit lower-order virtual container LOVC-S1A. Thus, the parity of the transmit lowerorder virtual container LOVC-S1A becomes the same as the parity of the received lower-order virtual container LOVC-RlA, so that there is no need to recalculate BIP-2.

In Fig. 4, the transmit lower-order virtual container LOVC-SlA transmitted from the POH interface circuit 13 is input to the POH interface circuit 14 as the received lower-order virtual container LOVG-RlB.

The BIP-2 error detector 25' detects the reception error count R-ERR1 from the received lowerorder virtual container LOVC-RlB, and the POHa extractor 21' extracts the path overhead R-POHa1.

Further, the IEC detector 27' extracts the incoming error count IEC from R-POHa1. In the arithmetic circuit 29', the IEC extracted by the IEC detector 27' is subtracted from the reception error count R-ERR1 detected by the BIP-2 error detector 25', and the result is output as F-IEC.

The F-IEC output from the arithmetic circuit 29' represents the difference between the number of errors detected at the input of the network element 11 and that detected at the input of the network element 12, and this difference indicates the number of errors caused along the TCM section in the first direction.

The F-IEC is passed through the combiner 32', the compensator 34', and the POHa inserter 24', and inserted into the transmit lower-order virtual container LOVC-S2B to be transmitted in the second direction.

The transmit lower-order virtual container LOVC S2B transmitted from the POH interface circuit 14 is input to the POH interface circuit 13 as the received lower-order virtual container LOVC-R2A.

The POHa extractor 22 extracts the received path overhead R-POHa2 from the received lower-order virtual container LOVC-R2A transported along the second direction, and then, the F-IEC detector 36 extracts F IEC from R-POHa2. The F-IEC thus extracted represents the number of errors per frame of the low-order LOVC, detected at the POH interface 14. This error count varies from frame to frame.

The counter 38 totalizes the F-IEC counts for one frame period. The number of errors that can be detected by BIP-2 is two per frame; therefore, the counter 38 need only have a maximum counting capacity equal to 2 x frame frequency x n (seconds). An MPU (not shown) having an error count display function reads the count value from the counter 38 and displays it on a man-machine interface.

With the above sequence of operations, the network element 11 can monitor the errors that have occurred in the virtual container during transmission from the network element 11 to the network element 12.

Since the POH interfaces 13 and 14 are symmetrical in configuration as shown in Fig. 2, it will be easily understood that monitoring of errors for a virtual container transported in the opposite direction can be accomplished in the same manner as described above.

TCM is effective in situations where errors occur, but error indications would be rendered useless unless reliability is ensured for IEC and F-IEC.

Fig. 5 shows a M interface circuit where provisions are made to verify the reliability of IEC and F-IEC. The same parts as those shown in Fig. 2 are designated by the same reference numerals.

The numerals 39 and 40 are parity detectors for detecting the parity of the received path overheads R-POHal and R-POHa2, respectively. The numerals 41 and 42 are parity bit adders for adding parity bits to the transmit path overheads S-POHal and S-POHa2, respectively.

Fig. 6 shows the POHa format in the circuit of Figure 5. In the figure, P indicates the parity bit for IEC and F-IEC, appended to increase reliability.

In Fig. 5, the parity detector 39 calculates the parity of the received path overhead R-POHal extracted by the POHa extractor 21, while the parity detector 40 calculates the parity of the received path overhead R-POHa2 extracted by the POHa extractor 22. The parity bit adder 41 adds parity bits to the transmit path overhead S-POHal to be inserted by the POHa inserter 23, while the parity bit adder 42 adds parity bits to the transmit path overhead S-POHa2 to be inserted by the POHa inserter 24.

Fig. 7 shows a POHa format used as an alternative to the format of Figure 6. In the figure, P1 and P2 are parity bits separately appended to IEC and F-IEC, respectively.

In the case of the received lower-order virtual container LOVC-R2A in the network element 11 shown in Fig. 1, the IEC carried therein is transmitted in the second direction and represents the number of errors contained in the received lower-order virtual container LoVC-R2B in the network element 12, while the F-IEC represents the number of errors caused along the TCM section in the first direction. Thus IEC and F-IEC have meanings independently of each other; therefore, in a case where there is a parity error in IEC, for example, if there is no parity error in F-IEC, the TCM section can be considered as having been monitored normally. Thus the format shown in Fig. 7 provides better TCM performance than the format shown in Fig. 6.

The TCM facility can be realized with a simple hardware configuration, by using the technique disclosed in either circuit shown in Fig. 2 or Fig. 5. However, in the case of a large-capacity transmission path such as STM-16, there are 1008 paths at the VC12 level, in which case the circuitry of the entire apparatus becomes large. Also, within a single apparatus, no such situations are generally expected where TCM is set for all the lower-order paths. Tb reduce the circuit size, the present invention provides a common POH interface circuit for a number of lowerorder paths, and a switch for switching between the paths.

Fig. 8 shows a first switch select method for the POH interface circuit, as a first eSxdi - t of the present invention. The switch (selector) to be used is not limited to the 1:4 configuration, shown here, but any 1:z configuration can be used for a further reduction in size.

The numerals 51 and 52 are selectors. Any one of the four lower-order paths LOVC#1 - LOVE#4 can be selected for connection to the POH interface circuit 53 to perform TCM. Therefore, according to the method of Fig. 8, the circuitry necessary for TCM can be reduced in size.

Using a plurality of such selectors as shown in Fig. 8, TCM can be performed on each lower-order path within the apparatus. However, if the value z is made extremely large, the circuit size can be reduced, but the number of paths on which TCM can be performed will also be reduced. Furthermore, since TCM cannot be performed simultaneously on the lower-order paths accommodated in the same selector, operational constraints will arise.

Fig. 9 shows a second ttodbtent of the invention (switch select rod.), wherein an x:y (x > y) matrix switch is provided between the lower-order paths and the POH interface circuit.

The numerals 55 and 56 are selectors each consisting of x switches. Using these switches, x lower-order paths, LOVG#l - LOVC#x, are selectively connected to MSWs 57 and 58. The MSWs 57 and 58 select arbitrary ports from x pairs of ports for connection to y pairs of ports, while short-circuiting the unselected ports. The numerals 591 to 59y indicate a number, y, of POH interface circuits which perform TCM on the y lower-order paths selected by the MSWs 57 and 58, respectively.

According to the method shown in Fig. 9, since arbitrarily selected lower-order paths can be connected to the POH interface circuits in a flexible manner, operational constraints can be eliminated.

The matrix switch is larger in circuit size than the selector, but in terms of circuit configuration, it can be constructed from a simple combination of gate circuits. Using gate array and similar technology, a compact, low-cost matrix switch can be realized.

Fig. 10 is a block diagram showing the configuration of an SDH apparatus.

In the figure, the numerals 61 and 62 are STM-N signal receivers; 63 and 64 are AU-4 signal receivers; 65 and 66 are HOVC receivers; 67 and 68 are TU signal receivers; 69 and 70 are LOVC sections; 71 is a POH interface circuit; 72 and 73 are TU signal transmitters; 74 and 75 are. HOVC transmitters; 76 and 77 are AU-4 signal transmitters; and 78 and 79 are STM-N signal transmitters.

In any of the above-described configurations, the number of reception errors, detected at the start point of a virtual container intended for transportation along the monitoring section, is transmitted to the end point, where the number of reception errors detected at the start point is subtracted from the number of reception errors detected at the end point, to calculate the number of errors caused along the monitoring section; then, the result of the calculation is carried in a virtual container to be transported in the opposite direction and is thus transmitted to the start point where the result is displayed. In an alternative configuration, the number of errors caused along the monitoring section and calculated at the end point may be displayed at the end point instead of returning it to the start point for display. In still another configuration, the number of errors detected at the end point may be transmitted to the start point by using a virtual container to be transported in the opposite direction, and the number of errors caused along the control section may be calculated at the start point. In such configurations, F-IEC need not be transmitted; in either case, if parity compensation bits COMP are used so that the BIP-2 calculation result of the entire virtual container remains unchanged, recalculation of BIP-2 is not necessary.

Claims (3)

1 . An apparatus for detecting errors caused along a detection section within a communication network for a plurality of virtual paths established along the entire length of the detection section, comprising: a path overhead (POH) interface circuit which, when connected at one end of the detection section to first- and second-direction lines of one of said plurality of virtual paths, detects errors in said connected virtual path within said detection section by using a path overhead of said connected virtual path; a first selector for selecting one of said plurality of virtual paths and connecting said first-direction line of said selected virtual path to said path overhead interface circuit; and a second selector for connecting said second-direction line of said virtual path selected by said first selector to said path overhead interface circuit.

2. An apparatus for detecting errors caused along a detection section within a communication network for a plurality of virtual paths established along the entire length of the detection section, comprising: a plurality of path overhead (POH) interface circuits each of which, when connected at one end of a detection section to first- and second-direction lines of one virtual path, detects errors in said connected virtual path within said detection section; a first matrix switch for selecting a number of virtual paths from among said plurality of virtual paths and connecting the first-direction lines of said selected virtual paths respectively to said path overhead interface circuits; and a second matrix switch for connecting the second-direction lines of said virtual paths selected by said first matrix switch respectively to said path overhead interface circuits.

3. A method of detecting errors caused along a detection section within a carnuriication network, substantially as hereinbefore described with reference to Figures 8 and 9 of the acccmpanying drawings.