GB2311673A

GB2311673A - Digital circuit with modulated clock

Info

Publication number: GB2311673A
Application number: GB9606722A
Authority: GB
Inventors: Peter James Hicks
Original assignee: Advanced Risc Machines Ltd
Current assignee: ARM Ltd
Priority date: 1996-03-29
Filing date: 1996-03-29
Publication date: 1997-10-01
Anticipated expiration: 2016-03-29
Also published as: GB2311673B; GB9606722D0

Description

CLOCKED ELECTRONIC CIRCUIT This invention relates to data processing systems and clock signals applied thereto.

Modern data processing systems typically comprise at least one digital circuit.

That digital circuit may often be a microprocessor of some description. It is known to provide microprocessors capable of running at a number of different clock speeds.

The clock speed of a microprocessor dictates the speed at which instructions are processed- by that microprocessor. For example, a clock speed of 25 megahertz (MHz), means that the microprocessor concerned is capable of processing a maximum of 25 million instructions per second, if each instruction requires only one clock cycle to complete.

A particular microprocessor is limited to a maximum clock speed which is governed by many factors including time delays for signal propagation and read/write operations and the like. In some cases the design is such that a microprocessor may be clocked at any speed ranging below the maximum clock speed of that microprocessor without data loss or timing problems occurring.

An example of such a microprocessor is the Advanced Risc Machines ARM6 microprocessor. The ARM6 series of microprocessors includes a variety of microprocessors that may have on chip memory management units and cache memories, for example. The ARM6 microprocessor is particularly resilient to clock speed variation and is even capable of static operation i.e. to the clock being stopped completely and then restarted. That is to say, that the ARM6 microprocessors are capable of stopping the clock, ceasing all operations and greatly reducing power consumption until a signal is received that instructs the microprocessor to resume operations. These particular ARM6 microprocessors also have a small physical size.

The small physical size of the ARM6 microprocessors and their low power consumption renders them extremely suitable for a number of applications. In particular, the ARM6 microprocessors are particularly well suited for applications where space and power are at a premium, such as mobile communications, electronic sensing and the like.

In the field of mobile telecommunications, a number of problems have been ndted with regard to the growing requirements for the provision of a digital mobile telecommunication network. Digital mobile telephones and pagers commonly use microprocessors to conduct digital signal processing or to control separate digital signal processing logic units. Typically, these microprocessors are clocked at frequencies that may be as high as 25 MHz or higher. These high frequency clocked microprocessors are housed within the device (which is desirably compact) and accordingly in close proximity to an aerial which receives and transmits digital signals. Such an arrangement causes interference problems between the aerial and the microprocessor. In particular, it has been found that the clock signals can induce high frequency harmonics which interfere with signals received by the aerial.

Known techniques for reducing this interference include surrounding the microprocessor with screening material (size and weight penalty) and attempting to align the clock signals with gaps in the received signal frequency spectrum (constraining other design parameters).

In accordance with a first aspect of the present invention, there is provided an apparatus for processing data comprising: a frequency control circuit; a clock signal generator for generating a clock signal; and a digital circuit driven by said clock signal; wherein said clock signal generator generates clock signals within a range of frequencies and said frequency control circuit controls the frequency at which said clock signal is generated to substantially continuously vary within said range.

The present invention helps to alleviate the problems associated with the prior art by providing a system in which noise induced by the clock signal is spread more widely across the frequency spectrum and accordingly is of a relatively low amplitude when compared to the amplitude of the received signals.

In this aspect, it is preferred that the clock signal generator comprises a voltage controlled oscillator for generating said clock signal under control of a control signal generated by said frequency control circuit, wherein said control signal controls said voltage controlled oscillator to substantially continuously vary said clock signal.

In accordance with a second aspect of the present invention, there is provided a radio telecommunications apparatus comprising: a radio receiving circuit for receiving radio telecommunications signals; a clock signal generator for generating a clock signal; and a digital circuit driven by said clock signal; wherein said clock signal has a substantially continuously varying frequency.

As mentioned above, the frequency at which said clock signal is generated may be varied from substantially zero hertz up to the maximum clock speed of the digital circuit to be clocked.

In this second aspect. the radio telecommunications apparatus may comprise a handheld portable device.

In addition, the digital circuit may comprise a digital signal microprocessor.

In any case, it is preferred that the clock signal generator comprises a voltage controlled oscillator for generating said clock signal under control of a control signal, and a frequency control circuit for generating said control signal, wherein said control signal controls said voltage controlled oscillator to substantially continuously vary said clock signal.

In either of the above aspects, the frequency control circuit may generate sine waves, ramp waves or triangular waves.

In addition, in either of the above aspects, it is preferred that the digital circuit is such that the clock signal may be stopped and restarted without loss of data. I n which case, the digital circuit may be a central processing unit core.

Viewed from a further aspect the present invention also provides a method of processing data comprising the steps of: (a) generating a clock signal with a clock signal generator; and (b) driving a digital circuit with said clock signal; wherein said clock signal has a substantially continuously varying frequency, said continuously varying frequency being controlled by a frequency control circuit.

A still further aspect of the invention provides a method of clocking a radio telecommunications apparatus, the method comprising the steps of: (a) generating a clock signal with a clock signal generator; and (b) driving a digital circuit with said clock signal; wherein said clock signal has a substantially continuously varying frequency.

The present invention will now be described, by way of example only, with reference to the appended drawings, in which like numerals represent like parts and in which: Figure la illustrates a schematic representation of a clock signal according to the prior art, Figure ib illustrates a schematic representation of a clock signal according to the present technique, Figure 2 shows a schematic representation of an exemplary circuit that may be used to generate the clock signal of Figure ib, Figure 3 shows a schematic representation of the frequency spectrum of a clock signal as shown in Figure la when modulated by a sine wave, for example; and Figure 4 shows a schematic representation of a Voltage Controlled Oscillator.

With reference to Figure 1(a), a conventional clock signal 1 is shown. As illustrated, this conventional signal 1 comprises a series over time "t" of pulses 3.

For example only, the signal is shown as having a pulse width "r", amplitude "A" and period "top". Each of these pulses 3, when received by a logic circuit 5 (shown in Figure 2), cause that logic circuit to execute a processing cycle.

Figure 1(b) illustrates a clock signal 10 according to the present technique.

The clock signal 10 comprises a series of pulses 12 of constant amplitude "A", but with differing pulse widths "T" and periods "tp". Hereinafter, the clock signal 10 according to the present technique will be generally designated as a clock signal.

Figure 2 illustrates an exemplary circuit embodying the present technique.

With reference to Figure 2, the logic unit 5 is connected to a voltage controlled oscillator (VCO) 12, which is in turn connected to a low frequency signal source 14.

In operation, the low frequency source 14 drives the VCO 12 to produce the above mentioned signal 10. The low frequency source may produce a number of differing drive waves which may be sine waves, triangular or ramp waves, for example. The exact shape of the drive waves is not important, it is only important that the drive waves have some voltage variation over time.

In this way, the circuit operates in an open loop (due to the lack of any feedback) to produce, in effect, a frequency modulated clock signal akin to the signal described above.

The signal 10 is similar to the conventional signal 1, except that each peak of the signal 10 has been displaced from the corresponding peak of the conventional signal 1 by a randomly varying frequency amount. Thus the signal 10 may be considered to be the result of modulating a notional carrier signal (having a constant frequency and a waveform similar to that of Figure 1(a)) with a signal having a continuously varying frequency (i.e. a continuously varying dispjacement from the carrier signal).

If the conventional signal 1 of frequency f= 1/tp were to be modulated with a sine wave, then the resulting frequency spectrum of the modulated signal would look like an infinite series of regularly spaced pulses. Such a frequency spectrum is shown in Figure 3. The largest pulse is attributable to the carrier wave frequency f, the smaller pulses being sidebands thereof and attributable to harmonics (generated at multiples of f) of the carrier wave frequency. Each sideband pulse has an amplitude dependent upon a Bessel function and thus, successive pulses decrease in amplitude.

Changing the modulating frequency gives rise to a different series of pulses having a different amplitude and appearing at different frequencies.

Thus, as the signal 10 is the result of modulating a notional carrier signal with a signal having a continuously varying frequency, the corresponding frequency spectrum would comprise an infinite series of pulses for each modulating frequency.

Thus, the clock signal is smeared throughout the frequency spectrum and sidebands of the various frequency signals all reduce in amplitude.

To summarise, the present technique employs a clock signal that has a frequency spectrum that is spread right across the frequency range and has a dramatically reduced amplitude when compared to that of the frequency spectrum ot a traditional clock signal 1.

Clocking a digital circuit with a clock signal as described above allows devices to be manufactured that need less or even no protective shielding around the clocked circuits. The absence of this shielding provides a weight and size advantage to any apparatus that incorporates such a system therein.

Figure 4 shows an exemplary circuit diagram of a VCO. Driving the Figure 4 VCO with a constant voltage Vjn gives rise to an output signal VOUL that has a square waveform with a frequency dependent on the ratio of Vjn/V+. Substituting the constant Vjn voltage with a sine wave, for example, would give an output signal V that maintained its square waveform but had a varying frequency i.e. a signal that could be used as a clock signal for driving a logic unit as in the present technique.

It will be understood, of course, that the present invention has been described above by way of example only and that modifications may be made within the scope of the appended claims.

For example, the use of a VCO is not essential to this invention. Other signal generators may be utilised to provide a suitable clock signal. However, these other signal generators would also need to exhibit some frequency independent characteristics in order to minimise any cross talk between received signals and the clock signal.

In addition, whilst embodiments of the present invention have been discussed above in relation to the field of telecommunications. it will be apparent that the present techniques may be applied to other fields in which Radio Frequency Interference from clocked circuits is a problem.

Claims

1. Apparatus for processing data comprising: a frequency control circuit; a clock signal generator for generating a clock signal; and a digital circuit driven by said clock signal; wherein said clock signal generator generates clock signals within a range of frequencies and said frequency control circuit controls the frequency at which said clock signal is generated to substantially continuously vary within said range.

2. Apparatus for processing data according to Claim 1 wherein said clock signal generator comprises a voltage controlled oscillator for generating said clock signal under control of a control signal generated by said frequency control circuit, wherein said control signal controls said voltage controlled oscillator to substantially continuously vary said clock signal.

3. A radio telecommunications apparatus comprising: a radio receiving circuit for receiving radio telecommunications signals; a clock signal generator for generating a clock signal; and a digital circuit driven by said clock signal; wherein said clock signal has a substantially continuously varying frequency.

4. A radio telecommunications apparatus according to Claim 3, wherein said telecommunications apparatus comprises a handheld portable device.

5. A telecommunications apparatus according to Claim 3 or Claim 4 wherein said digital circuit comprises a digital signal microprocessor.

6. Apparatus according to any one of Claims 3 to 5 wherein said clock signal generator comprises a voltage controlled oscillator for generating said clock signal under control of a control signal, and a frequency control circuit for generating said control signal, wherein said control signal controls said voltage controlled oscillator to substantially continuously vary said clock signal.

7. Apparatus according to any one of Claims 2 to 6 wherein said frequency control circuit generates sine waves.

8. Apparatus according to any one of Claims 2 to 6 wherein said frequency control circuit generates ramp waves.

9. Apparatus according to any one of Claims 2 to 6 wherein said frequency control circuit generates triangular waves.

10. Apparatus according to any one of the preceding Claims, wherein said digital circuit is such that said clock signal may be stopped and restarted without loss of data.

11. Apparatus according to any one of the preceding Claims wherein said digital circuit is a central processing unit core.

12. A method of processing data comprising the steps of: (a) generating a clock signal with a clock signal generator; and (b) driving a digital circuit with said clock signal; wherein said clock signal has a substantially continuously varying frequency, said continuously varying frequency being controlled by a frequency control circuit.

13. A method of clocking a radio telecommunications apparatus, the method comprising the steps of: (a) generating a clock signal with a clock signal generator; and (b) driving a digital circuit with said clock signal; wherein said clock signal has a substantially continuously varying frequency.

14. Apparatus for processing data substantially as hereinbefore described and as shown in the accompanying drawings.

15. A radio telecommunications apparatus substantially as hereinbefore described and as shown in the accompanying drawings.

16. A method of processing data substantially as hereinbefore described and as shown in the accompanying drawings.

17. A method of clocking a radio telecommunications apparatus substantially as hereinbefore described and as shown in the accompanying drawings.