GB2311632B - An enciphering process for the multiplication modulo N of two binary numbers - Google Patents
An enciphering process for the multiplication modulo N of two binary numbersInfo
- Publication number
- GB2311632B GB2311632B GB8824624A GB8824624A GB2311632B GB 2311632 B GB2311632 B GB 2311632B GB 8824624 A GB8824624 A GB 8824624A GB 8824624 A GB8824624 A GB 8824624A GB 2311632 B GB2311632 B GB 2311632B
- Authority
- GB
- United Kingdom
- Prior art keywords
- binary numbers
- multiplication modulo
- enciphering process
- enciphering
- modulo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/722—Modular multiplication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/723—Modular exponentiation
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8714668A FR2738365A1 (en) | 1987-10-23 | 1987-10-23 | Modulo N multiplication of two binary numbers and application to exponentiation for public key encryption |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8824624D0 GB8824624D0 (en) | 1997-07-16 |
GB2311632A GB2311632A (en) | 1997-10-01 |
GB2311632B true GB2311632B (en) | 1998-01-14 |
Family
ID=9356103
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8824624A Expired - Fee Related GB2311632B (en) | 1987-10-23 | 1988-10-20 | An enciphering process for the multiplication modulo N of two binary numbers |
Country Status (3)
Country | Link |
---|---|
DE (1) | DE3836188A1 (en) |
FR (1) | FR2738365A1 (en) |
GB (1) | GB2311632B (en) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60140429A (en) * | 1983-12-28 | 1985-07-25 | Hitachi Ltd | Decimal notation multiplier system |
-
1987
- 1987-10-23 FR FR8714668A patent/FR2738365A1/en active Pending
-
1988
- 1988-10-20 GB GB8824624A patent/GB2311632B/en not_active Expired - Fee Related
- 1988-10-24 DE DE19883836188 patent/DE3836188A1/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
GB8824624D0 (en) | 1997-07-16 |
GB2311632A (en) | 1997-10-01 |
DE3836188A1 (en) | 1997-05-22 |
FR2738365A1 (en) | 1997-03-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19980414 |