GB2309342A - Linear TDMA transmitter using selectable gain elements in forward and feedback paths - Google Patents
Linear TDMA transmitter using selectable gain elements in forward and feedback paths Download PDFInfo
- Publication number
- GB2309342A GB2309342A GB9600977A GB9600977A GB2309342A GB 2309342 A GB2309342 A GB 2309342A GB 9600977 A GB9600977 A GB 9600977A GB 9600977 A GB9600977 A GB 9600977A GB 2309342 A GB2309342 A GB 2309342A
- Authority
- GB
- United Kingdom
- Prior art keywords
- gain elements
- transmitter circuit
- selectable matrix
- gain
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 claims description 49
- 238000006243 chemical reaction Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 15
- 230000005540 biological transmission Effects 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000002238 attenuated effect Effects 0.000 description 5
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
- H03G3/3047—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers for intermittent signals, e.g. burst signals
Landscapes
- Transmitters (AREA)
- Amplifiers (AREA)
Description
LINEAR TRANSM1XAND METhOD OF OPERATION
Field of the Invention
This invention is related to linear transmitter designs and, in particular, to their operation in time domain multiple access (TDMA) communications systems. The invention is applicable to, but not limited to, reduction of adjacent channel interference in such TDMA communications systems.
Background of the Invention
Time Division Multiple Access (TDMA) linear transmitters tend to transmit more power into the adjacent channel (often termed splatter) during the beginning of the transmission (TX) time slot (ramp-up) and during the end of the TX time slot (ramp-down). The excessive splatter during these ramp-up and ramp-down periods cause harmful interference to any communications in adjacent frequency channels. Hence, splatter during these periods is designed to be kept at a minimum by using linear transmitter technology.
Standard transmitters operating in a class 'A' mode are inefficient and therefore linearisation of more efficient transmitters are typically used. Some international communications standards e.g. the European
Telecommunications Standard Institute (ETSI) Trans-European Trunked
Radio (TETRA) standard, allow some relaxation in the adjacent channel coupled power ratio (ACCPR) performance (namely the transmitter interference permitted in adjacent channels) during the ramp-up and the ramp-down periods. However, such performance limits are still difficult to achieve.
This invention seeks to provide a method for reducing adjacent channel interference of linearised transmitters and a linearised transmitter circuit to facilitate such a reduction.
Summarv of the Invention
According to a first aspect of the preferred embodiment of the invention, a method for reducing adjacent channel transmissions of a communications unit operating in a time domain communications system is provided. The communications unit has a linearised transmitter circuit for transmitting time domain multiplexed signals in time slots. The method includes the steps of transmitting information during a time slot and switching a selectable matrix of gain elements in the linearised transmitter circuit during a particular time period of the time slot in such a manner as to reduce adjacent channel transmissions. In the preferred embodiment of the invention, the selectable matrix of gain elements comprises a first selectable matrix of gain elements in a forward path and a second selectable matrix of gain elements in a feedback path. The step of switching the first selectable matrix of gain elements in a forward path and the second selectable matrix of gain elements in a feedback path includes selecting at least one gain element from the first selectable matrix of gain elements in the forward path and selecting at least one gain element from the second selectable matrix of gain elements in the feedback path.
Preferably, the particular time period for switching the selectable gain elements includes at least one of: substantially at the beginning or substantially at the end of the time slot.
Advantageously, in the preferred embodiment of the invention, the method for reducing adjacent channel interference in a Cartesian feedback linearised transmitter circuit, will reduce the adjacent channel coupled power ratio (ACCPR) due to the linearised transmitter ramping up and ramping down by 12 dB.
In a second aspect of the preferred embodiment of the invention a linearised transmitter circuit for reducing adjacent channel interference in a time division communications system is provided. The linearised transmitter circuit includes a baseband linearisation circuit having a baseband input and providing a filtered baseband output signal to a frequency up conversion circuit having a first selectable matrix of gain elements for receiving the filtered baseband output signal and a frequency conversion signal and for providing a high frequency output signal. A power amplifier receives the high frequency output signal and provides a transmitter circuit output to a feedback circuit which receives a portion of the transmitter circuit output and provides a feedback signal. A frequency down-conversion circuit is provided having a second selectable matrix of gain elements for receiving the feedback signal and a frequency downconversion signal and for providing a low frequency output to the baseband linearisation circuitry. A controller is operably coupled to the first and second selectable matrix of gain elements for providing a control signal for selectively switching the first and second selectable matrix of gain elements in order to reduce adjacent channel transmissions at the beginning and/or at the end of a time slot.
In this manner, the total loop gain is controlled and maintained at a constant level whilst the transmitter output power is successively reduced, thereby limiting the adjacent channel interference generated by the rampdown process.
A preferred embodiment of the invention will now be described by way of example only, with reference to the drawings.
Brief Descrintion of the Drawings
FIG. 1 shows a block diagram of a prior art Cartesian feedback linearised transmitter circuit.
FIG. 2 shows a block diagram of a simplified theoretical model of the
Cartesian feedback transmitter.
FIG. 3 is a block diagram of a Cartesian feedback linearised transmitter circuit, in accordance with a preferred embodiment of the invention.
FIG. 4 is a timing diagram showing the transmitter power control behaviour, in accordance with the preferred embodiment of the invention.
FIG. 5 is a flow chart detailing a method for reducing adjacent channel transmissions of a communications unit operating in a time domain communications system, in accordance with the preferred embodiment of the invention.
Detailed Description of the Drawings
Referring first to FIG. 1, a block diagram of a prior art Cartesian feedback linearised transmitter circuit is shown. The linearised transmitter circuit is part of a communications unit, i.e. a radio transmitter, and comprises an digital input signal 8, a digital signal processor (DSP) 10, a digital to analog converter (D/A) for in-phase (I) channel 11, a D/A for a quadrature (Q) channel 12, input attenuation 13, a summing junction 15 and a loop filter 21 for the I channel 11, input attenuation 14, a summing junction 17 and a loop filter 22 for the Q channel 12. The linearised transmitter circuit further comprises a summing junction 24, a low pass filter 28, an up-conversion forward attenuator 29, a mixer 30, a power amplifier 31, a coupler 32, a down converter feedback attenuator 34, a down-mixer 35, a main local oscillator (LO) 36, a baseband amplifier 41 for the I channel, a baseband amplifier 40 for the Q channel and an antenna 33.
In operation, a digital input signal 8 is fed into both the I and Q D/A converters to provide I and Q baseband analog signals which are attenuated by input attenuation 13 and input attenuation 14 respectively.
The filtered analog signals are then combined at summing junction 15 and summing junction 17 respectively with real-time fedback signals to provide linearised baseband I and Q signals. The linearised baseband I and Q signals are input to loop filter 21 and loop filter 22 respectively and then combined to provide a single baseband linearised signal. The single baseband linearised signal is filtered by low pass filter 28 and attenuated by the up-conversion forward attenuator 29 to provide an attenuated baseband linearised signal. The attenuated baseband linearised signal is upconverted to a suitable radio frequency by the mixer 30 and main local oscillator (LO) 36, where it is amplified by the power amplifier 31. The amplified linearised radio signal is sampled by the coupler 32 and the sampled signal fed via the down converter feedback attenuator 34 to the down-mixer 35 to produce a baseband fedback signal. The down converted signal is divided and input to baseband amplifier 41 for the I channel and to the baseband amplifier 40 for the Q channel in order to close the real-time feedback loop. Power control in the above linearised transmitter is achieved by simultaneously controlling the attenuation of the up-conversion forward attenuator 29 and the down-converter feedback attenuator 34. A typical example would be for five combinations of attenuation to be used as shown in Table 1.
Table 1. Typical attenuator levels to achieve power control in a linearised transmitter.
Power control Forward Attenuator 29 Feedback Attenuator 34
TX Power 5 ( Maximum) 0 dB 20 dB TX Power 4 5dB 15 dB TX Power 3 10 dB 10 dB TX Power 2 15 dB 5dB
TX Power 1 ( Minimum) 20 dB OdB The combined attenuation of up-conversion forward attenuator 29 and down-converter feedback attenuator 34 is always set to be 20 dB. This ensures that the open-loop gain is constant regardless of the power control state, which is kept constant during the whole of the transmission in the
TX slot.
A problem associated with such transmitter operating in a TDMA communications system is that the transmitted power leaked into adjacent frequency channels during ramp-up and ramp-down periods is high if the power control state is high.
Linear transmitters often use negative feedback techniques, e.g.
Cartesian feedback, to achieve high linearity of the transmitted output spectrum and thereby minimise adjacent channel splatter generated by say, the more efficient, but less linear class AB Power Amplifier (PA) when compared to class 'A' PAs. The Cartesian feedback loop operates in a closed-loop arrangement with such a non linear RF class AB PA with the feedback signal being negatively combined with the input signal at a baseband frequency in its quadrature 'I' and 'Q' form. The PA's linearity performance improves proportionally to the loop-gain when it is closed in the loop.
Referring now to FIG. 2, a block diagram of a simplified theoretical model of the Cartesian feedback transmitter. The simplified theoretical model of the Cartesian feedback transmitter comprises the followed components: An input signal Vin 90, a forward summer 91, a forward gain element 'A' 92, a transmitter output signal Vout 96, a coupler 97, a feedback gain element ' ' 93, a feedback summer 95 and a feedback additive noise signal Nf 94.
In operation, the feedback additive noise signal Nf 94 represents the noise that is dominant at the adjacent channel. The transfer function from the feedback additive noise signal Nf 94 at the transmitter output Vout 96 is:
Vout = A (1)
Nf 1+ peA If .A > > 1 then the transfer function can be approximated as Vout l (2)
Nf P When the power control state is changed from the higher power state in
Table 1 of TX Power 5 to the lower power state of TX power 4 , the feedback gain is increased by 5 dB to compensate. Thus the feedback noise contribution at the adjacent channel is effectively decreased by 5 dB and the
ACCPR performance is improved by 5 dB.
Referring now to FIG. 3, a block diagram of a Cartesian feedback linearised transmitter circuit, in accordance with the second aspect of the preferred embodiment of the invention is shown. The linearised transmitter circuit reduces adjacent channel interference and operates in a time divided multiple access (TDMA) communications system. The linearised transmitter circuit includes a baseband linearisation circuit 51 having a baseband input 50 and provides a filtered output 62. The baseband linearisation circuit 51 includes an in-phase (I) channel 77 having a digital to analog converter (D/A) 52, an input attenuator 55, an adder 57 and a loop filter 59. A feedback signal is input to the I channel at the adder 57 via a baseband amplifier 74. The baseband linearisation circuit 51 also includes a quadrature (Q) channel 78 having a digital to analog converter (D\A) 54, an input attenuator 56, an adder 58 and a loop filter 60. A feedback signal is input to the Q channel at the adder 58 via a baseband amplifier 73. A digital signal processor (DSP) 53 is also provided. The linearised transmitter circuit also includes a frequency up-conversion circuit 75, for receiving the filtered output 62, the frequency up-conversion circuit 75 having a mixer 65 and a first selectable matrix of gain elements 63 to provide a high frequency output 79 to a power amplifier 66. The power amplifier 66 provides a transmitter circuit output 82, to a sampling circuit 67, e.g. a coupler, and an antenna 68. The sampling circuit 67 provides a feedback signal 70 to a frequency down-conversion circuit 76 having a mixer 71 and a second selectable matrix of gain elements 64. A frequency up-conversion signal 80 and a frequency down-conversion signal 81 are provided by a main local oscillator 69. The frequency down-conversion circuit 76 provides a low frequency output 83 which is fed to baseband amplifier 73 and baseband amplifier 74. The first selectable matrix of gain elements 63 and second selectable matrix of gain elements 64 includes at least one gain element 84.
In operation, the baseband input 50 is fed into the baseband linearisation circuit 51, divided into two signals in quadrature to each other and input to I channel 77 and Q channel 78 respectively. In each respective channel the input signal is converted from a digital signal to an analog signal by the D\A 52 in I channel 77 and D\A 54 in Q channel 78. The analog signals are attenuated by the input attenuator 55 and input attenuator 56, slimmed with fedback signals at the adder 57 and adder 58 and filtered by the loop filter 59 and loop filter 60 respectively. The signals from the I channel output and Q channel output are combined to provide a filtered output 62. The frequency up-conversion circuit 75 receives the filtered output 62 and the frequency conversion signal 80 from the main local oscillator 69 and provides a high frequency output 79. The frequency up-conversion circuit 75 includes the first selectable matrix of gain elements 63 for adjusting a power level of the frequency up-conversion signal 80. The power amplifier 66 receives the high frequency output 79 and provides the transmitter circuit output 82. The sampling circuit 67 couples off a portion of the transmitter circuit output 82 thereby providing the feedback signal 70. The frequency down-conversion signal 81 is fed into the second selectable matrix of gain elements 64 and mixed with the feedback signal 70 at the mixer 71 to provide the low frequency output 83.
The frequency down-conversion circuit 76 includes the second selectable matrix of gain elements 63 for adjusting a power level of the frequency down-conversion signal 81. The second selectable matrix of gain elements 64 adjusts the power level of the frequency down-conversion signal 81. The low frequency output 83 is divided and input to the I channel 77 via the baseband amplifier 74 and input to the Q channel 78 via the baseband amplifier 73 in order to close the real-time feedback loop.
In the preferred embodiment the linearised transmitter circuit is a
Cartesian feedback linearised transmitter circuit although it is within the contemplation of the invention that other linearised transmitter technologies, such as Adaptive Pre-distortion, benefit from the invention.
Power control in the preferred embodiment of the linearised transmitter circuit is achieved by controlling the gain performance of the first selectable matrix of gain elements 63 and second selectable matrix of gain elements 64 concurrently. The combined power gain of the first selectable matrix of gain elements 63 and second selectable matrix of gain elements 64 is kept constant thereby maintaining a constant power gain within the feedback loop of the linearised transmitter circuit. It is within the contemplation of the invention that alternative topologies and arrangements for the selectable matrix of gain elements may be used to adjust the forward and feedback levels of the transmitted signal.
Referring now to FIG. 4, a timing diagram of a time domain multiple access (TDMA) communications system, in accordance with a preferred embodiment of the invention is shown. The communications system includes communications units having linearised transmitter circuits for transmitting time domain multiplexed signals in time slots, for example a data message 200 is transmitted in time slot 204. When the transmission of data is complete, e.g. at the end of time slot 201, the transmitter power level can be reduced in a single step 203 by switching all of the gain elements off. Such a rapid reduction in transmitted power levels cause transient interference in adjacent frequency channels.
It is within the contemplation of the invention that the selectable adjustment of gain elements may occur during any time period of the time slot, in particular at the beginning or at the end of the time slot. FIG. 4 is described with regard to the selectable adjustment of gain elements, solely at the end of the time slot, for explanation purposes only.
In the preferred embodiment the transmitted output power is reduced using option 'A', whereby the selectable matrix of gain elements is successively reduced from a maximum voltage to a minimum voltage as shown in step 202. Advantageously, this reduces the power level introduced in, and hence the transient interference caused to, adjacent frequency channels. To accomplish this multiple step reduction in output power, both the forward selectable matrix of gain elements and the feedback selectable matrix of gain elements are adjusted concurrently to ensure that the loop-gain of the linearised transmitter remains constant and hence, the feedback loop of the linearised transmitter remains stable at all times.
Referring now to FIG. 5, a flow chart detailing a method for reducing adjacent channel interference in a time domain communications system, in accordance with the first aspect of the preferred embodiment of the invention is shown. The method for reducing the adjacent channel interference generated by the linearised transmitter includes the steps of setting power control to the required level, as in step 100, transmitting information, e.g. a data message 200 in a time slot 204 at a maximum transmit control voltage of TX Power 5, as shown in step 101. When the end of the data transmission is monitored at an end of a time slot time slot 201 (or as in the preferred embodiment of the invention approximately 500 micro second before the end of time slot 201), as in step 102, the output power level is reduced to a minimum by successively switching gain elements out of the first selectable matrix of gain elements 63 in the forward path and into the second selectable matrix of gain elements 64 in the feedback path, as shown in step 104. The step of switching comprises selecting at least one gain element 84 from the first selectable matrix of gain elements 63 in the forward path and selecting at least one gain element 84 from the second selectable matrix of gain elements 64 in the feedback path. At the end of the time slot the transmitter power level is reduced (ramped-down), as shown in step 108.
Advantageously, in the preferred embodiment of the invention, the method for reducing adjacent channel interference in a Cartesian feedback linearised transmitter circuit, will reduce the adjacent channel interference due to a linearised transmitter ramping up and/or ramping down its output power by 12 dB.
Claims (10)
1. A method for reducing adjacent channel transmissions of a communications unit operating in a time domain communications system, the communications unit having a linearised transmitter circuit for transmitting time domain multiplexed signals in time slots, the method comprising the steps of:
transmitting information during a time slot; and
switching a selectable matrix of gain elements in the linearised transmitter circuit at during a particular time period of the time slot in such a manner as to reduce adjacent channel transmissions.
2. The method of claim 1, wherein the selectable matrix of gain elements comprises a first selectable matrix of gain elements in a forward path of the linearised transmitter circuit and a second selectable matrix of gain elements in a feedback path of the linearised transmitter circuit and the step of switching a selectable matrix of gain elements includes:
selecting at least one gain element from the first selectable matrix of gain elements in the forward path; and
selecting at least one gain element from the second selectable matrix of gain elements in the feedback path.
3. The method of any of the preceding claims, wherein the particular time period of the time slot is at least one of the following: substantially at the beginning of the time slot, substantially at the end of the time slot.
4. A linearised transmitter circuit for reducing adjacent channel interference in a time division communications system, the linearised transmitter circuit comprising:
a baseband linearisation circuit having a baseband input and providing a filtered baseband output signal;
a frequency up conversion circuit having a first selectable matrix of gain elements for receiving the filtered baseband output signal and a frequency conversion signal and for providing a high frequency output signal;
a power amplifier for receiving the high frequency output signal and providing a transmitter circuit output;
a feedback circuit for receiving a portion of the transmitter circuit output and providing a feedback signal;
a frequency down conversion circuit having a second selectable matrix of gain elements for receiving the feedback signal and a frequency down conversion signal and for providing a low frequency output to the baseband linearisation circuit; and
a controller operably coupled to the first and second selectable matrix of gain elements for providing a control signal for selectively switching the first and second selectable matrix of gain elements to reduce adjacent channel transmissions during a particular period of a time slot.
5. The linearised transmitter circuit according to claim 4, wherein the first selectable matrix of gain elements adjusts a power level of the frequency conversion signal and the second selectable matrix of gain elements adjusts a power level of the frequency down conversion signal.
6. The linearised transmitter circuit according to any of the preceding claims 4 to 5, wherein the first selectable matrix of gain elements adjusts a power level of the high frequency output signal and the second selectable matrix of gain elements adjusts a power level of the feedback signal.
7. The linearised transmitter circuit according to any of the preceding claims 4 to 6, wherein a combined power gain of the first selectable matrix of gain elements and second selectable matrix of gain elements is constant thereby maintaining a constant power gain of a feedback loop of the linearised transmitter circuit.
8. The linearised transmitter circuit according to any of the preceding claims 4 to 7, wherein the particular period of a time slot includes at least one of the following: substantially at the beginning of the time slot, substantially at the end of the time slot.
9. The linearised transmitter circuit according to any of the preceding claims 4 to 8, wherein the baseband input, filtered output and low frequency output comprise two signals in quadrature to each other and the linearised transmitter circuit is a Cartesian feedback linearised transmitter circuit.
10. A linearised transmitter circuit substantially as described herein with respect to FIG. 3
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9600977A GB2309342B (en) | 1996-01-18 | 1996-01-18 | Linear transmitter and method of operation |
| FR9700069A FR2743961B1 (en) | 1996-01-18 | 1997-01-07 | LINEAR TRANSMITTER METHOD AND CIRCUIT FOR REDUCING INTERFERENCE OF ADJACENT TRACKS IN A TIME DIVISION MULTIPLE ACCESS TELECOMMUNICATIONS SYSTEM |
| DE1997101351 DE19701351C2 (en) | 1996-01-18 | 1997-01-16 | Linearized transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9600977A GB2309342B (en) | 1996-01-18 | 1996-01-18 | Linear transmitter and method of operation |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9600977D0 GB9600977D0 (en) | 1996-03-20 |
| GB2309342A true GB2309342A (en) | 1997-07-23 |
| GB2309342B GB2309342B (en) | 2000-08-23 |
Family
ID=10787183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9600977A Expired - Lifetime GB2309342B (en) | 1996-01-18 | 1996-01-18 | Linear transmitter and method of operation |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE19701351C2 (en) |
| FR (1) | FR2743961B1 (en) |
| GB (1) | GB2309342B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1480402A1 (en) * | 2003-05-23 | 2004-11-24 | Sony Ericsson Mobile Communications AB | Automatic power control circuitry for a QAM transmitter unit of a wireless communication device |
| WO2007082201A2 (en) * | 2006-01-12 | 2007-07-19 | Motorola, Inc. | Method and apparatus for improved carrier feed thru rejection for a linear amplifier |
| WO2019005385A1 (en) * | 2017-06-28 | 2019-01-03 | Qualcomm Incorporated | Systems and methods for reducing transmit and receive power via a t/r switch |
| GB2570379A (en) * | 2017-12-15 | 2019-07-24 | Motorola Solutions Inc | Cartesian loop circuits, transmitters, devices, and related methods |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0405445A2 (en) * | 1989-06-27 | 1991-01-02 | Nec Corporation | Output waveform control circuit |
| EP0407135A2 (en) * | 1989-07-05 | 1991-01-09 | Matsushita Electric Industrial Co., Ltd. | Apparatus for controlling transmission output level for burst signal |
| EP0537690A2 (en) * | 1991-10-14 | 1993-04-21 | Nec Corporation | Burst control circuit for use in TDMA communications system |
| GB2263596A (en) * | 1991-07-22 | 1993-07-28 | Motorola Inc | Transition generating between on and off states of a radio frequency transmitter |
| EP0648012A1 (en) * | 1993-09-29 | 1995-04-12 | Linear Modulation Technology Ltd | Power control for cartesian amplifiers |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2927896B2 (en) * | 1990-06-28 | 1999-07-28 | 日本電気株式会社 | Spectrum suppression circuit |
| US5066923A (en) * | 1990-10-31 | 1991-11-19 | Motorola, Inc. | Linear transmitter training method and apparatus |
| JP2871889B2 (en) * | 1991-04-16 | 1999-03-17 | 三菱電機株式会社 | High frequency power amplifier |
| GB9219825D0 (en) * | 1992-09-18 | 1992-10-28 | Philips Electronics Uk Ltd | Power amplifier and a transmitter including the power amplifier |
| DE4313152A1 (en) * | 1993-04-22 | 1994-10-27 | Sel Alcatel Ag | HF amplifier with signal level control and radio transmitter equipped with it |
| GB9316869D0 (en) * | 1993-08-13 | 1993-09-29 | Philips Electronics Uk Ltd | Transmitter and power amplifier therefor |
| US5590418A (en) * | 1993-09-30 | 1996-12-31 | Motorola, Inc. | Method and apparatus for stabilizing the gain of a control loop in a communication device |
| GB2293935B (en) * | 1994-10-03 | 1999-07-14 | Linear Modulation Tech | Automatic calibration of carrier suppression and loop phase in a cartesian amplifier |
-
1996
- 1996-01-18 GB GB9600977A patent/GB2309342B/en not_active Expired - Lifetime
-
1997
- 1997-01-07 FR FR9700069A patent/FR2743961B1/en not_active Expired - Fee Related
- 1997-01-16 DE DE1997101351 patent/DE19701351C2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0405445A2 (en) * | 1989-06-27 | 1991-01-02 | Nec Corporation | Output waveform control circuit |
| EP0407135A2 (en) * | 1989-07-05 | 1991-01-09 | Matsushita Electric Industrial Co., Ltd. | Apparatus for controlling transmission output level for burst signal |
| GB2263596A (en) * | 1991-07-22 | 1993-07-28 | Motorola Inc | Transition generating between on and off states of a radio frequency transmitter |
| EP0537690A2 (en) * | 1991-10-14 | 1993-04-21 | Nec Corporation | Burst control circuit for use in TDMA communications system |
| EP0648012A1 (en) * | 1993-09-29 | 1995-04-12 | Linear Modulation Technology Ltd | Power control for cartesian amplifiers |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1480402A1 (en) * | 2003-05-23 | 2004-11-24 | Sony Ericsson Mobile Communications AB | Automatic power control circuitry for a QAM transmitter unit of a wireless communication device |
| WO2004105338A1 (en) * | 2003-05-23 | 2004-12-02 | Sony Ericsson Mobile Communications Ab | Automatic power control circuitry for a qam transmitter unit of a wireless communication device |
| WO2007082201A2 (en) * | 2006-01-12 | 2007-07-19 | Motorola, Inc. | Method and apparatus for improved carrier feed thru rejection for a linear amplifier |
| WO2007082201A3 (en) * | 2006-01-12 | 2007-12-13 | Motorola Inc | Method and apparatus for improved carrier feed thru rejection for a linear amplifier |
| WO2019005385A1 (en) * | 2017-06-28 | 2019-01-03 | Qualcomm Incorporated | Systems and methods for reducing transmit and receive power via a t/r switch |
| US10361745B2 (en) | 2017-06-28 | 2019-07-23 | Qualcomm Incorporated | Systems and methods for reducing transmit and receive power via a T/R switch |
| GB2570379A (en) * | 2017-12-15 | 2019-07-24 | Motorola Solutions Inc | Cartesian loop circuits, transmitters, devices, and related methods |
| US10367535B2 (en) | 2017-12-15 | 2019-07-30 | Motorola Solutions, Inc. | Cartesian loop circuits, transmitters, devices, and related methods |
| GB2570379B (en) * | 2017-12-15 | 2021-01-06 | Motorola Solutions Inc | Cartesian loop circuits, transmitters, devices, and related methods |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19701351C2 (en) | 2003-04-24 |
| GB2309342B (en) | 2000-08-23 |
| FR2743961A1 (en) | 1997-07-25 |
| DE19701351A1 (en) | 1997-10-30 |
| FR2743961B1 (en) | 1998-12-31 |
| GB9600977D0 (en) | 1996-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5107487A (en) | Power control of a direct sequence CDMA radio | |
| AU704530B2 (en) | Linearized digital automatic gain control | |
| EP0941575B1 (en) | Efficient parallel-stage power amplifier | |
| US5974041A (en) | Efficient parallel-stage power amplifier | |
| US5748678A (en) | Radio communications apparatus | |
| EP1450479B1 (en) | Efficient modulation of RF signals | |
| KR100259680B1 (en) | Power control circuit for a radio frequency transmitter | |
| US6591090B1 (en) | Predistortion control for power reduction | |
| EP0665641B1 (en) | Power amplifier and radio transmitter | |
| KR101050928B1 (en) | Automatic power control circuit for RAM transmitter unit of wireless communication device | |
| US5621763A (en) | Apparatus and method for generating a transition between the on and off states of a radio frequency transmitter | |
| CA2173608A1 (en) | Apparatus and method for shaping and power controlling a signal in a transmitter | |
| GB2309342A (en) | Linear TDMA transmitter using selectable gain elements in forward and feedback paths | |
| JPH0722999A (en) | Digitally modulated radio telephone system | |
| KR100516670B1 (en) | Apparatus for output automatic compensation of multi-channel digital transceiver | |
| GB2329538A (en) | Reducing splatter from TDMA transmitter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Expiry date: 20160117 |