GB2308948A - Data Transfer Circuit - Google Patents

Data Transfer Circuit Download PDF

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Publication number
GB2308948A
GB2308948A GB9600257A GB9600257A GB2308948A GB 2308948 A GB2308948 A GB 2308948A GB 9600257 A GB9600257 A GB 9600257A GB 9600257 A GB9600257 A GB 9600257A GB 2308948 A GB2308948 A GB 2308948A
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GB
United Kingdom
Prior art keywords
circuit
modulated signal
data
signal
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9600257A
Other versions
GB2308948B (en
GB9600257D0 (en
Inventor
Michel Burri
Hans Staufer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to GB9600257A priority Critical patent/GB2308948B/en
Publication of GB9600257D0 publication Critical patent/GB9600257D0/en
Publication of GB2308948A publication Critical patent/GB2308948A/en
Application granted granted Critical
Publication of GB2308948B publication Critical patent/GB2308948B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0008General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer

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  • Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Near-Field Transmission Systems (AREA)

Abstract

A data transfer circuit (10) has an arrangement for receiving a modulated signal, a first current path (25, 30, 35) for providing a first polarity portion of the modulated signal to provide power to the circuit, and a second current path (40, 45, 50, 55) for providing a second polarity portion of the modulated signal to derive modulation information therefrom.

Description

DATA TRANSFER CIRCUIT AND METHOD Field of the Invention This invention relates to data transfer circuits, and particularly though not exclusively to contactless data transfer circuits.
Background of the Invention Contactless smartcard systems are known which provide for transfer of data from a base station to a smartcard and vice-versa without direct electrical coupling. Inductive couplings in the base station and smartcard are typically used to achieve a contactless interface.
In many smartcard applications the smart card itself is arranged to not contain any intrinsic power. Power and data are transferred by a modulated carrier signal via the inductive coupling. The smartcard then switches an internal resistor which can be sensed by the base station. In this way data is transferred back from the smartcard to the base station.
A problem with the above arrangement is that derivation of power from the carrier signal induced within the smartcard causes clipping of the carrier signal.
Furthermore, typical modulation schemes are problematic. Amplitude modulation of the carrier results in power transfer inefficiency, since each logic zero value modulated on the carrier results in a reduced amplitude.
Phase shift modulation causes discontinuities in the carrier signal during phase shift, which necessitates the provision of a phase locked loop to maintain an internal clock in the smartcard.
This invention seeks to provide a data transfer circuit and method which mitigate the above mentioned disadvantages.
Summary of the Invention According to a first aspect of the present invention there is provided a data transfer circuit for receiving a modulated signal, comprising: means for receiving the modulated signal; a first current path for carrying a first polarity portion of the modulated signal to provide power to the circuit; a second current path for providing a second polarity portion of the modulated signal to derive modulation information therefrom.
Preferably the means for receiving the modulated signal comprises an inductor, arranged to produce an induced signal in response to received radiation. The first and second current paths are preferably formed with diodes.
According to a second aspect of the present invention there is provided method for transferring data from a transmitter circuit to a receiver circuit, comprising the steps of: in the transmitter circuit, modulating a carrier signal with data to be transferred; transferring the modulated signal from the transmitter circuit to the receiver circuit; using a first polarity portion of the modulated signal for providing power to the receiver circuit; and, using a second polarity portion of the modulated signal for deriving modulation information in the receiver circuit.
Preferably the modulation information includes data modulated on to the carrier signal and a clock signal. The modulation is preferably amplitude modulation.
In this way clipping of the carrier signal is substantially avoided, power transfer efficiency is increased, and the need for a phase locked loop in the receiver circuit is avoided.
Brief Description of the Drawing(s) An exemplary embodiment of the invention will now be described with reference to the single figure drawing which shows a preferred embodiment of a data transfer system in accordance with the invention.
Detailed Description of a Preferred Embodiment Referring to FIG.1, there is shown a data transfer system 5 including a data transfer circuit 10 and a base station 100. The base station 100 comprises a data input terminal 115 for receiving data to be transmitted to the data transfer circuit 10. A transmitter circuit 110 is coupled to the data input terminal 115, for modulating a carrier frequency signal by the data to be transmitted.
A driver circuit 120 is coupled to receive the modulated signal, for driving it through an inductor 140 via a resistor 125 and a capacitor 130. A potential divider network of resistors 155 and 160 are coupled across the inductor 140, for providing a point of divided potential. A demodulator circuit 150 is coupled to the point of divided potential, for demodulating signals from the inductor 140. A data output terminal 170 is coupled to receive demodulated data from the demodulator 150.
The data transfer circuit 10 comprises an inductor 20 having first and second terminals 22 and 24 respectively, and having a capacitor 12 and a switched resistor 15 coupled in parallel across the first and second terminals 22 and 24.
A first diode 25 is coupled to the first terminal 22, for providing a positive voltage path providing power supply voltage Vdd. A storage capacitor 30 is coupled between the positive voltage path and ground. A second diode is coupled between ground and the second terminal 24 of the inductor 20, for providing a return path for the positive voltage path.
A third diode 40 provides a negative voltage path to be further described below. A fourth diode 45 provides a return path for the negative voltage path.
A clock recovery circuit 50 is coupled to the negative voltage path. A data recovery circuit 55 is also coupled to the negative voltage path. The data recovery circuit comprises a filter 60 coupled to the negative voltage path, an integrator coupled to the filter 60, and a comparator 70, coupled to compare an output of the integrator 65 with an output of the filter 60.
In operation, data to be transmitted to the data transfer circuit 10 is received at the data input terminal 115. The transmitter circuit 110 modulates the carrier frequency signal by this data, and the driver circuit 120 drives it through the inductor 140.
The inductor 20 of the data transfer circuit 10 receives the modulated signal by induction. The first diode 25 and the second diode 35 steer current during the positive phase of the modulated signal to charge the storage capacitor 30 and to provide the operating voltage Vdd to the data transfer circuit 10. The storage capacitor 30 discharges during the negative phase of the modulated signal, thus maintaining Vdd.
The third diode 40 and the fourth diode 45 steer current during the negative phase of the modulated signal to the clock recovery circuit 50 and to the data recovery circuit 55, where the data and clock respectively are recovered.
In this way the current drawn for Vdd does not result in any denigration of the signal to be demodulated. The negative phase is not at risk from clipping, as no current is drawn for Vdd from this phase. This allows the clock to be successfully derived. Furthermore, noise associated with the derivation of Vdd is prevented from being transferred to the data or the clock.
The data transfer circuit 10 is arranged to transfer data back to the base station by using the switched resistor 15 to vary the impedance of the inductor 20. With the switched resistor 15 in a first position, a first impedance is presented, and in a second position, a second impedance is presented. In this way data values of logical 1 and logical 0 can be communicated back to the base station 100.
Response data is transferred back from the data transfer circuit 10 to the base station 100 by mutual inductance of the inductors. The potential divider network of resistors 155 and 160, sense a voltage in the inductor 140, which is dependent upon the mutual inductance received back from the inductor 20. The demodulator circuit 150 demodulates the inductor voltage to provide the received data to the data output terminal 170.
It will be appreciated by a person skilled in the art that alternate embodiments to the one described above are possible. For example, the positive and negative phases and the diodes could be reversed. The inductors could be replaced by other media suitable for contactless data transfer, such as infra-red apparatus.

Claims (9)

Claims
1. A data transfer circuit for receiving a modulated signal, comprising: means for receiving the modulated signal; a first current path for carrying a first polarity portion of the modulated signal to provide power to the circuit; a second current path for providing a second polarity portion of the modulated signal to derive modulation information therefrom.
2. The circuit of claim 1 wherein the means for receiving the modulated signal comprises an inductor, arranged to produce an induced signal in response to received radiation.
3. The circuit of claim 1 or claim 2 wherein the first and second current paths are formed with diodes.
4. A method for transferring data from a transmitter circuit to a receiver circuit, comprising the steps of: in the transmitter circuit, modulating a carrier signal with data to be transferred; transferring the modulated signal from the transmitter circuit to the receiver circuit; using a first polarity portion of the modulated signal for providing power to the receiver circuit; and, using a second polarity portion of the modulated signal for deriving modulation information in the receiver circuit.
5. The circuit or method of any preceding claim wherein the modulation information includes data modulated on to the carrier signal.
6. The circuit or method of any preceding claim wherein the modulation information includes a clock signal.
7. The circuit or method of any preceding claim wherein the modulation is amplitude modulation.
8. A circuit substantially as hereinbefore described and with reference to the drawings.
9. A method substantially as hereinbefore described and with reference to the drawings.
GB9600257A 1996-01-06 1996-01-06 Data Transfer Circuit and Method Expired - Fee Related GB2308948B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9600257A GB2308948B (en) 1996-01-06 1996-01-06 Data Transfer Circuit and Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9600257A GB2308948B (en) 1996-01-06 1996-01-06 Data Transfer Circuit and Method

Publications (3)

Publication Number Publication Date
GB9600257D0 GB9600257D0 (en) 1996-03-06
GB2308948A true GB2308948A (en) 1997-07-09
GB2308948B GB2308948B (en) 1999-11-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB9600257A Expired - Fee Related GB2308948B (en) 1996-01-06 1996-01-06 Data Transfer Circuit and Method

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GB (1) GB2308948B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773933A1 (en) * 1998-01-21 1999-07-23 Sgs Thomson Microelectronics DEVICE FOR DEMODULATING A BINARY SIGNAL MODULATED IN PHASE BY CODE PULSES
WO2000004686A1 (en) * 1998-07-13 2000-01-27 Koninklijke Philips Electronics N.V. Data carrier with at least two demodulators for receiving ask signals of differing modulation index
GB2357597A (en) * 1999-12-22 2001-06-27 Keith Andrew Burton Dynamic process model with model interrogation

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773933A1 (en) * 1998-01-21 1999-07-23 Sgs Thomson Microelectronics DEVICE FOR DEMODULATING A BINARY SIGNAL MODULATED IN PHASE BY CODE PULSES
EP0932283A1 (en) * 1998-01-21 1999-07-28 STMicroelectronics SA BPSK demodulator for PCM signal
US6140869A (en) * 1998-01-21 2000-10-31 Stmicroelectronics S.A. Device for demodulating a binary phase-shift keyed signal
WO2000004686A1 (en) * 1998-07-13 2000-01-27 Koninklijke Philips Electronics N.V. Data carrier with at least two demodulators for receiving ask signals of differing modulation index
GB2357597A (en) * 1999-12-22 2001-06-27 Keith Andrew Burton Dynamic process model with model interrogation

Also Published As

Publication number Publication date
GB2308948B (en) 1999-11-24
GB9600257D0 (en) 1996-03-06

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080106