GB2306722A

GB2306722A - Encryption/decryption

Info

Publication number: GB2306722A
Application number: GB9521733A
Authority: GB
Inventors: Michel Burri; Pascal Renard
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1995-10-24
Filing date: 1995-10-24
Publication date: 1997-05-07
Anticipated expiration: 2015-10-24
Also published as: GB2306722B; GB9521733D0

Abstract

A method of encryption/decryption uses a linear feedback shift register 210, performing a predetermined number of shift iterations on an initial value in the register utilising a first predetermined selection of feedback paths 230 so as to produce an encrypted value in the register; and performing said predetermined number of shift iterations on the encrypted value in the register utilising a second predetermined selection of feedback paths 240 so as to produce the decrypted initial value in the register, wherein the first and second predetermined selections of feedback paths are chosen in accordance with complementary factors of the linear feedback shift register's transform function. During operation, the register values are mixed 250 with the outputs of a random key generator circuit 110 having another such linear feedback shift register 115.

Description

ENCRYPTION/DECRYPTION CIRCUIT, METHOD AND SYSTEM Fleld of the Invention This invention relates to encryption/decryption circuits, and particularly though not exclusively to encryption/decryption circuits for use in security applications.

Backound of the Invention Many devices such as smartcards and electronic locks require a highly secure data transmission between two devices, preferably in a form which prevents unauthorised access. A high level of security can be achieved using encryption/decryption techniques, used to encrypt the data before transmission by a first device and to decrypt the data after reception by a second device. Usually the higher the level of security, the greater the complexity of the hardware and software used to perform the encryption/decryption algorithm. Consequently much silicon is used and the resulting execution time is long.

However, a problem with this arrangement is that some applications require a high level of security using an encryption algorithm and yet also a fast execution time. A typical example of such an application is a vehicle antitheft system. Data is exchanged between the vehicle ignition switch and the key. If a mutual acknowledgement occurs, the user can drive the vehicle; if not, the engine is immobilised. The exchanged data is more secure if it is encrypted and decrypted as described above. Vehicle manufacturers require anti-theft systems in their vehicles to have fast total response times of about 100 ms. such that as soon as the user turns the key in the ignition switch, the engine is either started or immobilised.

This invention seeks to provide an encryption/decryption circuit and method which mitigates the above mentioned disadvantages.

Summarv of the Invention According to a first aspect of the present invention there is provided a method of encryption/decryption using a linear feedback shift register, the register comprising a number of cells each having a feedback path, the method comprising the steps of: performing a predetermined number of shift iterations on an initial value in the register utilising a first predetermined selection of feedback paths so as to produce an encrypted value in the register; and performing said predetermined number of shift iterations on the encrypted value in the register utilising a second predetermined selection of feedback paths 5G as to produce the decrypted initial value in the register, wherein the first and second predetermined selection of feedback paths are chosen in accordance with complementary factors of the linear feedback shift register's transform function.

According to a second aspect of the present invention there is provided an encryption/decryption circuit, comprising: an input for receiving a first signal which is either plain or encrypted; a shift register having a plurality of cells for storing the first signal, each cell having a feedback path, the shift register being further arranged for shifting the stored signal and for storing successive shifted signals; summing means coupled to each of the feedback paths, for summing together fed-back signals received therefrom according to first and second selection schemes and for providing a summed signal to one of the plurality of cells; and, an output coupled to provide a second signal corresponding to the values stored in the plurality of cells, the second signal being encrypted if the first signal is plain, or decrypted if the first signal is encrypted; wherein the first and second selection schemes are chosen in accordance with complementary factors of the linear feedback shift register's transform function, the first scheme being used for encryption and the second scheme being used for decryption.

According to a third aspect of the present invention there is provided an encryption circuit for use in combination with a decryption circuit, the encryption circuit comprising: an input for receiving a first signal; a shift register having a plurality of cells for storing the first signal, each cell having a feedback path, the shift register being further arranged for shifting the stored signal and for storing successive shifted signals; summing means coupled to each of the feedback paths, for sllmming together fed-back signals received therefrom according to a selection scheme and for providing a summed signal to one of the plurality of cells; and an output coupled to provide a second signal corresponding to the values stored in the plurality of cells; wherein the selection scheme is chosen in accordance with complementary factors of the linear feedback shift register's transform function, and a complementary arrangement of the decryption circuit.

According to a fourth aspect of the present invention there is provided a decryption circuit for use in combination with a encryption circuit, the decryption circuit comprising: an input for receiving a first signal; a shift register having a plurality of cells for storing the first signal, each cell having a feedback path, the shift register being further arranged for shifting the stored signal and for storing successive shifted signals; stmming means coupled to each of the feedback paths, for summing together fed-back signals received therefrom according to a selection scheme and for providing a summed signal to one of the plurality of cells; and an output coupled to provide a second signal corresponding to the values stored in the plurality of cells; wherein the selection scheme is chosen in accordance with complementary factors of the linear feedback shift register's transform function, and a complementary arrangement of the encryption circuit.

Preferably the circuit or method further comprises means for performing the shift a predetermined number of times.

In this way an encryption/decryption algorithm is provided which allows the user to obtain a good level of confidentiality, a low complexity in term of silicon and a fast execution time whatever the implementation (hardware or software).

Brief Descnption of the Drawing(s) An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIGS.1, 2 and 3 show conceptual diagrams of linear feedback shift registers in accordance with the invention.

FIGS.4 and 5 show bit sequence tables associated with the linear feedback shift registers of FIGS. 1, 2 and 3.

FiG.6 shows a preferred embodiment of an encryption/decryption circuit in accordance with the invention.

Detailed Descnption of a Preferred Embodiment Referring to FIG.1, there is shown a Linear Feedback Shift Register (LFSR) 10. The LFSR 10 contains a number of cells yl, y2, y3, ,yn each containing a data bit. Output paths from each of the cells yl, y2, y3, ,yn are input to a NOR gate 15, where they are summed together in modulo-2.

The result is then fed-back to the first cell yl, while the previous bit stored in each cell is shifted to the next cell on the right. A binary sequence is initially loaded into the cells of the LFSR 10, and a characteristic bit pattern is generated through successive iterations of the LFSR 10.

Mathematically, the operation of the LFSR 10 is:

y'1=y1#y2#.... ....yn y'2 =yl y'3=y2 y'n=yn-l Equation 1 This set of linear equations have the following matrix form: [r] [T].[Y] Equation 2 where [T] is the transition matrix.

Example for n = 4.

y'll 1 1 . lyl y'2 1 0 0 0 y2 = y'3# #0 1 0 0# #y3 y'4 0 0 1 0 y4

Equation 3 The polynomial P(x) = det([T] - [X].[I]) is the characteristic polynomial of [T].

Over the field of the integers mod 2, this can be written as: P(x) = det([T]+[X].[I]) Equation 4 where [I] is the unity matrix.

Characteristic polynomials for LFSR:

1 1 1 1 X 0 0 0 1 + X 1 1 1 1 0 0 0 0 X 0 0 1 X 0 0 P4(x)=det## #+# ##=| | 0 1 0 0 0 0 X 0 0 1 X 0 0 0 1 0 0 0 0 X 0 0 1 X P4(x)=(1+X)|1 X 0|+|1 X 0|=(1+X)#X.| |#+| |+| | 0 1 X 0 1 X P4(x)=X4+X3+X2 +X+l Therefore the polynomial for an n-cell LFSR will be: Pn(X) = Xn+Xn-1+... ...+X+1 An LFSR having a single cycle of length 2n -1 is said to be a maximum sequence LFSR and is suitable for encryption/decryption since the quality of data mixing inside a cycle is pseudo random. The period of the transition matrix must then be 2n -1. The characteristic polynomial of a maximum sequence LFSR must satisfy the two following conditions: - it must be irreducible (not factored) - it must not be a divisor of Xk -1 for k smaller then 2n -1.

The irreducible polynomials are deduced from P(x) in the following way: P(x) = Q(x).D(x)+ R(x) Example for n = 4.

P(x) = X4 + X3 + X2 + X +1 = (X+1).(X3 + 1)+ X2 where: Q(x) = (X + l) is the quotient D(x) = (X3 +1) is the greatest common divisor of P(x) R(x) = X2 is the remainder Q(x) is the inverse of feedback equation of D(x). Therefore it is possible to build a reversible encryption/decryption LFSR, if a first predetermined selection of the feedback paths is made (relating to the polynomial Q(x)) during the encryption sequence and a second predetermined selection of the feedback paths is made (relating to the polynomial D(x)) during the decryption sequence.

Referring now also to FIG. 2, a LFSR 30 having four cells x0 xl, x2, and x3 is shown. The feedback paths from cells xl and x0 are selected, corresponding to he polynomial P4(x) when divided by Q(x) = (X + 1). The table 60 of FIG. 4 shows the equivalent binary sequence when the LFSR 30 is shifted to right and initialised by "1 1 1 1".

Referring now also to FIG. 3 a LFSR 50 having four cells x0, xl, x2 and x3 is shown. The feedback paths from cells x0 and x3 are selected, corresponding to he polynomial P4(x) when divided by D(x) = (X3 +1). The table 70 of FIG. 5 shows the equivalent binary sequence when the LFSR 50 is shifted to left and initialised by "1 1 1 1". it can be seen that the binary sequence of the tables 60 and 70 follows the same pattern but in a reversed order.

The above principle may be used for encryption and decryption purposes as follows. In the case of a vehicle key and ignition lock, the key has a first LFSR such as the LFSR 50 initialised with a plain text message and having a first feedback selection scheme. When the key is placed in the ignition lock the first LFSR loads a summed, fedback bit to the leftmost cell and shifts the plain text message to the right. This is repeated a predetermined number of times and finally the message (which is now encrypted) is transmitted to the ignition lock.

The ignition lock has a second LFSR which is which has the same structure as the first LFSR, but with a second feedback selection scheme which is arranged to be complimentary with respect to that of the first LFSR. The second LFSR is initialised with the received encrypted message. The second LFSR loads a summed, fedback bit to the rightmost cell and shifts the plain text message to the left. This is repeated the same predetermined number of times, resulting in a decrypted message which the restored plain text message. This plain text message is then compared to an expected message and if the result of the comparison is positive, the ignition is enabled.

Referring now to FIG. 6, an encryption/decryption circuit 100 is shown. The circuit 100 is arranged for providing a further embedded encrypting/decrypting method by employing two LFSRs, one arranged to encrypt secure key data before mixing this data with that from the other LFSR. The circuit 100 comprises an encrypting/decrypting circuit 200, and a random key generator (RKG) circuit 110 and other components to be further described below.

The RKG circuit 110 comprising a first LFSR 115 of length M having a secure data input terminal 120 for loading secure data into the first LFSR 115, to be further described below. The first LFSR 115 has an output 150.

The random key generator circuit also includes first and second feedback paths 130 and 140 respectively. The first feedback path 130 includes an encryption input 135, and is arranged to provide encryption shifting in a first direction for the first LFSR 115. The second feedback path 140 includes an decryption input 145, and is arranged to provide decryption shifting in a second direction for the first LFSR 115.

The encrypting/decrypting circuit 200 comprises a second LFSR 210 of length N coupled to serial input and output terminals 220 and 215 respectively, and having parallel input and outputs to be further described below. Third and fourth feedback paths 230 and 240 respectively are coupled to the second LFSR 210. The first feedback path 230 includes an encryption input 235, and is arranged to provide encryption shifting in a first direction for the second LFSR 210. The second feedback path 240 includes an decryption input 245, and is arranged to provide decryption shifting in a second direction for the second LFSR 210.

The parallel output of the second LFSR 210 is coupled to a mixer circuit, which takes this output and the output 150 of the first LFSR 115, mixing them to produce a mixed parallel output.

The mixed parallel output is then sent to the parallel input of the second LFSR 210. A parity circuit 260 is coupled to count each occurrence of the mixed parallel output signal, and provides a parity bit signal indicating the whether an odd or an even number of signals have been detected.

A shift circuit 270 is coupled to receive the parity bit signals, and provides clocking signals to shift both the first and second LFSRs 115 and 210 respectively by an equal number of shifts. The number of shifts are determined by the parity bit signals. If a parity odd (0) signal is received, a first number of clocking signals are provided. If a parity even (1) signal is received, a second number of clocking signals are provided. In this way a further degree of complication is added, resulting in more security.

In operation, to encrypt a message, the encrypting feedback paths 130 of the first LFSR 115 and 230 of the second LFSR 150 are enabled by their respective inputs 135 and 235. The decrypting feedback paths 140 and 240 remain disabled.

A plain text message of length N is serially received at the serial input terminal 220 and loaded into the second LFSR 210. Simultaneously, a secret key is loaded into the first LFSR 115 via the secure data input terminal 120.

The value of the data in both LFSRs 115 and 210 are then combined in the mixer circuit 250. The mixed parallel signal is then loaded into the second LFSR 210. In this way the plain text message is encoded by the secure key data before shifting. The parity of the number of received mixed signals is then determined by the parity circuit 260, and an appropriate parity signal is sent to the shift circuit 270, which in turn sends a predetermined number of clocking signals to both LFSRs. Thereby the contents of the first and second LFSRs 115 and 210 are both right shifted by an amount determined by the shift circuit 270.

To provide increased security, the above process may be repeated a number of times with the partial results stored in the LFSRs 115 and 210, before a final encrypted message is provided from the second LFSR 210 at the serial output terminal 215.

The decryption process is similar to the encryption process described above.

The encrypted message is fed into the second LFSR 210 via the serial input terminal 220, the decryption inputs 145 and 245 are enabled and the encryption inputs 135 and 235 are disabled, thereby mandating a left shift operation for the LFSRs 115 and 210. For the decryption operation, the secure key data is not loaded into the first LFSR 115. Instead, the last shifted result from the encryption sequence is retained in the LFSR 115, and this is used as the first value provided to the mixer circuit 250 during decryption. The decryption sequence continues in an identical manner to the encryption sequence, being repeated the same number of times, and utilising the mixer circuit 250, the parity circuit 260 and the shift circuit 260 as described above.

In this way a deeply embedded encrytion/decryption algorithm is produced.

The algorithm is easily customised by varying the parameters of the secret key, the feedback paths, the number of shifts, the number of repetitions and the lengths N and M of the LFSRs 115 and 210 respectively.

It will be appreciated that alternate embodiments to the one described above are possible. For example, the arrangement of the feedback paths need not be limited to those precisely described above. Furthermore, an alternate method could be used for selecting the number of shifts to be performed by the shift circuit 270. For example, a logic circuit with an input from the first LFSR 115 could replace the parity circuit 260.

Claims

1. A method of encryption/decryption using a linear feedback shift register, the register comprising a number of cells each having a feedback path, the method comprising the steps of: performing a predetermined number of shift iterations on an initial value in the register utilising a first predetermined selection of feedback paths so as to produce an encrypted value in the register; and performing said predetermined number of shift iterations on the encrypted value in the register utilising a second predetermined selection of feedback paths so as to produce the decrypted initial value in the register, wherein the first and second predetermined selection of feedback paths are chosen in accordance with complementary factors of the linear feedback shift register's transform function.

2. An encryption/decryption circuit, comprising: an input for receiving a first signal which is either plain or encrypted; a shift register having a plurality of cells for storing the first signal, each cell having a feedback path, the shift register being further arranged for shifting the stored signal and for storing successive shifted signals; summing means coupled to each of the feedback paths, for summing together fed-back signals received therefrom according to first and second selection schemes and for providing a summed signal to one of the plurality of cells; and, an output coupled to provide a second signal corresponding to the values stored in the plurality of cells, the second signal being encrypted if the first signal is plain, or decrypted if the first signal is encrypted; wherein the first and second selection schemes are chosen in accordance with complementary factors of the linear feedback shift register's transform function, the first scheme being used for encryption and the second scheme being used for decryption.

3. An encryption circuit for use in combination with a decryption circuit, the encryption circuit comprising: an input for receiving a first signal; a shift register having a plurality of cells for storing the first signal, each cell having a feedback path, the shift register being further arranged for shifting the stored signal and for storing successive shifted signals; summing means coupled to each of the feedback paths, for sllmming together fed-back signals received therefrom according to a selection scheme and for providing a summed signal to one of the plurality of cells; and an output coupled to provide a second signal corresponding to the values stored in the plurality of cells; wherein the selection scheme is chosen in accordance with complementary factors of the linear feedback shift register's transform function, and a complementary arrangement of the decryption circuit.

4. A decryption circuit for use in combination with a encryption circuit, the decryption circuit comprising: an input for receiving a first signal; a shift register having a plurality of cells for storing the first signal, each cell having a feedback path, the shift register being further arranged for shifting the stored signal and for storing successive shifted signals; summing means coupled to each of the feedback paths, for summing together fed-back signals received therefrom according to a selection scheme and for providing a summed signal to one of the plurality of cells; and an output coupled to provide a second signal corresponding to the values stored in the plurality of cells; wherein the selection scheme is chosen in accordance with complementary factors of the linear feedback shift register's transform function, and a complementary arrangement of the encryption circuit.

5. An encryption/decryption system comprising the encryption circuit of claim 3 and the decryption circuit of claim 4.

6. The circuit, method or system of claims 2, 3, 4 or 5 further comprising means for performing the shift a predetermined number of times.

7. An encryption/decryption method substantially as hereinbefore described and with reference to the drawings.

8. An encryption circuit substantially as hereinbefore described and with reference to the drawings.

9. A decryption circuit substantially as hereinbefore described and with reference to the drawings.