GB2306721A

GB2306721A - Resource controller

Info

Publication number: GB2306721A
Application number: GB9521485A
Authority: GB
Inventors: John William Nicholl
Original assignee: CANMOY HOLDINGS Ltd
Current assignee: CANMOY HOLDINGS Ltd
Priority date: 1995-10-18
Filing date: 1995-10-20
Publication date: 1997-05-07
Anticipated expiration: 2015-10-20
Also published as: IES66413B2; GB2306721B; IES950815A2; GB9521485D0

Abstract

A resource controller 1 has a validation section 2 and a control section 3 for controlling mobile resources. The validation section 2 has a data input latch 12, an ID comparator 13 with an associated counter 14, an ID memory 15, an active low ID latch 16, a checksum comparator 20 and an associated checksum latch 21 and a checksum memory 22. The control section 3 has a crystal oscillator 30, a frequency divider 31 a resource clock 32, actuation means provided by a twelve volt stepper motor controller 40, a door lock release solenoid 41 and an emergency override switch 56. The crystal oscillator 30 provides the clock input to a card reader interface 10 and to the stepper motor controller 40 for controlling the operation of both validation and control sections. If the ID from the card agrees 13 with any of those in memory 15, and a checksum from the card agrees 20 with a checksum, corresponding to the ID, from memory 22, the ID and time are stored 26 and the lock is released.

Description

"A Resource Controller" The present invention relates to a resource controller and more particularly to a resource controller for controlling mobile resources. For the purposes of this specification the term resource is taken to include any resource which may be moved within an area for example items of equipment or personnel.

A variety of resource controllers are known, for example it is known to use transponders or transceivers mounted on each resource to track its position within a work area. While systems of this type provide highly accurate resource tracking they are relatively expensive to implement particularly when it is necessary to track a large number of resources.

Alternatively the use of a smart card and associated reader unit is shown in PCT Patent Specification No.

WO 94/233999. Smart card units of this type provide a cheaper method of monitoring resources and allow implementation of area access control. Smart cards of this type however, contain a relatively small amount of information which is difficult to update. Another method of area access control with similar information limitations is shown in European Patent No. EP 0 314 361.

There is therefore a need for a resource controller which will overcome the aforementioned problems.

Accordingly, there is provided a resource controller comprising: a validation section, the validation section having a serial interface for receiving a data input, means for extracting a position dependent data type from the received data input and comparing the extracted data type with a pre-defined valid data type stored in a secure memory device, means for generating a valid result output when the data type of the data input and the valid data type match and means for recording the received data input; and a control section, the control section having a logic circuit for receiving the valid result output and actuation means for actuating a door release mechanism in response to an actuation signal from the logic circuit.

A resource controller formed in accordance with the invention has a number of advantages. The use of a validation section in this way logs receipt and stores data input received, in addition to eliminating the possibility of unauthorised access and guaranteeing the integrity of the resource information contained in the data input it allows the information to be stored for retrieval and processing. Advantageously this allows the information received to be used in planning resource utilisation and resource planning in addition to the tracking functions required.

Preferably the resource controller has timing means for controlling receipt of the data input. This ensures that the data input is accurately received by the resource controller using a minimum of components and eliminates receipt of erroneous signals in electrically noisy working environments.

Ideally, the timing means has an associated real time clock for recording a time of receipt of the data input thereby allowing the information received and stored by the resource controller to be used for resource utilisation planning, payroll payments or job costing without reference to a given hardware platform with which the resource controller may communicate.

Additionally this information is provided in real time as the information stored is updated with each data input.

In one arrangement the timing means is provided by a crystal oscillator and the real time clock is provided by a frequency divider connected to the crystal oscillator. Thus the timing mechanism is provided in an efficient and cost effective manner. Additionally, as the real time clock is derived from the timing means required for receipt of the data input the need for complex timing circuitry is eliminated.

Preferably the frequency divider includes a D type flip flop thereby minimising cost using readily available inexpensive components.

Preferably the validation section incorporates a data input latch for storing the data input as a data word.

This increases the flexibility of the resource controller as the data input may be derived form any suitable detector or reader device.

Preferably the data word includes a data input checksum for ensuring the correct receipt of the data input, in this way incorrect or incomplete data is not validated and therefore incorrect data inputs are not accepted.

Ideally the validation section has means for comparing the data input checksum with a pre-defined valid checksum type and means for generating a valid checksum output when the data input checksum and the valid checksum type match thereby guaranteeing the integrity of the system.

In one arrangement the means for generating a valid result output is a two input AND gate having one input connected to the valid checksum output.

Preferably the means for recording the received data input is a memory device having an enable pin connected to a result output pin of the AND gate. The use of a memory device in this way allows the information to be accessed both by the control section to allow entry and for additional processing in an integrated manner.

Preferably the validation section has means for sequentially addressing a plurality of pre-defined valid data types and a plurality of pre-defined valid checksum types provided by two eight bit comparators and an associated counter.

Preferably the logic circuit is provided by at least two NAND gates and an associated OR gate.

Preferably the actuation means is provided by a stepper motor and the door release mechanism is provided by a fifty volt solenoid thereby achieving the required access control function in a relatively simple manner.

Ideally the actuation means has an emergency override for actuating the door release mechanism in response to an emergency condition.

In one arrangement the door release mechanism has an associated audio device provided by a buzzer for signalling activation of the door release mechanism.

The invention will be more clearly understood from the following description of one embodiment thereof, given by way of example only, with reference to the accompanying schematic diagram of one possible embodiment of a resource controller.

For the purposes of this description, specific devices, timing and performance details have been omitted as they are of no importance to the operation of the invention.

Referring to the drawing, there is illustrated one possible embodiment of a resource controller according to the invention, indicated generally by the reference numeral 1.

The resource controller 1 has a validation section 2 and a control section 3. The validation section 2 has a serial interface 10 a line driver 11, a data input latch 12 and an ID comparator 13. The ID comparator 13 has an associated counter 14 an ID memory 15 and an active low ID latch 16. The data input latch 12 also has a checksum comparator 20 and an associated checksum latch 21 and a checksum memory 22. The validation section 2 also has an AND gate 25 and a resource memory 26.

The control section 3 has an eight MHz crystal oscillator 30, a frequency divider 31 and a resource clock 32. The control section 3 also has actuation means provided by a twelve volt stepper motor controller 40 and a solenoid 41. Operation of the stepper motor controller 40 is controlled by an OR gate 42, two pullup resistors 43, 44, two diodes 45, 46 and a NAND logic circuit 48. The NAND logic circuit 48 has associated conditioning circuitry provided by two buffers 51, 52, a resistor 53, a capacitor 54, a 5 volt rail 55 and an emergency override switch 56.

The solenoid 41 has associated circuitry provided by three resistors 60, 61, 62, capacitors 63, 64, 65, buffers 67, 68 and a buzzer 69.

In more detail the serial interface 10 has a clock input pin 101 for receiving a clock signal 102 from the crystal oscillator 30 and a data input pin 103 for receiving data from a personnel card reader (not shown).

The serial interface 10 has a data output pin 105 for transferring a data signal 106 to a data input pin 107 of the line driver 11. The serial interface 10 also has two control output pins 108, 109 for communicating control signals to the line driver 11. The line driver 11 has a serial output pin 111 for transmitting a data stream 112 to a data input pin 113 of the data input latch 12. The data input latch 12 has an ID output port 115 connected to an ID input port 116 of the ID comparator 13 by an eight bit ID databus 117. The data input latch 12 also has a checksum output port 120 connected to a checksum input port 121 by an eight bit checksum bus 123. The ID comparator 13 has a comparison output pin 125 for transmitting an ID comparator output signal 130 to a transfer enable pin 126 of the counter 14.The counter 14 has an ID memory address port 127 connected to an ID memory input port 128 of the ID memory 15 by an ID memory bus 129. The ID memory 15 in turn has a data output port 135 connected to an ID latch input port 136 of the active low ID latch 16. The active low ID latch 16 has an ID output port 140 connected to an ID input port 141 of the ID comparator 13 and to an ID memory input port 128 of the resource memory 26 by a resource ID bus 143.

The ID comparator output signal 130 is also connected to an enable input 150 of the checksum memory 22. The checksum memory 22 has a data input port 151 connected to a checksum memory address port 152 by a checksum memory address bus 153. The checksum memory 22 also has a data output port 154 connected to an input port 155 of the checksum latch 21. The checksum latch 21 has a checksum output port 160 connected to a checksum comparator input port 161 of the checksum comparator 20.

The checksum comparator 20 has a checksum comparator output pin 165 connected to a checksum input pin 166 of the AND gate 25. The AND gate 25 has an ID input pin 167 connected to the ID comparator output signal 130.

The AND gate 25 has a result output pin 180 connected to an enable pin 181 of the resource memory 26. The resource memory 26 also has a resource clock input port 182 communicating with a resource clock output port 183 of the resource clock 32 by a clock bus 184.

The resource clock 32 in turn receives a one hertz input pulse 200 at a pulse input pin 201. The pulse 200 is generated at an output pin 202 of the frequency divider 31. The frequency divider 31 in turn has a pulse input pin 210 connected to the crystal oscillator 30 by the clock signal 102.

The clock signal 102 is also connected to a clock input pin 300 of the stepper motor controller 40. The stepper motor controller 40 has a ground input pin 301 and a power input pin 302 connected to a twelve volt supply pin 303 by a twelve volt rail 304. The twelve volt rail 304 is also connected to the pull-up resistors 43, 44.

The pull-up resistor 43 is in turn connected to a direction input pin 305 of the stepper motor controller 40 and the pull-up resistor 44 is connected to a reset input 306 of the stepper motor controller 40. Operation of the direction input pin 305 is controlled by the output from the OR gate 42 and the diode 45. The OR gate 42 has two inputs 310, 311 for receiving signals 312 and 313 respectively from the NAND logic circuit 48.

The control signal 313 is connected to the diode 46.

The five volt input pin 55 is connected to the emergency override switch 56 by the resistor 53 and the capacitor 54. The emergency switch 56 is also connected to the NAND logic circuit 48 through the buffers 51 and 52.

The NAND logic circuit 48 has an enable input pin 400 connected to the result output pin 180. The NAND logic circuit 48 also has a door release output 401 connected to a transistor base 402 through a resistor 403. The transistor controls the operation of the solenoid 41 and the buzzer 69 through the buffers 67, 68, capacitors 63, 64, 65 and resistors 60, 62.

In use, a card carrying a magnetic strip is passed through a card reader and the identification code associated with that card is read in through the data input pin 103 of the serial interface 10. The data in this case is provided by a serial data stream from the magnetic strip and is passed through the data output pin 105 to the data input pin 107 of the line driver 11 providing the data signal 106. The control output pins 108 and 109 control the line driver 11 and ensure that the data signal 106 is transmitted correctly. The line driver 11 corrects the data signal 106 and passes the received data signal 106 from the serial interface to the data input pin 113 from the serial output pin 111 providing the data stream 112.

The data stream 112 is loaded into the sixteen bit data input latch 12 and the eight most significant bits are passed from the ID output port 115 to the ID input port 116 of the ID comparator 13. The eight bit data word appearing at the ID input port 116 is compared with the eight bit data word on the ID input port 141 received from the ID output port 140 of the ID latch 16. When the values are not the same the comparison output pin 125 transmits a logic zero bringing the ID comparator output 130 to ground. When the ID comparator output signal 130 is at ground potential the counter 14 increments due to the logic zero on the transfer enable pin 126. The active low ID latch 16 is also enabled to receive the contents of the ID memory 15 addressed by the value provided by the ID memory address port 127 of the counter 14 through the ID latch input port 136.By incrementing the counter each time the value is not found to match, i.e. non identical values being present at the ID input port 141 and the ID input port 116, each successive location in the ID memory 15 is addressed and the contents passed through the active low ID latch 16.

When the contents of the address memory location in the ID memory 15 is the same as the eight bit data word appearing at the data input port 116, the ID comparator outputs signal 130 is changed to a logic 1. The ID latch 136 is then disabled storing the ID latch 16 contents and avoiding changes to the value at the ID output port 140.

The checksum memory 22 is enabled by the ID comparator output signal 130 being logic one and presenting a logic one to the enable input 150 of the checksum memory 22.

The contents of the counter 14 are passed to the checksum memory address port 152 and used to decode the checksum memory 22 by being passed along the checksum memory address bus 153 into the data input port 151 of the checksum memory 22. The contents of the memory location associated with the value on the checksum memory address bus 153 is passed to the data output port 154 and into the checksum latch 21. The value is then passed through the checksum latch 21 and out through the checksum output port 160 and into the checksum comparator 20 through the checksum comparator input port 161. The value received at the checksum comparator input port 161 is compared with the value at the checksum input port 121 as received from the checksum output port 120 being the eight least significant bits of the value on the data input latch 12.

Providing the checksum associated with the eight least significant bits of the value on the data input latch 12 are the same as those in the checksum memory 22 as addressed by the value on the counter 14 the AND gate 25 receives a logic 1 at the checksum input pin 166 and the ID input pin 167 generating a logic one at the result output pin 180. The logic one at the result output pin 180 is passed to the enable pin 181 of the resource memory 26 enabling the value on the resource ID bus 143 being the addressed contents of the ID memory 15 to be loaded into the resource memory through the input port 142.

The time is also recorded in the resource memory by loading the contents of the resource clock onto the clock bus 184 through the resource clock output port 183 and into the resource memory 26 through the resource clock input port 182. The logic one at the result output pin 180 also enables the NAND logic circuit 48 passing control of the resource controller 1 from the validation section 2 to the control section 3. The eight Mhz crystal 30 provides the clock input to the serial interface 10 and to the stepper motor controller 40 for controlling the operation of both circuits and is divided by the frequency divider 31 to provide the one hertz input pulse 200 from the output pin 202 to the pulse input pin 201 of the resource clock 32 (this frequency division is achieved in this case using a number of D type flip flops, only one of which is shown for clarity).

The stepper motor controller 40 is provided with power from the twelve volt supply pin 303 and along the twelve volt rail. The NAND logic circuit 48 provides NAND signals 312, 313 to the OR gate inputs 310, 311 to control operation of the stepper motor controller 40 through the diode 45 and the direction input pin 305.

The reset input for the stepper motor controller 40 is similarly provided by the NAND signal 313 through the diode 46. The door mechanism is released by a logic one being connected to the door release output pin 401 of the NAND logic 48 which is passed to the base of the transistor 402 through the resistor 403. This allows a current to flow from the five volt rail 55 through the resistor 61 and to ground through the buzzer 69. In addition to sounding the buzzer 69 a current is also passed from the fifty volt input through the solenoid 41 to release the door lock. Chatter on the circuit is prevented by the buffers 67, 68, resistors 60, 61, 62 and capacitor 63, 64 and 65 and the monostable provided may be used to activate the solenoid and buzzer for a pre-set time.In the event of an emergency, the emergency override switch 56 may be pressed allowing a current to flow through the resistor 53 from the five volt rail 55 and through the buffer stages 51, 52 this bypasses operation of the NAND circuit to produce a logic 1 at the door release output pin 401 of the NAND logic 48 releasing the door mechanism and sounding the buzzer as before.

It will be appreciated that one skilled in the art that the invention herein described provides for a significantly improved resource controller for controlling personnel, guaranteeing security and provideing resource information for planning or costing purposes in real time.

It will further be appreciated that any suitable device may be used to implement the invention. For example, the magnetic card reader may be configured to read in data as a parallel word or input data may originate from a bar code reader, a badge detector or any similar device mounted on a resource.

The invention is not limited to the embodiments hereinbefore described which may be varied in both construction and detail. For example, it will be clear that the functionality of one or more of the components hereinbefore described may be combined and executed in application specific integrated circuits or in one or more software routines.

Claims

CLAIMS:

1. A resource controller comprising: a validation section, the validation section having a serial interface for receiving a data input, means for extracting a position dependent data type from the received data input and comparing the extracted data type with a pre defined valid data type stored in a secure memory device, means for generating a valid result output when the data type of the data input and the valid data type match and means for recording the received data input; and a control section, the control section having a logic circuit for receiving the valid result output and actuation means for actuating a door release mechanism in response to an actuation signal from the logic circuit.

2. A resource controller as claimed in claim 1 wherein the resource controller has timing means for controlling receipt of the data input.

3. A resource controller as claimed in claim 2 wherein the timing means has an associated real time clock for recording a time of receipt of the data input.

4. A resource controller as claimed in claim 3 wherein the timing means is provided by a crystal oscillator and the real time clock is provided by a frequency divider connected to the crystal oscillator.

5. A resource controller as claimed in claim 4 wherein the frequency divider includes a D type flip flop.

6. A resource controller as claimed in any preceding claim wherein the validation section incorporates a data input latch for storing the data input as a data word.

7. A resource controller as claimed in claim 6 wherein the data word includes a data input checksum for ensuring the correct receipt of the data input.

8. A resource controller as claimed in claim 7 wherein the validation section has means for comparing the data input checksum with a pre defined valid checksum type and means for generating a valid checksum output when the data input checksum and the valid checksum type match.

9. A resource controller as claimed in claim 8 wherein the means for generating a valid result output is a two input AND gate having one input connected to the valid checksum output.

10. A resource controller as claimed in claim 9 wherein the means for recording the received data input is a memory device having an enable pin connected to a result output pin of the AND gate.

11. A resource controller as claimed in any preceding claim wherein the validation section has means for sequentially addressing a plurality of pre-defined valid data types and a plurality of pre-defined valid checksum types provided by two eight bit comparators and an associated counter.

12. A resource controller as claimed in any preceding claim wherein the logic circuit is provided by at least two NAND gates and an associated OR gate.

13. A resource controller as claimed in any preceding claim with reference to the accompanying drawing.

13. A resource controller as claimed in any preceding claim wherein the actuation means is provided by a stepper motor and the door release mechanism is provided by a fifty volt solenoid.

14. A resource controller as claimed in any preceding claim wherein the actuation means has an emergency override for actuating the door release mechanism in response to an emergency condition.

15. A resource controller as claimed in any preceding claim wherein the door release mechanism has an associated audio device provided by a buzzer for signalling activation of the door release mechanism.

16. A resource controller as claimed in any preceding claim with reference to the accompanying drawing.

Amendments to the clalms have been filed as follows 1. A resource controller comprising a validation section comprising a serial interface for receiving a data input, means for extracting a position dependent data type from the received data input and comparing the extracted data type with a pre-defined valid data type stored in a secure memory device, means for generating a valid result output when the data type of the data input and the valid data type match and means for recording the received data input; and timing means connected between the validation section and a control section, the timing means comprising a crystal oscillator, means for controlling receipt of the data input, and an associated real time clock provided by a frequency divider recording a time of receipt of the data input, the control section comprising a logic circuit connected to the crystal oscillator for receiving the valid result output and actuation means for actuating a door release mechanism in response to an actuation signal from the logic circuit.

2. A resource controller as claimed in claim 1 wherein the frequency divider includes a D type flip flop.

3. A resource controller as claimed in claims 1 or 2 wherein the validation section incorporates a data input latch for storing the data input as a data word.

4. A resource controller as claimed in claim 3 wherein the data word includes a data input checksum for ensuring the correct receipt of the data input.

5. A resource controller as claimed in claim 4 wherein the validation section has means for comparing the data input checksum with a pre defined valid checksum type and means for generating a valid checksum output when the data input checksum and the valid checksum type match.

6. A resource controller as claimed in claim 5 wherein the means for generating a valid result output is a two input AND gate having one input connected to the valid checksum output.

7. A resource controller as claimed in claim 6 wherein the means for recording the received data input is a memory device having an enable pin connected to a result output pin of the AND gate.

8. A resource controller as claimed in any preceding claim wherein the validation section has means for sequentially addressing a plurality of pre-defined valid data types and a plurality of pre-defined valid checksum types provided by two eight bit comparators and an associated counter.

9. A resource controller as claimed in any preceding claim wherein the logic circuit is provided by at least two NAND gates and an associated OR gate.

10. A resource controller as claimed in any preceding claim wherein the actuation means is provided by a stepper motor and the door release mechanism is provided by a fifty volt solenoid.

11. A resource controller as claimed in any preceding claim wherein the actuation means has an emergency override for actuating the door release mechanism in response to an emergency condition.

12. A resource controller as claimed in any preceding claim wherein the door release mechanism has an associated audio device provided by a buzzer for signalling activation of the door release mechanism.