GB2306240A

GB2306240A - Multiplexed electrical control systems

Info

Publication number: GB2306240A
Application number: GB9621400A
Authority: GB
Inventors: Jonathon Chard; Kevin Trevor Talbot
Original assignee: MG Rover Group Ltd
Current assignee: MG Rover Group Ltd
Priority date: 1995-10-14
Filing date: 1996-10-14
Publication date: 1997-04-30
Anticipated expiration: 2016-10-14
Also published as: GB9621400D0; GB2306240B; GB9521057D0

Abstract

A multiplexed electrical control system comprises a master station 10 and a plurality of slave stations 12, 14, 16 each having a microprocessor connected via a UART to a bus 15, the slave stations 12, 14, 16, being arranged to send out slave messages on the bus in response to headers addressed to them by the master station 10. Each byte of the slave message is sent out directly in response to a header message H addressed to the slave station, or an interrupt signal sent by the UART to the microprocessor in the slave station. Each header in a sequence of messages is sent out by the master when it detects that the previous slave message has been completed. This is done by counting the number of bytes using the UART interrupt signals. This eliminates the need for an accurate independent clock in each slave station to co-ordinate the multiplexing.

Description

Multiplexed Electrical Systems The present invention relates to multiplexed electrical systems, such as those used in vehicles, and in particular to improvements in the method of timing of signals in such systems.

It is an aim of the present invention to provide a multiplex system in which the timing can be controlled efficiently and cheaply.

Accordingly the present invention provides a multiplexed electrical control system comprising a master station and a plurality of slave stations all connected to a bus, each slave station being arranged to send out a slave message comprising one or more bytes of data on the bus in response to a header message sent by the master station and addressed to it, the master station being arranged to monitor transmission of the slave messages and to send out at least one of the header messages in response to transmission of a complete slave message from the previously addressed slave station.

Preferred embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings in which: Figure 1 is a diagrammatic representation of an electrical system according to the invention, and Figure 2 shows the sequence of signals in the system of Figure 1.

Referring to Figure 1, an asynchronous multiplexed vehicle electrical system comprises a master station 10 in the form of a control unit for the body electronics of a vehicle, first and second slave stations 12, 14, on the front doors and a third slave station 16 for the sunroof.

The master and slave stations 10, 12, 14, 16, are all connected to a single wire bus 15 through which all signals between the stations are transmitted. Each of the stations 10, 12, 14, 16 comprises a microprocessor 17 and a universal asynchronous receiver/transmitter (UART) 18. The microprocessor in the master station 10 includes an accurate clock 19 in the form of a crystal oscillator.

The microprocessor 17 in the master station 10 has eight connections 20 which are connected to the master station UART 18. These enable the microprocessor 17 to present eight parallel bits of data to the UART to be transmitted on the bus 15, or to receive eight bits of data from the UART simultaneously. A UART interrupt line 22 between the UART and the microprocessor 17 is used by the UART to transmit interrupt messages communicating its status to the microprocessor 17. The UART 18 transmits 'message received' and 'message transmitted' signals to the microprocessor to indicate reception or complete transmission of a byte of data on the bus. The microprocessor 17 responds to a 'message received' signal by reading the byte of data from the UART, and responds to a 'message transmitted' signal by presenting another byte of data for transmission, or waiting for receipt of data in reply.

Each of the slave stations 12, 14, 16 has a microprocessor 12a, 14a, 16a and a UART 12b, 14b, 16b for transmitting and receiving messages via the bus 15. These operate in the same manner as the master station.

The order of the transmission of data on the bus is structured and follows a sequence defined by the master microprocessor 17, as shown in Figure 2, the stations each sending out data in turn. After a bus quiet time when neither the master nor the slave stations have been transmitting, communication is initiated by the master 10 transmitting a header message H. The header message H comprises a single byte which either indicates that there will follow some information from the master 10 and identifies the slave or slaves to which that data is addressed, or indicates that the master is ready to receive data from one of the slaves and identifies which slave is required to send that data, or indicates that one of the slaves should transmit data for reception by another slave.

In the example shown the first header message H indicates that the master 10 is about to send data to two of the slave stations, in this case the two door outstations 12, 14. When the master UART 8 has transmitted this header message it sends a 'message transmitted' signal to the master microprocessor 17 which then sends the first data byte D to the master UART 8 for transmission. The remaining data bytes D are sent in the same way, followed by a check message C. This comprises a single byte, the bits of which are determined by all the preceding bytes in known manner, including the header byte H.

When the master 10 has sent out its entire data message, it then transmits a second header H1 which is addressed to the first slave station 12 and represents a request for it to respond. This header Hl is received by the UART 12b in the first slave station 12 which sends a 'message received' signal to the microprocessor 12a. The microprocessor 12a checks the header and, when it has determined that the header H1 is addressed to it presents the first byte of slave data Ds to the UART 12b for transmission. When this has been transmitted onto the bus the UART 12b sends a 'message transmitted' interrupt signal to the microprocessor 12a which then presents the next byte of data Ds to the UART 12b. The remaining data bytes Ds of the message from the first slave station 12 are then transmitted in the same way, followed by a checksum byte C.

The master station 10 reads all of the bytes of the slave message from its UART 18 as they are received. When the expected number of bytes, including the checksum byte C, has been received from the first slave station 12, the master station 10 sends out a third header H2, addressed to the second slave station 14, which is a request to the second slave station 14 to respond. In this case the information to be transmitted is required by the first slave station 12. The header H2 is received by the UART 14b in the second slave station 14 and passed on to the microprocessor 14a. The second slave station 14 responds to receipt of the header H2 by transmitting its data bytes Ds and a checksum byte C in the same way as the first slave station.The first slave station 12 also receives the header H2 and recognizes it as an indication that information from the second slave station 14 will follow.

It therefore reads the following data bytes Ds from its UART 12b as they are received.

The master station 10 monitors the transmission of data from the second slave station 14 by counting the number of data bytes using the ''message received' interrupts from its UART. When the last byte, which is the checksum byte C from the second slave station 14 has been received by the master 10, the sequence of messages ends and the bus goes quiet again. When the master station 10 needs to start another sequence of messages it will do so by issuing another header message onto the bus 15.

As described above, the trigger for the master station to send out the header messages H1 H2 is the receipt by the master station 10 of the last byte of each slave message.

This can be determined by the receipt by the master microprocessor 17 of a number of message received interrupt signals corresponding to the number of bytes expected from the slave. This is particularly useful where the slave stations are very simple and the slave message comprises a small amount of information, such as the position of a switch. Alternatively, or as an additional check, the end of the slave massage can be detected by a suitable indicator in the slave message. Where the last byte of the slave message is a checksum byte, this can be recognized as indicating the end of the message.

If the master station sends out a header to one of the slaves requesting transmission of a number of bytes of data in response, and the data is not properly transmitted or received for any reason, the master station needs to be able to proceed with communications with the other slaves.

This is achieved by setting a time-out period in the master station microprocessor 17 such that, if the microprocessor does not detect complete transmission of a slave message within the time-out period after it has sent a header, it will proceed to the next message in the communication. This will generally be to send out another header addressed to a different slave station.

A convenient way to identify the header and checksum bytes as such is by using a ninth bit in the header and checksum bytes. Such a ninth bit is conventionally used as a parity bit to set the parity of the byte. This is for a simple error check, which is not needed in the arrangement described here because of the use of the more sophisticated checksum bytes. The remaining eight bits of the header bytes are used to identify the slave station to which the header is addressed, and the remaining eight bits of the checksum bytes are used to provide the check code which is dependent on all the other bytes in the message. The data bytes can then have only eight bits.

It will be understood that, in the embodiment described above, the control of the timing of the messages within the sequence is carried out by the master station 10 on the basis of the UART interrupt signals. There is therefore no need to use a clock or other independent timing means in the slave stations to synchronise the transmission of messages on the bus by the master and slaves. Although the slaves will have to include some form of clock to enable the transmission and reception of data, the accuracy of these clocks only has to be sufficient for the slaves to be in agreement with the master as to which bit of data is which, within a particular message.

It will also be appreciated that the system described provides a way of communicating between a large number of substations which is efficient in terms of both the speed of transmission, and the amount of wiring required.

Claims

1. A multiplexed electrical control system comprising a master station and a plurality of slave stations all connected to a bus, each slave station being arranged to send out a slave message comprising one or more bytes of data on the bus in response to a header message sent by the master station and addressed to it, the master station being arranged to monitor transmission of the slave messages and to send out at least one of the header messages in response to transmission of a complete slave message from the previously addressed slave station.

2. A control system according to claim 1 wherein the master station detects transmission of a complete slave message by recognizing an indicator which indicates which is the last byte of the slave message.

3. A control system according to claim 2 wherein the master station detects transmission of a complete slave message by recognizing a checksum byte in the slave message.

4. A control system according to any foregoing claim wherein the master station detects transmission of a complete slave message by detecting receipt of the expected number of bytes of the slave message.

5. A control system according to any foregoing claim wherein the master station includes a transmitting and receiving means and processing means, the transmitting and receiving means being arranged to communicate its status to the processing means by means of interrupt signals.

6. A control system according to claim 5 wherein the transmitting and receiving means is arranged to send a message transmitted interrupt signal when it has transmitted a byte of a message onto the bus.

7. A control system according to claim 5 or claim 6 wherein the transmitting and receiving means is arranged to send a message received interrupt signal when it has received a byte of a message from the bus.

8. A control system according to claim 7 wherein the master station is arranged to detect transmission of a complete slave message by counting the number of message received interrupt signals sent by the transmitting and receiving means.

9. A control system according to any foregoing claim wherein the master station and slave stations send their respective messages on the same bus.

10. A control system according to any foregoing claim wherein each slave station includes a transmitting and receiving means and a processing means.

ll.A control system according to claim 10 wherein the processing means is arranged to detect reception of a header message addressed to the slave station and respond by enabling transmission of a slave message by the transmitting and receiving means.

12.A control system according to claim 10 or claim 11 wherein the slave station processing means is arranged to communicate each byte of a slave message to the transmitting and receiving means only on receipt of a header addressed to it, or in response to an interrupt signal from the transmitting and receiving means that a previous byte of the slave message has been transmitted.

13. A control system according to any foregoing claim wherein the transmitting and receiving means is a universal asynchronous receiver/transmitter.

14. A control system according to any foregoing claim wherein each header comprises a byte of information.

15. A control system according to claim 14 wherein each header has a plurality of bits, one of which is used to identify the byte as a header.

l6.A control system according to claim 15 wherein the remaining bits of each header identify the slave station to which the header is addressed.

17.A control system according to any foregoing claim wherein each message from the master station or the slave stations includes a block of information which provides a check on data in the message.

18. A control system according to claim 14 wherein each said block comprises a check byte of information.

19.A control system according to claim 18 wherein each check byte has a plurality of bits, one of which is used to identify the byte as a check byte.

20.A control system according to claim 19 wherein the remaining bits of each check byte provide the check.

21.A control system according to claim 17 wherein the headers and the check bytes have the same number of bits, and each have one more bit than other bytes in the messages.

22.A control system substantially as hereinbefore described with reference to the accompanying drawings.