GB2299231A - Improving slew rate and stability of follower output stage for differential amplifier by charging gates of FETs - Google Patents

Abstract

A switching circuit (110) for an output stage of an operational amplifier is disclosed which includes a first transistor (112) having a first current guiding electrode (112a) connected to a first power supply rail (Vcc), a second current guiding electrode (112b) connected to an output terminal, and a control electrode (112c), a second transistor (114) having a first current guiding electrode (114a) connected to a second power supply rail (GND), a second current guiding electrode (114b) connected to said output terminal, and a control electrode (114c), an impedance (116) coupled between the control electrode (112c) of the first transistor (112) and the control electrode (114c) of the second transistor (114), and control circuitry (120a, 120b) for applying a pulse to the control electrode (112c, 114c) of the first or second transistors (112, 114), said pulse being generated at an edge of a transition in input signal waveforms such that charging and discharging at the control electrodes (112c, 114c) of said first and second transistors (112, 114) is assisted.

Description

IMPROVEMENTS IN OR RELATING TO CLOSED LOOP VOLTAGE FOLLOWERS The present invention is related to electrical circuits, and more particularly to voltage followers having a closed loop configuration.

Typically, operational amplifiers (Op-Amps) have a finite open-loop output impedance which may cause difficulties if the Op-Amp is used to drive a capacitive load. Lagging phase shifts produced by the output impedance in combination with the capacitive load to ground can generate feedback instabilities.

Several methods of overcoming these problems are known in the art, but each typically introduces further difficulties. For example, if a split feedback path technique is utilised a degradation in the high-frequency performance of the Op-Amp occurs, since feedback is not operative at high frequencies on the signal.

An alternative approach is to introduce a unity-gain highcurrent buffer into the feedback loop. Typically, these buffers have no significant phase-shift up to the unity-gain frequency of most op-amps, and can be introduced into the feedback loop without any additional frequency compensation.

Two configurations of unity gain buffer are known in the art; open-loop configuration and closed-loop configuration.

Typically, the open-loop configuration is an emitter follower or a source electrode follower circuit as is commonly used in electronic circuits. The open-loop configuration has the advantage of high speed operation but suffers from low DC accuracy. Conversely, the closed-loop configuration offers much improved DC accuracy, but can never match the speed of operation of the open-loop configuration.

Typically, the most demanding operational requirement of unity gain buffers of either configuration, is the buffering of a high frequency, high slew rate square wave while maintaining accurate control of the steady-state amplitude.

Therefore, a need exists for an operational amplifier with a reduced output settling time, which is capable of receiving a high frequency, high slew rate square wave which is capable of maintaining accurate control of steady state amplitude.

Accordingly, the present invention provides a switching circuit for an output stage of an operational amplifier comprising; a first transistor having a first current guiding electrode connected to a first power supply rail, a second current guiding electrode connected to an output terminal, and a control electrode, a second transistor having a first current guiding electrode connected to a second power supply rail, a second current guiding electrode connected to said output terminal, and a control electrode, an impedance coupled between the control electrode of the first transistor and the control electrode of the second transistor, and control circuitry for applying a pulse to the control electrode of the first or second transistors, said pulse being generated at an edge of a transition in input signal waveforms such that charging and discharging at the gate electrodes of said first and second transistors is assisted.

The present invention will be further described by way of example, with reference to the accompanying drawings, in which; Figure 1 is a diagram of the circuit of prior art output stage of a rail to rail push-pull operational amplifier; Figure 2 shows waveforms of a shape which are derived from the circuit of Figure 1; Figure 3 is a diagram of a preferred circuit of an output stage for reducing the setting time at the output of an operational amplifier for use in accordance with the invention; Figure 4 show waveforms of a shape which are derived from the circuit of Figure 3; Figure 5 is a diagram of a circuit for limiting overshoot at the output of the circuits of Figure 3; and Figure 6 shows waveforms of a shape which is derived from the circuit of Figure 5.

Figure 1 illustrates the circuit 10 of an output stage of a rail-to-rail push-pull operational amplifier not shown. The circuit 10 includes an n-channel metal-oxide semiconductor field effect transistor 12, or MOSFET and p-channel MOSFET 14, and an impedance 16.

The transistor 12 has a source electrode 12a connected to the voltage supply rail Vcc, and a drain electrode 12b connected to a drain electrode 14b of transistor 14. The source electrode 14a of the transistor 14 is connected to a ground potential supply rail GND. The impedance 16 is connected between the gate electrode 12c and the gate electrode 14c of the transistors 12 and 14 respectively.

As discussed earlier herein, the illustrated output stage is designed to be operable in Class AB. In operation, the voltage across impedance 16 determines the relative degree of Class A or Class B introduced into the output stage.

If the voltage across the impedance 16 is constant i.e.

voltage VAB between nodes A and B is constant, then a change in the voltage at either node A or node B would cause a voltage change at the output. The ratio of the change in voltage at the output as compared to the input determines the output stage gain. If the output stage is required to drive a low output impedance a limitation on the output voltage range will be reached at the high or low voltage extremes. This limitation is determined by the impedance between the drain electrode and source electrode regions of the transistor 12 or 14 when conducting. One solution to this problem is to use high aspect ratio MOS devices to maintain an acceptable dropout. However, the capacitive loading at nodes A or B can be large due to the capacitance of large output devices. This is generally attributed to Miller Effect.

Large capacitive loading at nodes A or B can result in slewrate limitation of the output response as illustrated in Figure 2. Large capacitive loading on a preceding driver stage will cause a delay in toggling the gate electrodes of the output devices. As previously stated, square waves are particularly prone to this difficulty.

Referring now to Figure 3, a preferred circuit 110 of an output stage of the invention is illustrated. The circuit 110 includes an n-channel metal-oxide semiconductor field effect transistor 112, a p-channel MOSFET 114, and an impedance 116.

The transistor 112 has a source electrode 112a connected to the voltage supply rail Vcc, and a drain electrode 112b connected to a drain electrode 114b of transistor 114. The source electrode 114a of the transistor 114 is connected to a ground potential supply rail GND. The impedance 116 is connected between the gate electrode 112c and the gate electrode 114c of the transistors 112 and 114 respectively.

Furthermore, an output terminal is connected between the drain electrode 112b of transistor 112 and the drain electrode 114b of transistor 114.

A pair of control circuits (120a, 120b) are connected to the gate electrodes (112c, 114c) of transistors 112, 114 respectively. Each control circuit (120a, 120b) includes an p-channel MOSFET (122a, 122b) and a n-channel MOSFET (124a, 124b). The source electrode 122x of each p-channel transistor (122a, 122b) are connected to the voltage supply rail Vcc, and the source electrode 124x of each n-channel transistor (124a, 124b) are connected to a ground potential supply rail GND.

The drain electrode 122y of each p-channel transistor (122a, 122b) are connected to the drain electrode 124y of the nchannel transistor (124a, 124b) of the corresponding pair.

The drain electrode electrodes (122y, 124y) of each pair are further connected to either node A or node B.

The gate electrode 122z of the n-channel transistors (122a, 122b) are coupled to a node C, and the gate electrode 124z of the p-channel transistor are coupled to a node D.

In operation, when zero volts is applied to the C nodes of the control circuits 120a, 120b, the gate electrodes 122z are pulled low. Therefore, transistors (122a, 122b) are caused to conduct pulling nodes A and B high. Consequently, gate electrode 112c will be high causing transistor 112 to be nonconducting and gate electrode 114c will be high causing transistor 114 to be conducting resulting in the output being pulled low.

Similarly, if Vcc is applied to the D nodes of the control circuits (120a, 120b), the gate electrode electrodes 124z nodes A and B low. Consequently, gate electrode 114c will be high and transistor 114 is caused to be conducting and gate electrode 112c will be low causing transistor 112 to be nonconducting. This results in the output being pulled high.

The size of transistor 122a of the first control circuit 120a relative to transistor 122b of the second control circuit 120b can be selected to cause equal rise and fall time of the voltages at nodes A and B, since the source electrode-drain electrode voltages of the transistors (112, 114, 122a, 122b, 124a, 124b) will all be different and the sizes of transistors 112 and 114 will be different.

In operation, pulses are generated on the edges of square wave transitions which are provided at nodes C and D. These pulses are short, the period of the pulse being selected to produce the desired slew rate at the output. The pulses assist the charging process at nodes A and B, an example of input and output waveforms being illustrated in Figure 4. Following the application of pulses to nodes C and D, normal closed loop action prevails with the control circuits 120a, 120b inoperative and DC accuracy unaltered.

However, this increase in slew rate can be at the expense of possible overshoot. Overshoot may be minimised by connecting a limiter 200 to the buffered output. The limiter is operative at a higher voltage than the maximum DC amplitude of the square wave under extreme conditions. The addition of the limiter 200 does not affect the closed loop operation of the output stage. An example of a suitable limiter circuit is illustrated in Figure 5, although other clamp circuits may be suitable.

The limiter 200 includes an operational amplifier 202 including two input terminals and an output terminal. The first input terminal 201a is connected to the output of output stage 110, and the output terminal 201c is connected to the second input terminal 201b.

The output terminal 201c is also coupled to the drain and gate electrodes of NMOS transistor 204. The source electrode of the transistor 204 is coupled to receive a bias voltage Vbia5.

The output terminal 201c is also coupled to the source electrode of PMOS transistor 206, the gate and drain electrodes being coupled to receive a bias voltage Vbias1.

In operation, the limiter 200 has no effect, with the exception of capacitive loading, if the output lies between; (VH13S2 + VTP) and (Vbias1 - VTE-) or the high and low.

If the output swings below; (Vbias1 - V-) due to overshoot, transistor 206 actuates injecting current onto the output line to prevent the voltage falling further. Similarly if the output overshoots to above (Vbias2 + VTN), transistor 204 will actuate and cause the output node to discharge.

The output voltage is thus clamped such that the following condition exists; (VbLa51 VTP) # Vo/p # (VblaSL + VTN) The resulting improvement in overshoot is illustrated in Figure 6, which shows a first waveform generated by the output circuit of the invention with no limiter circuit, and a second waveform generated by the circuit with a limiter 200.

Although the present invention has been illustrated with reference to the illustrated embodiments, various alternative embodiments which fall within the spirit and scope of the present invention will be apparent to those skilled in the art upon reference to this description.

Claims (5)

1. A switching circuit for an output stage of an operational amplifier comprising; a first transistor having a first current guiding electrode connected to a first power supply rail, a second current guiding electrode connected to an output terminal, and a control electrode; a second transistor having a first current guiding electrode connected to a second power supply rail, a second current guiding electrode connected to said output terminal, and a control electrode; an impedance coupled between the control electrode of the first transistor and the control electrode of the second transistor; control circuitry for applying a pulse to the control electrode of the first or second transistors, said pulse being generated at an edge of a transition in input signal waveforms such that charging and discharging at the control electrodes of said first and second transistors is assisted.

2. The switching circuit according to Claim 1, wherein the control circuitry comprises separate control circuits for the first and second transistors.

3. The switching circuit according to Claim 2, wherein the or each control circuit comprises; a third transistor having a first current guiding electrode connected to the first power supply rail, a second current guiding electrode connected to the control electrode of the first or second transistors, and a control electrode for receiving a control signal; and a fourth transistor having a first current guiding electrode connected to the second power supply rail, a second current guiding electrode connected to the control electrode of the first or second transistor, and a control electrode for receiving a control signal.

4. The switching circuit according to any of Claims 1 to 3 further comprising; a limiter circuit connected to the output terminal, the limiter circuit being capable of clamping signals at the output terminal to a predetermined voltage such that overshoot is substantially eliminated.

5. A switching circuit for an output stage of an operational amplifier substantially as herein described with reference to Figures 3 to 6 of the accompanying drawings.