GB2298977A - Tuner with gain control in dependence on locked/unlocked state of PLL - Google Patents

Abstract

A tuner circuit for TV, VCR, radio or other use comprises a high frequency amplifier (2), the gain of which is controlled by an automatic gain control (AGC) and a PLL circuit (5). In order to reduce abnormal effects before the PLL is locked, a signal from the PLL lock detect terminal (8) is used to control a switch (10) which reduces the level of the input AGC voltage to the amplifier only when the PLL is unlocked.

Description

ELECTRICALLY TUNED TUNER This invention relates to an electrically tuned tuner. In particular, it relates to an RF tuner for use in the tuning circuit of a television or video apparatus, or for the reception of radio or other RF signals.

Along with most other electronic equipment, there is a continuing drive to miniaturise the size of electrically tuned tuners to reduce product size and weight. However, as the size of devices such as tuners decreases, so problems arise due to their size and the proximity of their components to each other. One of these problems is described below.

Figure 1 shows a typical conventional electrically tuned tuner. In such a circuit, a signal received at an antenna input terminal 1 is amplified by a high frequency amplifier 2 and inputted into a mixer 3 where it is mixed with a local oscillator signal from a local oscillator circuit 6. The resulting intermediate frequency (IF) signal is outputted to an IF signal output terminal 4. The IF signal is then used as desired, typically by being applied to an IF demodulator for detection and subsequent viewing or recording of the TV signal for example. The output signal of the local oscillator circuit 6 is also inputted into a phase locked loop (PLL) circuit 5. Any change in the tuning voltage caused by the signal from the local oscillator is supplied to each of the tuning components in three tuning circuits.

A first tuning circuit 9A is used to tune the input terminal. A second tuning circuit 9B is used to tune the signal entering the mixer and a third tuning circuit 9C is applied to the local oscillator circuit.

The PLL circuit can include a terminal 8 which is a lock signal detector to detect whether the PLL is locked or unlocked. Typically, different logic levels may be present at terminal 8 dependent upon whether the PLL is locked or unlocked. For instance, as shown in Figure 3, the level may be low when the PLL is locked and high (e.g. about 5 volts) when the PLL is unlocked. The output of an automatic gain control (AGC) circuit is also applied to the high frequency amplifier circuit. AGC circuits are a standard feature on many tuners and are essentially used to adjust the gain of amplifying circuit 2 to compensate for variations in input signal levels.

The AGC is generally derived from the level of the signal received by a subsequent IF demodulator. If the input signal at input terminal 1 is low then the AGC increases the gain of amplifier 2 to increase the signal level. If the signal received at input terminal 1 is high then the AGC provides only moderate or low gain and thus the signal level at the mixer is intended to remain constant regardless of input signal strength.

However, there is a weakness in that if the PLL circuit detects signals other than the local oscillator signal, abnormal operation is caused so that normal receiving cannot be achieved. This may happen when the high frequency and comparatively high input signal from antenna input terminal 1 is further amplified, say about a hundred times by the high frequency amplifier 2 and therefore inputted into the PLL circuit 5 through the mixer circuit 3, the local oscillator 6, or the other tuning circuits 9. As stated above, this situation should not normally be a problem since the degree of amplification in the high frequency amplifier 2 should be reduced when a large signal is input to antenna terminal 1 because the AGC voltage would be proportionately changed according to input signal magnitude to maintain constant signal level at the mixer input circuit 3.In practice, however, a problem does remain and it is exacerbated as miniaturisation progresses. When a receiving channel is changed so that a comparatively larger signal level is received than before the change, then the degree of amplification remains at its highest level, or the same level as that for the previously received signal. This is because the AGC voltage level does not change instantly since the time constant of the AGC circuit is greater than that of the PLL lock circuit. Therefore, when the PLL circuit is not operating normally an abnormal IF signal, which may be distorted for example, due to a too high signal strength, is outputted from the tuner and this is not detectable by the IF demodulator AGC circuit.

Therefore, the AGC voltage which is outputted from the IF demodulator AGC circuit to the tuner AGC terminal 7 remains at its previous high setting. This condition will remain and therefore prevent signal reception.

The present invention arose in an attempt to overcome the above problems.

According to the present invention there is provided a tuner circuit comprising an amplifier, the gain of which is altered by an automatic gain control (AGC) input and a PLL circuit, and means for varying the level of the AGC input in accordance with whether the PLL circuit is locked or unlocked.

According to the present invention there is further provided a method of improving the performance of a tuner comprising an amplifier, the gain of which is altered by an AGC input, and a PLL circuit, the method comprising reducing the level of the AGC inputted to the amplifier when the PLL circuit is unlocked.

Embodiments of the invention will now be described, by way of example only, with reference to accompanying drawings in which; Figure 1 shows a conventional tuner circuit; Figure 2 shows a tuner circuit with switched AGC; Figure 3 shows output signals from a PLL locked/unlock detector terminal; Figure 4 shows an alternative tuner circuit with switched AGC; and Figure 5 shows an alternative output from the PLL locked/unlocked terminal.

Referring to Figure 2, a tuning circuit according to the present invention is similar to that of a conventional circuit apart from the provision of a switching means between an output of the PLL circuit and the AGC input 7 to the high frequency amplifier circuit 2.

In the example shown in Figure 2 the switch comprises an NPN type transistor 10 having its collector connected to the AGC voltage terminal 7 and its base connected to the PLL lock detector signal output terminal 8 via a resistor 11. In use, an AGC voltage from an IF demodulator (not shown) corresponding to a signal inputted to the antenna input terminal is present at the AGC voltage terminal 7.

If no signal has been previously inputted, then the AGC voltage will be such as to give maximum gain from amplifier 2. When the PLL circuit is locked (i.e. when the local oscillator frequency matches the set frequency) then a signal is outputted from the lock detector output terminal 8 as shown in Figure 3. The signal in this case is at low level. When the oscillator is unlocked, i.e. when the local oscillator does not match the set frequency, then a high level is held.

Thus, under locked conditions, the AGC voltage supplied is applied directly to the AGC voltage terminal 7 since there is a high impedance between the collector and emitter of transistor 10, this impedance being sufficiently high compared to the input impedance of the AGC circuit. The emitter of transistor 10 is connected to ground via a resistor 12, as will be described below.

However, when the PLL is unlocked, i.e. in the period from immediately after a tuning operation starts until the tuning operation finishes in the PLL circuit, the lock detector signal is kept HIGH. The transistor 10 in this case is switched on and therefore has a low impedance between its collector and emitter, resulting in the AGC voltage terminal being connected to ground through resistor 12. Hence, the AGC voltage actually applied to the high frequency amplifier 2 is determined by the original AGC voltage divided by the AGC circuit impedance and the impedance of resistor 12. Thus, the AGC signal is kept low during this time. Indeed, if resistor 12 were not present then the AGC voltage applied to the amplifier circuit at this time would be zero.

The high frequency amplifier 2 keeps an appropriate degree of amplification because the AGC voltage supplied corresponds to the input signal before the start and after the finish of tuning in the PLL circuit. During tuning operations in the PLL circuit the degree of amplification in the amplifier 2 is greatly reduced and hence the flow of high frequency input signals into the PLL circuit is suppressed to enable the PLL circuit to operate normally.

The resistors 12 and 13 are used for setting the AGC voltage which gives the lowest acceptable gain in the high frequency amplifier. Resistor 13 is connected to, e.g. a power supply terminal 15 (for example 5V). The setting of resistors 12 and 13 will therefore depend on the circuit and type of signal being received. They may be variable.

In effect, by using apparatus according to the present invention stable receiving of signals is possible without abnormal operation of the PLL circuit because during the tuning operation, and therefore in the period before the PLL circuit can lock, the gain of the high frequency amplifier is reduced to a minimum. Hence large input signals are not further amplified to a level at which they can interfere with the PLL circuit and cause this to enter a state of permanent unlock.

In the above described embodiment, a transistor is used as a switch. It will be appreciated that any other type of switch may be used. Figure 4 for example shows the use of a diode 14. This circuit may be used where the PLL lock detector terminal is arranged to be high when the PLL is locked and low when the PLL is unlocked (Figure 5). Thus, when the PLL is unlocked, terminal 8 is at low potential and the diode 14 conducts.

Many other switching means may be used such as FET's or even the lock detector signal output terminal and the AGC voltage terminal may be connected directly together or connected via a resistor for example. Electro-mechanical or optical switches may be used for example.

Claims (12)

1. A tuner circuit comprising an amplifier, the gain of which is altered by an automatic gain control (AGC) input, a PLL circuit, and means for varying the level of the AGC input in accordance with whether the PLL circuit is locked or unlocked.

2. A tuner circuit as claimed in Claim 1, including means for using a PLL lock/unlock detect voltage to alter the level of the AGC input.

3. A tuner circuit as claimed in Claim 2, wherein the level varying means is a switch means acting on an AGC input to the amplifier and controlled by a voltage at a PLL lock detect terminal.

4. A tuner circuit as claimed in Claim 3, wherein the switch is a transistor switch.

5. A tuner circuit as claimed in any one of Claims 1 to 3, wherein the level varying means includes a diode.

6. A tuner circuit as claimed in any of Claims 1 to 5, wherein the level of the AGC input is reduced when the PLL is unlocked.

7. A tuner circuit substantially as hereinbefore described with reference to, and as illustrated by, Figures 2 to 5 of the accompanying drawings.

8. A method of improving the performance of a tuner comprising an amplifier, the gain of which is altered by an AGC input, and a PLL circuit, the method comprising reducing the level of the AGC inputted to the amplifier when the PLL circuit is unlocked.

9. A method as claimed in Claim 8, wherein when the PLL circuit is locked, normal AGC operation is maintained.

10. A method as claimed in Claim 8 or Claim 9, wherein a PLL lock/unlock detect voltage is used to reduce the level of the AGC inputted to the amplifier when the PLL is unlocked.

11. A method as claimed in Claim 10, wherein the voltage is used to control a switch.

12. A method of improving the performance of a tuner substantially as hereinbefore described with reference to the accompanying drawings.