GB2297873A - Reversing light and audible warning control circuit - Google Patents

Abstract

An auxiliary load is energised when the power supply to a main load is switched OFF and then ON again within a predetermined time. The main load may be a vehicle reversing light RL, and the auxiliary load may be a piezoelectric audio warning circuit (figure 3), whereby both loads may be controlled by a single gearstick-operated switch. When the switch (not shown) is opened, Q2 turns on and charge transfers from C6 to C7. The charge on C7 then decays through R13, but if the switch is reclosed while the potential on C7 exceeds the Zener diode DZ1 breakdown voltage, then thyristor Q3, which controls the auxiliary load, is turned on.

Description

"Power-on memory circuit" THIS INVENTION relates to a power-on memory circuit.

It is desirable to provide a circuit which provides an output signal indicative of the circuit having been reactivated within a pre-determined period of time since a preceding activation.

The present invention accordingly provides a poweron memory circuit for connection to a power supply comprising: a first charge storage device operable to be charged by the power supply when connected thereto; a first switch means which is in an off condition whilst the power supply is connected to the circuit to prevent current flow through the first switch means and which is biased to an on condition by the first charge storage device whilst the power supply is disconnected from the circuit; a second charge storage device connected to the first switch means and operable to be charged by the voltage discharged from the first storage device whilst the power supply is disconnected from the circuit, the second charge storage device being operable to discharge through a load to a predetermined charge level over a pre-determined time; and a second switch means connected to a discharge path of the second charge storage device which second switch means is biased to an on condition during the pre-determined time, but which is biased to an off condition when the charge of the second charge storage device drops below the predetermined charge level.

In many countries it is a legal requirement that heavy goods vehicles and the like must, in addition to showing a visible reversing light, also emit an audible warning signal when reversing. It is impossible to turn the audible warning signal off without turning off the reversing light as the reversing light and audible warning signal are powered by the same source and are also usually housed in the same unit.

In a further aspect, the present invention provides a power-on memory switch including a power-on memory circuit embodying the present invention, wherein the circuit is connected to a first element to be turned on and off and the power supply is connected to a second element to be turned on and off, wherein the second element is always turned on when the power supply is connected thereto and the first element is only turned on when the first output is provided by the second switch means.

In order that the present invention may be more readily understood, embodiments thereof will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a schematic diagram of a circuit for use with an embodiment of the present invention; Figure 2 shows a schematic diagram of the device of a circuit embodying the present invention comprising the circuit of Figure 1 provided with a latch; and Figure 3 shows a schematic diagram of the circuit of Figure 2 configured as part of circuitry for controlling a reversing bulb unit of a vehicle.

Referring to Figure 1, a resistive load RL is connected across a power supply having two terminals, V+ and V-. A diode D4 is connected in series with a first capacitor C6 in parallel across the load RL. An npn transistor Q2 is connected across the diode D4, a base of the transistor Q2 being connected to the V+ terminal and an emitter of the transistor Q2 being connected to the junction of the diode D4 and the first capacitor C6. A collector of the transistor Q2 is connected to the anode of a further diode D5. A second capacitor C7 is connected in parallel with a resistor the cathode of the further diode D5 and the V- terminal of the power supply.

In use, when the power supply is connected, the first capacitor C6 will be charged to a voltage level near V+ via the diode D4. When the power supply is removed, then diode D4 becomes reversed biased and the junction of the diode D4 and the capacitor C6 is forced to a voltage level of (V+) + (Q2 be), Vb. being the voltage at the emitter-base junction of the transistor Q2. The emitterbase junction of transistor Q2 is now forward biased thereby allowing the conduction of the positive charge from capacitor C6 via diode D5 to the second capacitor C7. The discharge of the first capacitor C6 causes a voltage increment across the second capacitor C7. The charge across the second capacitor C7 then begins to decay at an exponential rate through the resistor R13, giving rise to a decaying output signal on output line OP.

If the power supply is pulsed at an appropriate rate, then the voltage across the second capacitor C7 will accumulate until a maximum level is reached near a voltage level of V+.

If the power supply is removed, then any charge accumulated in the second capacitor C7 is drained via the collector-base junction of transistor Q2 into any other load that may be connected in parallel with the circuit of Figure 1.

Because the energy stored in the first capacitor C6 is the only power actually used to store charge in the second capacitor C7, it is clear that by removing the power from the V+ terminal, all the transferable charge is passed on to the second capacitor C7 and the diode D5 becomes reversed biased and prevents the charge in the second capacitor C7 from being discharged into the load resistor RL via the transistor Q2 collector-base junction.

Thus, whilst the power is disconnected from the circuit shown in Figure 1, the charge left in capacitor C7 and the output signal on the output line OP decays. If the power supply is reconnected again before the charge in the second capacitor C7 is fully decayed, then the resultant charge in the second capacitor C7 will be the charge remaining in the second capacitor C7 plus a step-wise voltage increment produced by the positive charge received from the now recharged first capacitor C6. This will cause a corresponding rise in the output signal on the line OP.

Referring now to Figure 2 which shows a circuit which is identical to the circuit of Figure 1, except that the circuit is effectively provided with a latch. The output signal on output line OP is applied to a Zener diode DZ1 which establishes a threshold value for the output signal as delivered to a sensitive thyristor Q3. The anode of the thyristor Q3 is connected to the V+ terminal and the cathode of the thyristor Q3 is connected in series through a resistor R14 to the V- terminal. The control gate of the thyristor Q3 is connected via the Zener diode DZ1 to the output line. A further diode D7 is connected at the junction of the cathode of the thyristor Q3 and the resistor R14 and comprises the resultant output of the circuit of Figure 2.

In a preferred example, the circuit runs at a nominal 12 volts and the threshold level is set at 4.7 volts, i.e. about half the voltage of terminal V+. This voltage is fed to the gate of the thyristor Q3 which requires a trigger current in the order 0.2 milliamps. The thyristor "on" state hold current is supplied through resistor R14. The values used in this example are chosen to enable the trigger current to be provided without buffering. The RL load shown in Figure 2 is preferably a visual signal producing device such as, for example, a reversing bulb.

The second capacitor C7 is tailored to reduce any bounce produced during switching of the power supply. The configuration of the thyristor Q3 provides a maximum memory time after the power supply has been disconnected by a switch-off. Whilst the thyristor Q3 is in the "on" state, the parasitic diode in the thyristor Q3 and the Zener diode DZ1 are forward biased and thus apply a voltage of nearly V+ to the second capacitor C7. This maximises memory retention after a switch-off. The signal present at the cathode of thyristor Q3 is isolated via the diode D7 and available to a control circuit as an active high signal.

Figure 3 shows the device of Figure 2 incorporated in an application circuit in which the load to be controlled comprises a piezo-electric audio transducer yl.

A load comprising a reversing bulb (not shown) is connected across the power supply.

When the power supply is connected for a short period of time (insufficient to allow the piezo-electric audio transducer Y1 to be driven) and then the power supply is switched off, then the second capacitor C7 is left to discharge through the resistor R13. If the power supply is reconnected before the charge in the second capacitor C7 has decayed below the pre-determined threshold level, then the output of the circuit of Figure 2 will inhibit operation of the piezo-electric audio transducer Y1 but will not inhibit operation of the reversing bulb (not shown) which is on a parallel circuit. Accordingly, in this manner, the piezo-electric audio transducer may be selectively disabled.

Preferably, the means for connecting and disconnecting the power supply to the power-on memory circuit comprises a switch which is actuable by a gear shift lever in a vehicle. This allows the audible warning signal of the reversing light unit to be selectively turned off whilst the reversing light of the unit remains lit.

For normal operation - i.e. to provide power to both the reversing light and the audible warning signal, the power supply is simply connected and left connected by the gear shift lever switch.

The additional circuitry shown in Figure 3 for driving the piezo-electric audio transducer Y1 and the means for sampling the output of the circuit of Figure 2 is a known driving circuit such as that disclosed in International Publication No. WO 93/01069.

Claims (16)

CLAIMS:

1. A power-on memory circuit for connection to a power supply comprising: a first charge storage device operable to be charged by the power supply when connected thereto; a first switch means which is in an off condition whilst the power supply is connected to the circuit to prevent current flow through the first switch means and which is biased to an on condition by the first charge storage device whilst the power supply is disconnected from the circuit; a second charge storage device connected to the first switch means and operable to be charged by the voltage discharged from the first storage device whilst the power supply is disconnected from the circuit, the second charge storage device being operable to discharge through a load to a pre-determined charge level over a predetermined time; and a second switch means connected to a discharge path of the second charge storage device which second switch means is biased to an on condition during the pre-determined time, but which is biased to an off condition when the charge of the second charge storage device drops below the pre-determined charge level, the biassing of the second switch means determining the output of the second switch means.

2. A power-on memory circuit according to Claim 1, wherein reconnection of the power supply to the circuit during the pre-determined time causes the second switch means to produce a first output.

3. A power-on memory circuit according to Claim 2, wherein the first output produced by the second switch means comprises the power supply voltage fed through the second switch means.

4. A power-on memory circuit according to Claim 2 or 3, wherein the first output produced by the second switch means is a logic signal indicative that the power-on memory device has been reconnected to the power supply within the pre-determined time.

5. A power-on memory circuit according to any one of Claims 2 to 4, wherein the second switch means comprises a thyristor, the gate thereof being connected to the second charge storage device, the anode thereof being connected to a terminal of the power supply and the cathode thereof comprising an output line of the circuit for producing the first output.

6. A power-on memory circuit according to any preceding claim, wherein the means to set the predetermined charge level comprises a threshold device.

7. A power-on memory circuit according to Claim 6, wherein the threshold device comprises a Zener diode.

8. A power-on memory circuit according to any preceding claim, wherein the second charge storage device comprises a capacitor and the load is a resistor.

9. A power-on memory circuit according to any preceding claim, wherein the first switch means comprises a transistor.

10. A power-on memory switch including a power-on memory circuit according to any preceding claim, wherein the circuit is connected to a first element to be turned on and off and the power supply is connected to a second element to be turned on and off, wherein the second element is always turned on when the power supply is connected thereto and the first element is only turned on when the first output is provided by the second switch means.

11. A power-on memory switch according to Claim 10, wherein the first element comprises an audible warning signal producing device and the second element comprises a visual signal producing device.

12. A power-on memory switch according to Claim 11, wherein the - audible warning signal producing device comprises a piezo-electric audio transducer and the visual signal producing device comprises a light bulb.

13. A power-on memory switch according to any one of Claims 10 to 12, wherein the means for connecting and disconnecting the power supply to the power-on memory circuit comprises a switch which is actuable by a gear shift lever in a vehicle.

14. A power-on memory circuit substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

15. A power-on memory switch substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

16. Any novel feature or combination of features disclosed herein.