GB2296834A - BiCMOS tri-state buffers - Google Patents

Abstract

Non-inverting or inverting (figure 7) tri-state buffers incorporate protection against negative biasing of the base-emitter junction of the bipolar output pull-up transistor 34. PMOS device 33 isolates the base of the bipolar device 34 from the data input 61 when the Enable input 62 is low, and NMOS device 35 shunts its base-emitter junction. The output pull-down NMOS transistor 72 is disabled by the gate-hunting transistor 69 when the Enable input 62 is low. <IMAGE>

Description

INVERTING AND NON-INVERTING Bi1OS TRI-STATE BUFFER CIRCUITS FIELD OF THE INVENTION The present invention relates to the field of integrated circuits which combine bipolar and compiementary metal-oxide semiconductor (CMOS) devices on the same substrate.

BACKGROUND OF THE INVENTION In recent years, much effort has been directed toward developing digital logic circuits which combine bipolar and CMOS technologies in a single integrated circuit. The combination of bipolar and CMOS technologies is particularly advantageous since the superior aspects of each may be exploited to yield optimal circuit performance.

For example, CMOS circuits have the advantages of extremely low quiescent power consumption, rail to rail output capability, high density, and a very high input impedance. Bipolar logic circuits, on the other hand, are useful in driving large capacitive loads, have fast switching capabilities, and feature better performance over temperature and power supply. These attributes have led to the development of a family of BiCMOS inverting logic circuits which employ bipolar transistors to drive output loads, while utilizing CMOS devices to perform the basic logic functions.

One problem with bipolar devices is that they suffer from a reliability problem when the voltage across the base and emitter junction (VBE) is negative. This reliability problem typically results in creation of base-emitter leakage current that is a function of negative base-emitter stress voltage and stress time. This leakage current degrades the circuit performance of the bipolar transistors. For example, consider the "bare-base" buffer circuit 10 of Figure 1. If input node 11 is initially at high voltage level (e.g. +5V), bipolar transistor 12 will be on, since the base is driven by the input signal and bipolar transistor 12 is connected as an emitter follower. Also, when input node 11 is at a high voltage level, a low voltage level will result at the gate of MOS transistor 15 due to inverter 16.Transistor 15 will thus be turned off, electrically isolating output node 14 from ground vSS Output node 14 will then be at a high voltage level due to the emitter follower operation of bipolar transistor 12 with its collector coupled to the VDD mode. Conversely, when input node 11 switches to a low voltage level, transistor 12 is off, preventing any current flow from VDD node 13 to output node 14. Transistor 15 is on, discharging the voltage at output node 14 to ground. However, input node 11 can go low faster than output node 14 due to the delay through inverter 16 and transistor 15. When this occurs, the base-emitter voltage VBE across bipolar transistor 12 will be negative (i.e. lower on the base side than the emitter side) causing the reliability voltage stress problem discussed above.

Similarly, a bipolar device cannot be used in a signal bus pre-charge circuit due to reliability problems caused by the negative VBE that can develop.

For example, if the circuit 20 of Figure 2 were used as a pre-charge circuit, transistor 22 would charge output node 24 so long as node 21 is at a high voltage state (logical one). This is due to the bipolar emitter follower between input node 21 and output node 24. Once the base is turned off (node 21 at a low voltage state, i.e. logical zero), a negative base-emitter voltage will result due to the remaining charge on output node 24.

What is needed is an integrated circuit combining CMOS and bipolar technologies which does not develop a negative VBE during operation. Such a circuit should be implemented with a minimum device count and should retain the advantages of both bipolar and CMOS technologies discussed above.

Additionally, the circuitry used to protect the base should also be capable of tristating the bipolar device.

SUMMARY OF THE INVENTION According to the present invention there is provided a BiCMoS non-inverting tri-state buffer circuit, as set forth in claim 1 appended hereto.

Also, according to the present invention there is provided a BiCMOS inverting tri-state buffer circuit, as set forth in claim 6 appended hereto.

The circuit described herein is an inverting or non-inverting tri-state buffer where the first input is coupled to a "data" line, and the second input is coupled to an "enable" line. When used as a tri-state buffer, additional circuitry is disclosed which causes the output to float whenever the enable line is low.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an example of a prior art "bare-base circuit.

Figure 2 is an example of a prior art pre-charge device.

Figure 3A shows a circuit used to provide protection against a negative VBE of a bipolar transistor.

Figure 3B shows the improvement of the circuit of Figure 3A.

Figure 4 shows the circuit of Figure 3A when used in a pre-charge circuit.

Figure 5 shows the circuit of Figure 3A when used in a bare-base circuit.

Figure 6 shows a non-inverting tri-state buffer including the circuit of Figure 3A.

Figure 7 shows an inverting tri-state buffer including the circuit of Figure 3A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Embodiments of the present invention are described below, particularly with reference to Figures 6 and 7. However, a description of Figures 3A, 3B, 4 and 5 is provided first to assist a full understanding of the present invention.

Referring to Figure 3A, circuit 30 shows a BiCMos circuit with negative VBE protection. Transistor 33 is a PMOS transistor, transistor 34 is an NPN bipolar transistor, and transistor 35 is an NMOS transistor.

The gates of transistors 33 and 35 are coupled to the control line through node 36. The drain of transistor 33 is coupled to the drain of transistor 35 at node 37.

In addition, the base of transistor 34 is coupled to the drain of transistor 33 at node 37. The emitter of transistor 34 is coupled to node 39. Node 39 is coupled to ground via one or more transistor devices or other circuits.

If input node 31 of Figure 3A is at a high voltage state while control node 32 is at a low voltage state, transistor 33 will be on while transistor 35 is off. This in turn will cause the input high voltage to propagate to the base of bipolar transistor 34 turning it on, creating an emitter follower between nodes 37 and 39.

Node 39 is the output node of the circuit. In this case, the result of input node 31 being high while control node 32 is low is a logical high voltage state at node 39.

If input node 31 is then turned to logical low voltage state while control node 32 maintains the logical low state, node 37 is pulled to within a Vtp voltage of the low voltage on node 31. Note that the Vtp voltage is the threshold voltage of transistor 33 which includes body effect since the source of transistor 33 is below the bulk N-WELL potential of VcC. N-channel transistor 35 is turned off at this time. Therefore, a negative VBE voltage can be developed, but the maximum possible negative VBE is lower than the Vcc voltage by the Vlp drop.

When control node 32 receives a logical high control signal, transistor 33 is turned off and transistor 35 is turned on. At this time, if node 37 registers a logical high voltage, it is discharged through output node 39 via the turned-on transistor 35. Circuit 30 is then disabled receiving any input signal from input node 31. In this situation, node 37 is assured not to be discharged faster than the emitter of transistor 34 since it is now discharged through node 39.

Figure 3B illustrates a circuit 30A which is an improvement of circuit 30 of Figure 3A. In Figure 3B, circuit 30A is identical to circuit 30 of Figure 3A, except a P-channel transistor 35a is coupled in parallel with N-channel transistor 35.

The source of transistor 35a is coupled to node 37 and the drain of transistor 35a is coupled to node 39. The gate of F-channel transistor 35a receives the control signal at node 32 via an inverter 35b. Logically speaking, transistor 35a is turned on and off by the control signal in the same manner as transistor 35.

In an alternative embodiment, N-channel transistor 35 and P-channel transistor 35a can be made of appropriate width to achieve the desired resistance between nodes 39 and 37, when transistors 35 and 35a are meant to be "on." The purpose of providing P-channel transistor 35a in parallel with N-channel transistor 35 is to provide a better discharge path between nodes 37 and 39 when control node 32 receives a logical high control signal to turn transistor 35 on.

Because transistor 35 is an N-channel transistor, it may be turned off even if control node 32 receives the logical high control signal. When node 39 registers a voltage which is above the voltage level of the logical high control signal minus a threshold voltage Vtn of transistor 35, transistor 35 is turned off even if control node 32 registers the logical high control signal. The Vtn voltage is the threshold voltage of an N-channel transistor. When P-channel transistor 35a is coupled in parallel with transistor 35 as shown in Figure 38, the discharge path between nodes 37 and 39 is not broken when node 39 registers a voltage which is higher than the voltage level of the logical high control signal minus the Vtn voltage of transistor 35.When node 39 experiences a voltage which is above the voltage level of the logical high control signal at control node 32 minus the Vtn voltage, transistor 35 is off but transistor 35a is on, which equalizes the voltage level between nodes 37 and 39. By coupling P-channel transistor 35a in parallel with N-channel transistor 35, a CMOS switch is formed and either of or both of transistors 35 and 35a will be turned on depending on the voltage at node 39 when control node 32 register the logical high control signal.

In Figures 4-7, circuit 30 of Figure 3A is shown as part of various circuits, including as part of a pre-charge circuit (Figure 4), as part of a bare-base buffer circuit (Figure 5), as part of a non-inverting tri-state BiCMOS buffer circuit (Figure 6), and as part of an inverting tri-state BiCMOS buffer circuit (Figure 7).

It shall also be noted that circuit 30A of Figure 38 can replace circuit 30 of Figure 3A to be used as part of the circuits shown in Figures 4-7.

Referring to Figure 4, a pre-charge circuit 40 is shown. Circuit 40 includes input node 41 and inverter 42 coupled to input node 41. Input node 41 is coupled to node 31 of circuit 30, while the output of inverter 42 is coupled to node 32 of circuit 30. Output node 43 of circuit 40 is coupled to node 39 of circuit 30 and to the next stage of circuits (not shown). The use of pre-charge circuit 40 includes precharging an SRAM array, for example. The pre-charge circuit 40 can also be used to precharge register file bits. In general, precharge is a mechanism where a node is charged to a high voltage state and conditionally discharged to low or remain high. This saves the transition time it takes to generate a high voltage from a low voltage state.

If input node 41 is taken to a logical high voltage state, the output of inverter 42 will be low. In this case, transistor 33 will be on thus turning transistor 34 on and forming an emitter follower between VDD and output node 43. The low output of inverter 42 will also cause transistor 35 to be off thus isolating the base of transistor 34 from the output. The result will be to charge output node 43.

When input node 41 is taken to a logical low voltage state, the output of inverter 42 will be high, turning transistor 33 off and transistor 35 on. In this case, the base of transistor 34 will be shorted to the output through transistor 35 which is coupled to output node 43 at node 39. The circuit 40 then waits for events to happen in the next stage of the circuit to which output node 43 is coupled to discharge output node 43. Note that unlike transistor 22 of circuit 20 of Figure 2, transistor 34 of Figure 4 cannot develop a negative VBE as input node 41 is switched from high to low due to the isolation of the base from input node 41 provided by transistor 33 and the shorting of the base to the output through transistor 35 when input node 41 switches from high to low.

Figure 5 shows a bare-base circuit 50 which employs circuit 30 of Figure 3A. When input node 51 is taken high, the ouput inverter 52 will be low. Node 31, coupled to node 51, will be high while node 32, coupled to the output of inverter 52, will be low. The operation of the circuit 30 portion of circuit 50 under these circumstances is identical to that described in connection with Figure 3A when node 31 is high and node 32 is low. Note that nodes 31 and 32 cannot be both at the low voltage, the case which causes some level of negative VBE for Figure 3A. Node 39 will be high under these conditions. Output 55 of Figure 5 (coupled to node 39) will then be high when input node 51 is high.Note that under these conditions transistor 54, coupled to inverter 52 at node 53, will be off due to the low from inverter 52 thus isolating node 39 (and, therefore, output 55) from ground Vss. Transistor 54 is preferably an n-type NOS transistor.

When node 51 is taken low, the output of inverter 52 will be high. In this case, node 31 will be low and node 32 high and the operation of the circuit 30 portion of circuit 50 will be identical to that described for these conditions in conjunction with Figure 3A. Transistors 33 and 34 will be off and transistors 35 and 54 will be on. In this case, the output, as well as the base of transistor 34, are discharged to ground Vss through transistor 54. Thus, the base of transistor 34 can never be discharged faster than the output (as is the case for the bare-base circuit of Figure 1) since it is discharged through the output rather than through input node 51. Thus, a negative VBE cannot develop. The circuit 50 of Figure 5 can be used as, for example, a two state non-inverting buffer.

Figure 6 shows a tri-state noninverting buffer circuit 60 which employs circuit 30 of Figure 3A Data node 61 is coupled to input node 31. Data node 61 is also coupled to inverter 64, the output of which is coupled to transistors 65 and 66, which are connected in parallel as a switch as shown in Figure 6. Enable node 62 couples an Enable signal to the gate of transistor 66. Enable node 62 also couples the Enable signal to inverter 63, the output of which is coupled to node 32. The output of inverter 63 is also coupled to node 67, which is further coupled to the gate of transistor 65 through node 68, and to the gate of transistor 69. The output of transistors 65 and 66 are coupled to the gate of transistor 72. In the currently preferred embodiment, transistors 66, 69, and 72 are n-type MOS transistors, and transistor 65 is a p-type MOS transistor.

When enable node 62 is high (i.e., a high Enable signal), transistor 66 is on. The output of inverter 63 is low. As a result of the low at the output of inverter 63, transistor 33 is on, transistor 35 is off, transistor 65 is on, and transistor 69 is off.

Now consider the operation of circuit 60 of Figure 6 while enable node 62 is high. If data node 61 is high, the output of inverter 64 will be low. Since transistors 65 and 66 are on, transistor 72 is off, isolating output node 70 from ground Vss. Also, since transistor 33 is on, transistor 34 is turned on allowing current to flow from node 38 to output node 70 (emitter follower from node 37), resulting in a high voltage state at output node 70.

With enable node 62 still high, if data node 61 is low, node 37 is pulled down to Vtp from the ground V5S. This causes node 37 to gradually discharge the high voltage through the drain to substrate current flowing through transistor 33. Also, while data node 61 is low, the output of inverter 64 will be high thus turning transistor 72 on (since transistors 65 and 66 are on) and thereby quickly discharging output node 70 to ground VSS through transistor 72.

Thus, while enable node 62 is at a high State, output 70 will be at a high state when data node 61 is high, and at a low state when data node 61 is low (i.e. when enable = 1, output node 70 = data).

When enable node 62 is low, the output of inverter 63 will be high.

Transistors 65 and 66 will be off while transistor 69 will be on. Since transistor 69 is connected to ground, node 71 will be low whenever enable node 62 is low thus turning off transistor 72 thereby isolating output node 70 from ground.

Additionally, due to the high output of inverter 63, transistor 33 will be off, isolating transistor 34 from data node 61. Transistor 35 will be on, coupling the base of transistor 34 to output node 70 through transistor 35. Thus, when enable node 62 is low, output node 70 is floating.

Therefore, when enable node 62 is high, output node 70 equals data, and when enable node 62 is low, output node 70 is floating.

Figure 7 shows tri-state inverting buffer circuit 80. Circuit 80 is similar to circuit 60 of Figure 6 except that inverter 84 is placed between the data node 81 and input node 31 of circuit 30, and there is no inverter between data node 81 and the parallel transistors 85 and 86. The operation of the enable circuitry is the same in circuit 80 as in circuit 60 of Figure 6. Whenever enable node 82 is high, output node 90 will be at the same level as the output from inverter 84.

Thus, output 90 will be the inverted signal of the data node 81 whenever enable node 82 is high. Whenever enable node 82 is low, output node 90 will float.

Thus, when enable equals 1, out equals inverted data, and when enable equals 0, output node 90 is floating.

The present application is a divisional of GB9312217.4 (GB2270598) entitled "BiCMOS circuit with negative VBE protection".

Claims (12)

1. A BiCMOS non-inverting tri-state buffer circuit comprising: a) a bipolar transistor having a base, a collector coupled to a power supply, and an emitter coupled to an output of said circuit; b) a first transistor having a gate coupled to a first input via a first inverter, a drain coupled to said output node, and a source coupled to ground; c) a second transistor having a gate coupled to a second input via a second inverter, a drain coupled to said gate of said first transistor, and a source coupled to ground; d) means including a third transistor having a drain coupled to said base of said bipolar transistor, a source coupled to said output node, and a gate coupled to said second input via said second inverter for coupling said base of said bipolar transistor to said output node when said second input is in a first voltage state;; e) a fourth transistor having a drain coupled to said base of said bipolar transistor, a source coupled to said first input, and a gate coupled to said gate of said third transistor, wherein said second input is in said first voltage state, said third transistor couples said base of said bipolar transistor to said output node, wherein when said first input is in said first voltage state and said second input is in said second voltage state, said base of said bipolar transistor assumes a voltage equal to said first voltage state plus a threshold voltage of said fourth transistor at which said fourth transistor is turned off.

2. The circuit of claim 1, wherein said first, second, and third transistors are N-channel MOS transistors and said fourth transistor is a P-channel MOS transistor.

3. The circuit of claim 2, wherein said coupling means further comprises a fifth transistor coupled in parallel with said third transistor, wherein said fifth transistor has a gate coupled to said second input, wherein said fifth transistor is a P-channel MOS transistor.

4. The circuit of claim 1, wherein said first voltage state is a logical low voltage and said second voltage state is a logical high voltage.

5. The circuit of claim 2, wherein said first input is a data input and said second input is a control input.

6. A BiCMOS inverting tri-state buffer circuit, comprising: a) a bipolar transistor having a base, a collector coupled to a power supply, and an emitter coupled to an output of the circuit; b) a first transistor having a gate coupled to a first input, a drain coupled to said output node, and a source coupled to ground; c) a second transistor having a gate coupled to a second input via a first inverter, a drain coupled to said gate of said first transistor, and a source coupled to ground; d) means having a third transistor having a drain coupled to said base of said bipolar transistor, a source coupled to said output node, and a gate coupled to said second input via said first inverter for coupling said base of said bipolar transistor to said output node when said second input is in a first voltage state;; e) a fourth transistor having a drain coupled to said base of said bipolar transistor, a source coupled to said first input via a second inverter, and a gate coupled to said gate of said third transistor, wherein when said second input is in said first voltage state, said third transistor couples said base of said bipolar transistor to said output node, wherein when said first input is in a second voltage state and said second input is in said second voltage state, said base of said bipolar transistor assumes a voltage equal to said first voltage state plus a threshold voltage of said fourth transistor at which said fourth transistor is turned off.

7. The circuit of claim 6, wherein said first, second, and third transistors are N-channel MOS transistors and said fourth transistor is a P-channel MOS transistor.

8. The circuit of claim 6, wherein said first voltage state is a logical low voltage and said second voltage state is a logical high voltage.

9. The circuit of claim 6, wherein said first input is a data input and said second input is a control input.

10. The circuit of claim 7, wherein said coupling means further comprises a fifth transistor coupled in parallel with said third transistor, wherein said fifth transistor has a gate coupled to said second input, wherein said fifth transistor is a P-channel MOS transistor.

11. A BiCMoS non-inverting tri-state buffer circuit, substantially as hereinbefore described with reference to Fig. 6 of the accompanying drawings.

12. A BiCMOS inverting tri-state buffer circuit, substantially as hereinbefore described with reference to Fig. 7 of the accompanying drawings.