GB2295527A

GB2295527A - Rake combiner/despreader apparatus

Info

Publication number: GB2295527A
Application number: GB9423935A
Authority: GB
Inventors: Anthony Peter Hulbert
Original assignee: Roke Manor Research Ltd
Current assignee: Roke Manor Research Ltd
Priority date: 1994-11-26
Filing date: 1994-11-26
Publication date: 1996-05-29
Anticipated expiration: 2014-11-26
Also published as: GB2295527B; GB9423935D0

Abstract

The Rake combiner/despreader apparatus comprises a shift register 2 for receiving channel estimates. The channel estimates are stored temporarily in two register banks 24, 22 which respectively store the real channel estimates and the imaginary channel estimates. The output of the register banks are applied to a respective adder/subtractor circuit 18, 26 and the respective channel estimates are included in the addition/subtraction under the control of control circuits 16 which compare the bit reference from the shift register to the output of a modulo N counter 4. The output of the counter 4 represents an index for the received bit corresponding to the position of the chip specified in a real or imaginary chip sequence which is applied to the shift register 2. The outputs from the respective adder/subtractor circuits 18, 26 are passed through a respective combiner circuit 28, 30 which combines the output with the real or imaginary channel samples respectively. The output of the combiner circuits 28, 30 are added together in an adder 32. An accumulator is provided for each bit position, and the output from the adder 32 is applied to an input of the particular accumulator 14, by a switch 38. The inputs to the accumulator 14 is formed by the output of the adder circuit 32 in combination with the selected output from the accumulator 14. The output of the accumulator 14 is selected by switch 36. When the last sample which can influence a particular bit has been processed, the contents of the accumulator 14 are read out and fed to subsequent circuitry for appropriate processing. <IMAGE>

Description

RAKE COMBINER/DESPREADER APPARATUS The present invention is concerned with a Rake combiner/despreader apparatus for the demodulation of direct sequence spread spectrum (DSSS) signals in a multipath environment using so called Rake technology.

The Comprehensive Rake Receiver as described in pending patent application number 9316489.5 involves sampling the filtered complex baseband signal at one chip intervals and creating a digital matched filter to the channel (Rake filter) in which all of the multipath components are combined in a maximal ratio sense. The signal is also despread. In the prior art there are two approaches to this problem. The traditional approach despreads the individual multipath components, then scales them according to the path levels and then adds them together. The pre-combining approach as described in co-pending patent application number 9213535.9 weights and combines the multipath components at the chip level prior to despreading them.

The traditional approach is useful where there is only a small number of Rake fingers and where only one spread spectrum code, transmitted over the common path, needs to be demodulated.

The pre-combining approach is useful where many signals need to be demodulated. It is, however, rather complicated.

An aim of the present invention is to provide a combiner/despreading apparatus which allows many Rake fingers to be combined but has modest complexity. Typically the multiplication rate is the same as for the traditional approach but the multiplication is by the samples on one port (which are typically only four bits precision), leading to a lower complexity multiplier.

According to the present invention there is provided a Rake combiner/despreader apparatus, for use in a spread spectrum system, the apparatus comprising means for obtaining channel estimates, storage means for holding said channel estimates, controlling means for controlling the passage of data from the storage means to calculation means arranged to add or subtract said channel estimates and generate an output signal which is applied to combining means arranged to combine said output signal with a channel sample.

According to an aspect of the invention the storage means comprises a first register bank for receiving real channel estimates and a second register bank for receiving imaginary channel estimates.

According to a further aspect of the invention the controlling means comprises a store holding a current part of a spread spectrum chip sequence derived from a local generator and references to bits which are currently being despread, and a plurality of control circuits each connected to a respective chip position of said store, so that, for each chip position the control circuit connected thereto performs a comparison between the bit reference and all current bit references, and if equality is found the corresponding stored channel estimate is passed to said calculation means.

According to yet a further aspect of the invention the value of the corresponding stored chip determines whether the relevant channel estimate is added or subtracted in the calculation means.

An embodiment of the invention will now be described with reference to the accompanying drawings wherein: Figure 1 shows a block diagram of a combiner/despreader apparatus, and, Figure 2 shows an example of a control circuit shown in Figure 1.

The combiner/despreader circuit shown in Figure 1 comprises a shift register 2 connected to receive a reference clock from a modulo N counter 4. A real chip sequence signal is generated by a generator 44 and duplicates the transmitted real chip sequence signal, and is received at a further input 6 of the shift register. A respective bit of the shift register 2 is connected to an input of a control circuit 16 respectively, which receives at a further input thereof, an output signal from a second modulo N counter 12. An output from each of the control circuits 16 is connected to an input of a register bank 22 and an input of a register bank 24. The register bank 22 handles imaginary channel estimates and the register bank 24 handles real channel estimates. The real and imaginary channel estimates are generated from channel estimators 40, 42 respectively.The real channel estimates are applied to an add/subtract tree circuit 18, and the imaginary channel estimates are applied to an add/subtract tree circuit 26. A master clock circuit 8 drives the modulo N counter 12 and the modulo N counter 4. The output of the master clock circuit 8 is passed to a divide by N circuit 10 and is further divided by a divide by H circuit 20 prior to application to the module N counter 4. The divide by H circuit represents the spreading factor. The output from each add/subtract tree circuit 18, 26 is connected to an input of a combiner circuit 28 ,30 respectively. The combiner circuit 28 combines the output of the add/subtract tree circuit 18 with the real channel samples, and the combiner circuit 30 combines the output of the add/subtract tree circuit 26 with the imaginary channel samples.The output generated from each of the combiner circuits 28, 30 is applied to an adder circuit 32, the output of which is applied to an input of a further adder circuit 34. N accumulators, 14 one for each bit currently being processed have a switch 36 connected to the output of each accumulator and a switch 38 connected to the input of each accumulator. The switch 36 selects which bit is to be connected to the adder circuit 34, the output of which is connected back to the switch 38 and is fed back to an input of a particular bit position in the accumulator 14. The switches 36, 38 are controlled by the output of the modulo N counter 12.

The operation of Figure 1 will now be described in conjunction with Figure 2 which shows an example of one of the control circuits 16.

The fundamental principle is to take the incoming complex baseband samples and determine their contribution (by despreading and by channel matched filtering) to every bit that they may be derived from. Each received sample comprises noise and interference plus components derived from several transmitted chips, each subjected to a path delay. Thus, suppose the sampled response throught the transmitter pulse shaping filter, channel and receiver filter for a radio link can be described as:

and suppose that the chip sequence is:

If the spreading factor is H then the bit sequence can be set as:

Where br is the rth transmitted bit. This is a set H identical impulses, bipolar modulated with data, at the chip rate for every bit.Thus the actual transmitted sequence is then:

Then the received sequence of samples is:

Thus, the signal component in the nth sample can be written as:

where the subscript, v = #n - i# H Thus, if the nth received sample is Y(n), a matched filtering operation can be performed for every sample by forming Y(n).S*(n). In fact, because of the modulation, various S(n) must be formed over summation values for which v is constant.

Thus vO = FHl gives the sample's contribution to the matched filter accumulation for the newest bit bvo This is obtained as

where âi is an estimate of aj.

The contribution to the previous bit bX,l is given by:

And to the bit before, by

and so on....

The last contribution ends when i reaches L-1. Thus the maximum number of bits which can contribute to one sample is N =1+ FHH.

The maximum significant delay span for assumed for the channel, Lmax chips must be determined. Then for a given spreading factor, H, the number of bits, N to be handled in parallel can be determined.

The complexity of the receiver will depend upon the form of spreading and on the basic modulation. The simplest form is real-only spreading - ie q;=0 for all k. The simplest form of modulation is BPSK in which only the real part of Y(n) .S*(n) need be calculated.

One implementation for the case of real-only spreading and BPSK modulation based on these principles is shown in Figure 1.

It is assumed that channel estimates have already been derived over the delay spread of the signal (either using a pilot signal or from the data signal through decision direction).

The process is half complex, therefore much of the hardware is repeated and shown symmetrically. For simplicity, only the left hand side (the real part) will be described. Essentially, the circuit operates for each sample (taken at the chip rate) to accumulate, sequentially, chip contributions for each of the pertinent N transmitted bits. Thus the master clock rate is N/Tc.

The shift register 2 is several bits wide. It will be appreciated that a further shift register would need to be provided for the Q imaginary channel which would receive the imaginary chip sequence in the case of quaternary phase shift keying (QPSK) spreading. These bits are arranged to consist of two components: One bit corresponding to the appropriate real chip, and Llog7NJ bits, together forming an index for the received bit corresponding to the position of the chip specified in the bit corresponding to the appropriate real chip. These latter bits are provided by the modulo N counter 4 which is driven from a divide by H circuit 20 (the spreading factor) from the chip sample clock, generated from the master clock 8 and divided by N in circuit 10.

The modulo N counter 12 from the master clock 8 and the divide by N circuit 10 cycles through the reference numbers for all output bits (in this case three). Its output, in turn, therefore makes connections to the inputs and outputs of the relevant M bit accumulator circuit 14. Additionally, the output of counter 12 is applied to the control circuits 16, the operation of which is shown in Figure 2.

The control circuit detects when a given chip corresponds to the bit which is currently active by comparing in a comparator 50, the bit reference from the shift register 2 with the output of the modulo N counter 12 and causes the "Include" line to be activated so that corresponding channel estimates will be included in the summation. It also passes the Chip value from the shift register circuit. This will have the effect of either passing the relevant channel estimate to the adder/subtractor tree circuit 18, 20 or of 2's complementing it first (for subtraction).

Thus, the control lines pass into the registers holding the real channel estimates and control their output in to the adder/subtractor tree circuit. This produces, in turn the summations of equations 1, 2, 3 etc. The matched filtering operation is then performed taking the real and imaginary complex samples, and multiplying and adding them. The values are then summed into the appropriate M bit accumulator 14.

When the last sample which can influence a particular bit has been processed, the contents of the bit accumulator are read out and fed to subsequent circuitry for appropriate processing (eg decisions, de-interleaving, soft error correction decoding) according to the original operations applied prior to modulation in the transmitter. After the accumulator output is read out, it is reset to zero and assigned to the next bit in the sequence.

It will be appreciated that if the spreading is complex, most of the hardware will need to be duplicated to recover the bit energy from the Qchannel signal component. Moreover, if the modulation is complex, further duplication will be needed to recover the complex decision variable.

Claims

1. A Rake combiner/despreader apparatus, for use in a spread spectrum system, the apparatus comprising means for obtaining channel estimates, storage means for holding said channel estimates, controlling means for controlling the passage of data from the storage means to calculation means arranged to add or subtract said channel estimates and generate an output signal which is applied to combining means arranged to combine said output signal with a channel sample.

2. Apparatus as claimed in Claim 1, wherein the storage means comprises a first register bank for receiving real channel estimates and a second register bank for receiving imaginary channel estimates.

3. Apparatus as claimed in Claim 1 or Claim 2, wherein said controlling means comprises a store holding a current part of a spread spectrum chip sequence derived from a local generator and references to bits which are currently being despread, and a plurality of control circuits each connected to a respective chip position of said store, so that, for each chip position the control circuit connected thereto performs a comparison between the bit reference and all current bit references, and if equality is found the corresponding stored channel estimate is passed to said calculation means.

4. Apparatus as claimed in Claim 3, wherein the value of the corresponding stored chip determines whether the relevant channel estimate is added or subtracted in the calculation means.

5. Apparatus as claimed in Claim 3 or Claim 4 wherein said store is a shift register.

6. Apparatus as claimed in any of the preceding Claims 3,4 or S wherein said store is connected to a first modulo counting means driven by a clock generator via a divider circuit representing a spreading factor, said modulo counting means providing an index for each received bit corresponding to the position of an appropriate real chip.

7. Apparatus as claimed in any preceding Claim, wherein the calculation means comprises first and second add/subtract tree circuits, an output of each being respectively connected to a combiner means arranged to combine the output of the calculation means with the channel sample.

8. Apparatus is claimed in Claim 7, wherein an output of each combiner means is applied to a first adder and accumulated on a bit by bit basis in an accumulator.

9. Apparatus as claimed in Claim 8, wherein the input to the accumulator comprises a combined signal generated from a second adder which receives at a first input, an output from said first adder, and at a second input, a selected output from said accumulator.

10. Apparatus as claimed in Claim 9 wherein the input to the accumulator is to a selected bit position.

11. Apparatus as claimed in Claim 10, wherein the input and output selection to/from the accumulator is controlled by switching means controlled by an output of a second modulo counting means driven via a master clock.

12. Apparatus as claimed in any preceding claim which utilises binary phase shift keying modulation.

13. Apparatus as claimed in any of the preceding Claims 1 to 11 which utilises quaternary phase shift keying modulation.

14. Apparatus substantially as herein before described with reference to the accompanying drawings.