GB2294807B - Self-registered capacitor bottom plate local interconnect scheme for dram - Google Patents

Self-registered capacitor bottom plate local interconnect scheme for dram

Info

Publication number
GB2294807B
GB2294807B GB9422069A GB9422069A GB2294807B GB 2294807 B GB2294807 B GB 2294807B GB 9422069 A GB9422069 A GB 9422069A GB 9422069 A GB9422069 A GB 9422069A GB 2294807 B GB2294807 B GB 2294807B
Authority
GB
United Kingdom
Prior art keywords
layer
polysilicon
capacitor electrode
lower capacitor
dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9422069A
Other versions
GB2294807A (en
GB9422069D0 (en
Inventor
Min-Liang Chen
Nan-Hsiung Tsai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosel Vitelic Inc
Original Assignee
Mosel Vitelic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosel Vitelic Inc filed Critical Mosel Vitelic Inc
Priority to GB9422069A priority Critical patent/GB2294807B/en
Publication of GB9422069D0 publication Critical patent/GB9422069D0/en
Publication of GB2294807A publication Critical patent/GB2294807A/en
Application granted granted Critical
Publication of GB2294807B publication Critical patent/GB2294807B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Semiconductor Memories (AREA)

Abstract

A method and structure for a lower capacitor electrode (67) for a dynamic random access integrated (DRAM) circuit (50). A polysilicon gate layer (64) is formed over a thin layer of oxide (63) in a first region of a semiconductor substrate (49). Another oxide layer (62) is then formed overlying the polysilicon gate layer (64). A polysilicon layer (121) which was doped by S/D implant and includes the lower capacitor electrode (131) self-aligns and forms overlying a second region of the semiconductor substrate (100) and over the oxide layer (108) on the polysilicon gate layer (110). A nitride layer (127) forms on the lower capacitor electrode (131) portion overlying the second region. Exposed portions (132) of the polysilicon layer (121) are then oxidized. The S/D (114, 116) was formed by driving dopant from implanted second layer polysilicon (121). Portions of polysilicon (121) under the nitride layer (127) corresponding to the lower capacitor electrode (131) oxidizes at a slower rate than the exposed portions (132) of the polysilicon (121) giving rise to a birds beak structure. Such sequence of steps forms a self-aligned lower capacitor electrode (67) for a DRAM (50). <IMAGE>
GB9422069A 1994-11-02 1994-11-02 Self-registered capacitor bottom plate local interconnect scheme for dram Expired - Fee Related GB2294807B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9422069A GB2294807B (en) 1994-11-02 1994-11-02 Self-registered capacitor bottom plate local interconnect scheme for dram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9422069A GB2294807B (en) 1994-11-02 1994-11-02 Self-registered capacitor bottom plate local interconnect scheme for dram

Publications (3)

Publication Number Publication Date
GB9422069D0 GB9422069D0 (en) 1994-12-21
GB2294807A GB2294807A (en) 1996-05-08
GB2294807B true GB2294807B (en) 1998-10-21

Family

ID=10763756

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9422069A Expired - Fee Related GB2294807B (en) 1994-11-02 1994-11-02 Self-registered capacitor bottom plate local interconnect scheme for dram

Country Status (1)

Country Link
GB (1) GB2294807B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0258657A1 (en) * 1986-08-22 1988-03-09 Siemens Aktiengesellschaft Varactor-transistor device for dynamic semiconductor memory
US5272103A (en) * 1991-02-08 1993-12-21 Mitsubishi Denki Kabushiki Kaisha DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0258657A1 (en) * 1986-08-22 1988-03-09 Siemens Aktiengesellschaft Varactor-transistor device for dynamic semiconductor memory
US5272103A (en) * 1991-02-08 1993-12-21 Mitsubishi Denki Kabushiki Kaisha DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof

Also Published As

Publication number Publication date
GB2294807A (en) 1996-05-08
GB9422069D0 (en) 1994-12-21

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20091102