GB2293254A - Emulator for debugging embedded software for almost any microprocessor - Google Patents

Abstract

A Universal emulator has a dual port emulation memory which can be connected to any microprocessor target board system via a standard memory socket and to a programmable computer via an interface circuit. The interface circuit contains breakpoint control logic (Fig 3) with an interrupt output signal which can be connected to the interrupt line of the microprocessor target board. An interrupt driven debug routine which can be executed by the target microprocessor allows the status of the microprocessor's registers etc to be viewed on the programmable computer display. The programmable computer is also able to control the operation of the target microprocessor via the breakpoint control logic and a Universal Step/Animate control circuit, USAM. The emulator can be configured for many different microprocessors by personality files supplied on disc, containing information about microprocessor register architecture. <IMAGE>

Description

A NEW, FAST METHOD OF DEBUGGING EMBEDDED SOFTWARE FOR ALMOST ANY MICROPROCESSOR....EASY-I.C.E.

Their are two traditional methods for debugging embedded software: 1. The low cost and slow method of using a target monitor program. Your program is downloaded via the serial port of the P.C. to target RAM. A limited selection of monitor commands are normally available, such as Go, Single Step, Dis-assemble etc. The monitors themselves may consume anything from 2-32k bytes of user code space and require an RS232 port on your target system. Most target monitor based systems are for developing assembler only programs and cannot cope with 'C' 2. The expensive method of using I.C.E. where the microprocessor is replaced by an In-Circuit Emulator. The user is given comprehensive Source Level Debugging Capabilities (Assembler or 'C') for a given microprocessor. Changing your microprocessor requires either a change of pod or the purchase of a complete new I.C.E.

In this invention, we want to present a new method for debugging embedded software which overcomes the limitations of method 1, whilst providing most of the benefits of method 2 without being tied to a single microprocessor family.

The use of memory emulation for downloading and running programs is widely established and used. The EASY-I.C.E. memory emulator can also be used in this way, there exists though a need to provide more sophisticated debugging whereby the status of the microprocessor can be examined at a breakpoint. I.C.E. provides additional program control facilities such as single stepping the program or continuing from a breakpoint. The purpose of this invention is to explain a new low cost method of providing similar features to I.C.E., using the Interrupt pin of the users micropocessor, a breakpoint control circuit, a very small additional debug program that runs on the users target system and a memory emulator connected to a Personal Computer via a plug-in card. The P.C. also runs a program to control the complete emulator system.

Finally, this invention also seeks to introduce a new type of breakpoint called "Firmware Breakpoint" which offers a low cost way of debugging the users programs.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made by way of example, to the accompanying drawings, in which: Fig 1 is an overview of connecting EASY-I.C.E. to an example target system Fig 2 provides flowchart and target system connection example for Firmware Breakpoint Fig 3 shows the breakpoint control circuit for EASY-I.C.E.

Fig 4 shows the pulse input/output waveforms for Fig 3 Fig 5 is a flowchart of a Debug Routine invoked by the breakpoint control circuit Fig 6 shows the circuit diagram of a Universal Step/Animate Module Fig 7 is a screen example of the P.C. software showing target control modes Fig 8 is an example assembler listing of the Debug Routine (Fig 5) Fig 9 is a circuit schematic of the EASY-I.C.E. emulator Fig 10 is a circuit schematic of the PC Card containing the breakpoint control circuit EASY-I.C.E. is described as a Universal Development System because it can be configured for many different microprocessors via MicroWatch personality files supplied on disc.The personality files contain information about the internal register architecture of a microprocessor (see FIG 8 example) plus information as to where each register variable is stored with respect to a base offset start address of the Microwatch Data. The Microwatch Data can be mapped to any spare block of memory within the EASY-I.C.E. emulator to allow the target status to be viewed at a breakpoint. The EASY-I.C.E. memory emulator requires connection via JEDEC memory socket(s) rather than the microprocessor socket, so some single chip microprocessors may require internal memory to be expanded out and lost I/O ports reproduced.

The invention also includes details of a Universal Step/Animate Module (USAM) which has been designed as part of the EASY-I.C.E. M.D.S. The USAM allows the programmer to single step and animate through a program. It is not required if you only want to pause and observe, or run and 'snapshot' the target status at a breakpoint. The USAM is a stand-alone module, but designers of low volume boards, microprocessor trainer boards or those containing a monitor may want to build this circuitry into their new board designs, Fig 1 shows it as part of a target board design.

The EASY-I.C.E. system has been designed to use the absolute minimum of target resources.

With reference to FIG 1, EASY-I.C.E. requires the use of a used or spare highest priority maskable interrupt pin, a non maskable interrupt cannot be used. A spare input bit (C) may be required, if you have no spare maskable interrupts available or the level status of the interrupt port (A) cannot be read under software control. The USAM can be triggered by a spare or used output bit (B) e.g. an l.e.d. port bit. The l.e.d. can be used because the trigger pulse will not affect the visual status of the l.e.d. to the naked eye. For single pod systems, the debug routine should be stored either in the microprocessor or in external code memory such as an EPROM. For dual pod systems (emulating code and data) , the debug can be stored in the emulator.For 16 bit microprocessors, dual pods (2 x code) are required and the debug must be stored in external EPROM or SAAR memory.

The INT P5 Probe generates an active positive or negative interrupt signal when a breakpoint is triggered. A breakpoint can either be triggered from an optional Turbo-Trace unit (not shown) which has a built-in hardware address comparator circuit (established method) using the address lines from the EASY-I.C.E. emulator. Alternatively a Firmware Breakpoint signal can be generated from the users target system (FIG 2) to trigger a breakpoint latch on the PC Card Breakpoint Control Circuit (Fig 3).

with reference to Fig 3, the breakpoint trigger output signal should be a spare output pin if using a "Call Breakpoint Subroutine" method. Alternatively, the breakpoint trigger could be attached to any output port bit generating a suitable edge without the need for "Calling A Breakpoint Subroutine" The Firmware breakpoint option has one slight drawback, when the breakpoint triggers, an interrupt will be generated causing the processor to enter the debug routine. The breakpoint triggers when X goes from low to high, which means the debug routine will display the status of the registers within the Breakpoint Subroutine. The user will then have to step through the Return From Subroutine before being able to view the true status of registers immediately following the "Call Breakpoint" instruction.It is therefore advantageous to avoid using registers if possible within the Breakpoint Subroutine when generating the breakpoint trigger pulse.

The Breakpoint Control Circuit Fig 3, provides the means for controlling the status of the INT P5 OUTPUT PROBE. The three input signals on the left: RESET TRIGGER, P5 INT CONTROL, BREAKPOINT ENABLE are under the control of software running on the P.C. The circuit is mounted on a plug-in ISA card that plugs into the backplane of the P.C. Fig 10. The circuit though could be controlled via the serial/parrallel port of the P.C. with suitable additional components. The 74HC109 provides a means of latching the status of the breakpoint trigger input signal, to cause the (Q) Breakpoint Trigger Status to change from low to high. The Trigger Status is monitored by the P.C. software if Breakpoints are enabled to provide visual indication to the user on the V.D.U. that a breakpoint trigger has occured.At this point the P.C. will take control of the INT P5 OUT line by setting P5 INT CONTROL=1, it will reset the 74HC109 latch so that the circuit can be re-triggered. With INT P5 OUT active the users target system will enter the debug routine and wait at the "END CONDITION" After a pre-set delay the P.C. will read the copy of the microprocessor status from the emulator memory and display these details on the V.D.U. It also automatically presents the user with the following mouse selectable Target Control Options Fig 7: SINGLE STEP ANIMATE CONTINUE SNAPSHOT RUN FOREVER Animate is Single Step automatically repeating, Snapshot is Continue automatically repeating.

When the user selects one ofthese options the P.C. program will produce a pulse output on INT PS OUT as shown in Fig 4.

EASY-I.C.E. works in conjunction with a background debug assembler routine Fig 8 which can be supplied for various microprocessors. The background debugger is typically 100-150 bytes for each microprocessor making it one of the smallest debuggers in the world. In Fig 5, we outline in block diagram form how the debugger works.

The background debugger is only invoked when the EASY-I.C.E. system is connected to your target system It is non-intrusive on real-time program run and for this reason it can be left in production boards. The debugger is activated when a breakpoint is hit causing an interrupt to be generated via the PS probe. If you use a WIRED-OR interrupt (A), then the status of "P5 INVERSE" must be read-in via a spare input pin to determine the source of the interrupt. If the interrupt port status (A) cannot be read under software control then "P5 INVERSE" connection is required to control the exit from debug. The debugger can be divided into two sections, the first pan copies all tlle microprocessor information out to a spare block of emulator memory. You can pass parameters to the debug routine via EASY-I.C.E. to say what section of internal RAM you want to view, you can also customise the debug for displaying external port I/O etc. The second part copies all the microprocessor information back and provides the USAM trigger pulse. In between these two sections is the "END CONDITION" which monitors the status of the "P5 INVERSE" probe (if connected) or the "INT P5 OUTPUT". These probes are under the control ofthe software running on the P.C., the pulse output determines whether you SINGLE STEP, ANIMATE, CONTINUE or SNAPSHOT your program. The main benefit of this method is SPEED, for example you can animate through your assembler code at over 80 instructions per second.In SNAPSHOT mode your program runs in real-time except when it passes through the breakpoint. You also have a very convenient way of modifying any variable on-the-fly. The important thing to notice about this debug routine is that NO software commands are sent by the host computer, it is controlled by pure logic, that is why it is the smallest, fastest and easiest to understand debugger in the world.

Finally we turn to the USAM circuit Fig 6, which is required for almost all microprocessors except the 8031 series which has a built-in single step facility on the interrupt port. On the 8031 series if the interrupt is still active on executing a 'Return From Interrupt' (RTI) instruction the microprocessor will automatically return to the main program and execute a single instruction before entering the interrupt routine again. By pulsing the interrupt line you can single step your program. For other microprocessors an active interrupt on an 'RTI' instruction will cause the microprocessor to immediately re-enter the interrupt again without returning to the main program.

To single step the microprocessor, the interrupt must be made in-active for a short period whilst the 'RTI' instruction is executed. This is the function of the USAM. The EXT TRIG INPUT starts the time delay (td) determined by the Cl, R4, R1 network, the width ofthe output pulse (tp) is determined by the C2 R5/R6 network. ICI is a 74HC221 Dual Monostable Multivibrator, the C/R network time delay is equal to C * R.

If the time for your microprocessor to go from the trigger pulse instruction to completing the 'RTI' is (x) uSecs, then single stepping will work if: (x) - (tp) < time delay (td) < (x) + (tp) The pulse output width (tp) can be altered by SWI (default open), to allow single stepping to operate for most microprocessor with clock rates from approx 1 Mhz upwards depending on instruction execution time. The two exclusive Or gates allow the circuit to be used for either active low or active high interrupts The OR gate is used to inhibit the effect of false external triggers that may occur outside of the debug routine and also for allowing the P5 output to follow the PS input when pin 5 IC1 is low. The circuit can be simplified ifyou only require active low interrupts by removing the exclusive Or gates and SW6 from the circuit, leaving a two chip solution one 74HC221 1 and one NOR gate.

In Fig 7 we show a screen dump of the PC software when a breakpoint has triggered showing the standard Target Control Nodes, plus two new ones: Xstep - Allows 'C' code to be single stepped or Step Over Library Calls StepTo - Operates with source view tracker bar (Step to selected line) Fig 9 shows a circuit schematic of the EASY-I.C.E. emulator which can be connected to the PC Card circuit shown in Fig 10.

Claims (9)

1. A Universal emulator comprising of (a) a dual port read/write emulation memory with connection means via one port to a memory socket of a microprocessor target system board, connection means via another port to a programmable computer with read means to emulation memory to allow the display of emulation memory on the programmable computers display, (b) a breakpoint control circuit comprising of a breakpoint trigger signal input means which when triggered causes a breakpoint triggered interrupt output signal to go active which can be connected directly or indirectly to an interrupt pin of a target system microprocessor, a breakpoint trigger status signal output means to a programmable computer to indicate when a breakpoint has occured.
2. 2 A Universal emulator as claimed in Claim 1 wherein an interrupt driven background debug routine which is executed by a target system microprocessor (interrupts must be enabled) after the breakpoint triggered interrupt output signal goes active, causes microprocessor/target status (e.g. registers, SFR's, memory etc) to be copied out to emulation memory, the programmable computer after a suitable delay initiated for example by the breakpoint trigger status signal output means, reads the emulation memory containing a copy ofthe microprocessor/target status and displays the same information on the programmable computers display.
3. 3 A Universal emulator as claimed in Claim 1 wherein the breakpoint trigger signal input means for example is derived from and connected to a target system output bit that toggles from one logic level state to another in response to program instructions executed by a target system microprocessor.
4. 4 A Universal emulator as claimed in Claim 1 wherein the breakpoint control circuit includes an interrupt control input signal means to provide overide control of the level status of the breakpoint triggered interrupt output signal to provide for example a manual interrupt break facility from the programmable computer.
5. 5 A Universal emulator as claimed in Claim 1 wherein the breakpoint control circuit includes a breakpoint trigger enable/disable means to inhibit operation of the breakpoint triggered interrupt output signal from going active even if the breakpoint trigger signal input means is triggered.
6. 6 A Universal emulator as claimed in Claim 1 and Claim 2 wherein an interrupt driven background debug routine includes one or more instructions to read the level status of a programmable computer controllable output signal means (e.g. the breakpoint triggered interrupt output signal or its inverse) via a signal input means on the microprocessor target system board to allow the programmable computer to control when and how the target system microprocessor exits from the debug routine and to allow operation of Wired-Or interrupts.
7. 7 A Universal emulator as claimed in Claim 1 and Claim 2 and Claim 6 wherein the background debug routine includes instructions to copy back some or all of the thus allowing the microprocessor/target status to be modified before returning from the background debug routine.
8. 8 A Universal emulator as claimed in Claim 1 and Claim 2 and Claim 6 wherein a pulse injection circuit (U.S.A.M.) is inserted between the interrupt output signal of the breakpoint control circuit and the interrupt pin of the target microprocessor and includes an external trigger signal input means for initiating the start of the pulse injection process to cause the interrupt pin of the target microprocessor to go inactive for a short period when the return from interrupt instruction is being executed in the debug routine thereby causing the processor to single step through a program running on the target system.
9. 9 A Universal emulator substantially as described herein with reference to Figures 1-10 of the accompanying drawings.