GB2292470A - Rom patching - Google Patents
Rom patching Download PDFInfo
- Publication number
- GB2292470A GB2292470A GB9416815A GB9416815A GB2292470A GB 2292470 A GB2292470 A GB 2292470A GB 9416815 A GB9416815 A GB 9416815A GB 9416815 A GB9416815 A GB 9416815A GB 2292470 A GB2292470 A GB 2292470A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory
- program instructions
- patch
- read
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/66—Updates of program code stored in read-only memory [ROM]
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Debugging And Monitoring (AREA)
- Stored Programmes (AREA)
Abstract
A data processing system having a central processor unit core 8 operating under control of program instructions stored within a read only memory 10 may be subject to mistakes within the program instructions. In order to deal with this, patch program instructions are stored within a patch memory 6. A breakpoint detector 14 monitors the address bus to the read only memory 10 and detects when an access is made to an address known to contain a mistake. Upon such an access, an interrupt handler 16 serves to divert processing to the patch stored within the patch memory 6 by writing a new value into a program counter register 12 coupled to the central processor unit core 8. At the end of the patch, control is returned to the program instructions of the read only memory 10. <IMAGE>
Description
ROM PATCHING
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems having a central processor unit core controlled by program instructions stored within a read only memory (ROM).
It is known to provide data processing systems including a central processor unit core controlled by program instructions stored within a ROM. Such arrangements are becoming increasingly common and are often used within mass-market electronic devices incorporating embedded microprocessor controllers.
A constant problem with the use of program instructions to control central processor unit cores is the presence of mistakes (bugs) within the program instructions. Whilst considerable efforts are taken to thoroughly test program instructions, some -mistakes inevitably tend to be overlooked and are only discovered at a later date. In order to deal with such mistakes that are recognised at a late stage, it is known to correct such mistakes with so called "patches". If the mistake is small, then it may be possible to directly replace the erroneous program instructions within a sequence of corrected instructions. Alternatively, the mistake may be such that the required solution is to insert a sub-routine call into the original instruction flow, so that the new sub-routine can perform the necessary corrections to the operation.
Whilst such approaches are possible when the program instructions are stored in a manner in which they may be altered, this is not a possibility when the program instructions are stored in ROM. If a ROM contains mistakes, then it must be replaced, since there is no mechanism for altering the program instructions stored by the ROM.
Whilst this is inconvenient in itself, the problem becomes even more severe when the ROM forms part of a larger, more expensive integrated circuit where several functional elements are formed as a single integrated circuit. The waste involved in replacing such sophisticated integrated circuits is even greater.
Whilst one approach might be to avoid the use of ROMs, this would cause its own problems. ROMs are an efficient, inexpensive and robust way of storing program instructions that would be disadvantageous to give up.
Viewed from one aspect this invention provides apparatus for processing data comprising:
a central processor unit core controlled by program instructions, each program instruction having an associated instruction address;
a read only memory for storing program instructions;
a further memory for storing patch program instructions;
an address bus for transmitting instruction addresses from said central processor unit core to said read only memory;
a breakpoint detector coupled to said address bus for detecting on said address bus a predetermined instruction address within said read only memory and thereupon generating a breakpoint interrupt signal;;
an interrupt handler responsive to said breakpoint interrupt signal for passing control of said central processor unit core to a sequence of patch program instructions stored within said further memory to effect a program patch over one or more program instructions stored in said read only memory and then returning control of said central processor unit core to a return program instruction stored within said read only memory following said one or more program instructions.
The invention provides a mechanism whereby the advantages of the use of a ROM may be achieved whilst the problems of program instruction mistakes may be readily overcome. The system is provided with a further memory, which need only be small, for handling any patch program instructions that later become necessary as mistakes within the program instructions of the ROM are discovered. When such mistakes are discovered, the breakpoint detector and the interrupt handler can be programmed to prevent the mistakes being executed and instead divert control to the patch program instructions within the further memory.
The return program instruction need not be special in any way, it is simply the next instruction to be executed after the patch. The return program instruction may typically be positioned after the bug to be fixed, but could also be at any point within the program stored within the ROM or at a point in another program not stored in the ROM.
It will be appreciated that whilst the invention is particularly suited to correcting mistakes within program instructions, it may also be used to provide a degree of flexibility in modifying/updating the program instructions for reasons that do not stem from a coding mistake; in this case the patch program instructions are actually updated code.
Whilst the further memory could take many different forms, such as a further small read only memory or a set of registers, it is preferred that said further memory comprises a random access memory.
Such random access memory is often already provided within such systems to provide other functions, such as working memory for dynamic data storage.
As previously discussed, it is possible with large scale integration techniques to incorporate more than one functional element upon a single integrated circuit. Accordingly, it would be possible to fabricate the further memory as part of the system containing the central processor unit core and ROM. However, it yields an advantageous degree of flexibility when said further memory comprises a discrete integrated circuit.
As previously mentioned, the invention is particularly suited to embodiments in which said central processor unit core, said read only memory, said breakpoint detector and said interrupt handler are formed within a single integrated circuit.
With regard to the interrupt handler, this may be implemented as a hardware circuit element. Alternatively, the interrupt handler could be implemented as a software routine executing on the central processor unit core, e.g. an interrupt handler routine may be started that diverts to the appropriate patch in dependence upon the value in the program counter register at the time of the interrupt, or such interrupt handler software could in another way determine which patch should be used in dependence upon the state of the system.
In order that the breakpoint detector and the interrupt handler can efficiently serve to divert processing control to the patch program instructions, in preferred embodiments said breakpoint detector stores said predetermined address.
In a complementary manner said interrupt handler stores an associated start address of said patch program instructions within said further memory.
Whilst the system could provide the capability for a single patch, it is preferred that multiple patches can be supported by providing that said breakpoint detector and said interrupt handler store a plurality of said predetermined addresses and a plurality of said associated start addresses.
In preferred embodiments of the invention said central processor unit core comprises a program counter register storing an address of a current program instruction to control said central processor unit core and wherein said interrupt handler responds to said breakpoint interrupt signal by writing an associated start address of said patch program instructions into said program counter register.
The interrupt handler may, in accordance with the above, readily force a jump to the patch program instructions by writing a new program counter value.
At the end of a sequence of patch program instructions, it is preferred that the patch itself returns control to the main program instructions within the read only memory by writing a return address into the program counter register.
Viewed from another aspect this invention provides a method of processing data comprising the steps of:
storing program instructions within a read only memory;
controlling a central processor unit core by program instructions, each program instruction having an associated instruction address;
storing patch program instructions within a further memory;
transmitting instruction addresses from said central processor unit core to said read only memory via an address bus;
detecting on said address bus a predetermined instruction address within said read only memory and thereupon generating a breakpoint interrupt signal; ;
in response to said breakpoint interrupt signal, passing control of said central processor unit core to a sequence of patch program instructions stored within said further memory to effect a program patch over one or more program instructions stored in said read only memory and then returning control of said central processor unit core to a return program instruction stored within said read only memory following said one or more program instructions.
An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:
Figure 1 illustrates a data processing system having a central processor unit core operating under control of program instructions stored within a ROM; and
Figure 2 illustrates the flow of control when a patch is utilised to skip a mistake within a main sequence of program instructions.
Figure 1 illustrates an integrated circuit 2 comprising a plurality of functional units. The integrated circuit 2 has a central bus 4 (including an address bus) via which signals are passed inside the integrated circuit 2 and to an external further memory in the form of a patch memory 6.
The integrated circuit 2 incorporates a central processor unit core 8 responsive to program instructions and a ROM 10 storing such program instructions. The central processor unit core 8 is controlled by whichever program instruction is stored at the address indicated by the current value held by a program counter register 12.
A breakpoint detector 14 is coupled to the bus 4 and continuously monitors the address bits of the currently accessed address within the
ROM 10 to detect the occurrence of the predetermined breakpoint address. An interrupt handler 16 stores a plurality of such breakpoint addresses (BPAdd) and corresponding patch addresses (PAdd). When the break point detector 14 detects one of its stored breakpoint addresses, it issues a breakpoint interrupt signal (BPIS) to the interrupt handler 16 that triggers the patch address corresponding to the detected breakpoint address to be written into the program counter register 12 via a line 18. The values of the break point addresses (BPAdd) and patch addresses (PAdd) may be stored within a volatile memory and loaded into the interrupt handler 16 via the bus 4 upon initialisation.
Another possibility is that the breakpoint addresses (BPAdd) and patch addresses (PAdd) could be serially loaded via a JTAG type serial interface to the integrated circuit.
In Figure 1 the breakpoint addresses (BPAdd) and patch addresses (PAdd) are shown as store within the interrupt handler. As an alternative the breakpoint addresses (BPAdd) could be stored in the breakpoint detector 14 from where they are readily available for high speed use on every cycle to compare with the address value being supplied to the ROM 10. In contrast, since the patch addresses (PAdd) are only infrequently needed, they could be stored elsewhere (e.g. in the patch memory 6) from where the can be recovered when needed.
Figure 2 illustrates the operation of the circuit of Figure 1.
A sequence of program instructions 20 are stored within the ROM 10.
These program instructions control the operation of the central processor unit core 8 as it sequentially steps through these instructions. As this operation progresses, the value of the program counter value stored within the program counter register 12 increments as illustrated by the sequence of address values 22.
Within the program instructions stored in the read only memory 10, erroneous program instructions (XXXXXXX) are stored at three addresses (Add N, Add N+1 and Add N+2). As an attempt is made to control the central processor unit core 8 upon the basis of the first of these instructions at address N, the breakpoint detector 14 recognises this as one of its predetermined addresses and issues a breakpoint interrupt signal (BPIS). This breakpoint interrupt signal forces the interrupt handler to write a new value into the program counter register 12, in this case, the program counter value is changed from N to Z.
The address Z points to a location in the patch memory 6 which contains an appropriate correcting set of code for the mistake starting at address N. By writing the address Z into the program counter register 12, control is passed to the patch program instructions and these execute in sequence until the end of the patch. The last instructions in the patch at address Z+3 is a return instruction that serves to write a return address value into the program counter register 12 for returning control to the program instructions of the
ROM 10. In this case, the program instructions return control to the instruction of address N+3, whereupon the sequence of execution of the program instructions of the ROM 10 is recommenced.
Whilst in the illustration of Figure 2 the patch contains the same number of program instructions as the error it fixes, this need not necessarily be the case, e.g. the patch may be a lengthy subroutine that in some way upgrades the performance of the integrated circuit 2 rather than correcting an error in the program codes stored within the read only memory 10. In addition, the patch is illustrated as sequentially executing in Figure 2; this need not necessarily be the case. The patch may contain jumps and sub routine calls just as any normal piece of code.
Claims (13)
1. Apparatus for processing data comprising:
a central processor unit core controlled by program instructions, each program instruction having an associated instruction address;
a read only memory for storing program instructions;
a further memory for storing patch program instructions;
an address bus for transmitting instruction addresses from said central processor unit core to said read only memory;
a breakpoint detector coupled to said address bus for detecting on said address bus a predetermined instruction address within said read only memory and thereupon generating a breakpoint interrupt signal;;
an interrupt handler responsive to said breakpoint interrupt signal for passing control of said central processor unit core to a sequence of patch program instructions stored within said further memory to effect a program patch over one or more program instructions stored in said read only memory and then returning control of said central processor unit core to a return program instruction.
2. Apparatus as claimed in claim 1, wherein said return program instruction is stored within said read only memory following said one or more program instructions.
3. Apparatus as claimed in any one of claims 1 and 2, wherein said further memory comprises a random access memory.
4. Apparatus as claimed in any one of claims 1, 2 and 3, wherein said further memory comprises a discrete integrated circuit.
5. Apparatus as claimed in any one of the preceding claims, wherein said central processor unit core, said read only memory, said breakpoint detector and said interrupt handler are formed within a single integrated circuit.
6. Apparatus as claimed in any one of the preceding claims, wherein said breakpoint detector stores said predetermined address.
7. Apparatus as claimed in any one of the preceding claims, wherein said interrupt handler stores an associated start address of said patch program instructions within said further memory.
8. Apparatus as claimed in claims 6 and 7, wherein said breakpoint detector and said interrupt handler store a plurality of said predetermined addresses and a plurality of said associated start addresses.
9. Apparatus as claimed in any one of the preceding claims, wherein said central processor unit core comprises a program counter register storing an address of a current program instruction to control said central processor unit core and wherein said interrupt handler responds to said breakpoint interrupt signal by writing an associated start address of said patch program instructions into said program counter register.
10. Apparatus as claimed in claim 9, wherein a last instruction within a sequence of patch program instructions writes into said program counter register a return address for said return program instruction stored within said read only memory.
11. A method of processing data comprising the steps of:
storing program instructions within a read only memory;
controlling a central processor unit core by program instructions, each program instruction having an associated instruction address;
storing patch program instructions within a further memory;
transmitting instruction addresses from said central processor unit core to said read only memory via an address bus;
detecting on said address bus a predetermined instruction address within said read only memory and thereupon generating a breakpoint interrupt signal; ;
in response to said breakpoint interrupt signal, passing control of said central processor unit core to a sequence of patch program instructions stored within said further memory to effect a program patch over one or more program instructions stored in said read only memory and then returning control of said central processor unit core to a return program instruction.
12. Apparatus for processing data substantially as hereinbefore described with reference to the accompanying drawings.
13. A method of processing data substantially as hereinbefore described with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9416815A GB2292470A (en) | 1994-08-19 | 1994-08-19 | Rom patching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9416815A GB2292470A (en) | 1994-08-19 | 1994-08-19 | Rom patching |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9416815D0 GB9416815D0 (en) | 1994-10-12 |
| GB2292470A true GB2292470A (en) | 1996-02-21 |
Family
ID=10760114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9416815A Withdrawn GB2292470A (en) | 1994-08-19 | 1994-08-19 | Rom patching |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2292470A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2309324A (en) * | 1996-01-17 | 1997-07-23 | Motorola Inc | Method for storing repair data in a microprocessor |
| GB2330428A (en) * | 1997-09-23 | 1999-04-21 | Winbond Electronics Corp | ROM program patching in an embedded microprocessor |
| US6463549B1 (en) * | 2000-09-28 | 2002-10-08 | Motorola, Inc. | Device and method for patching code residing on a read only memory module utilizing a random access memory for storing a set of fields, each field indicating validity of content of a group, and for receiving an address of a memory portion of the read only memory |
| DE19781620B4 (en) * | 1996-02-28 | 2005-09-08 | Intel Corporation, Santa Clara | Bus patcher |
| US7302605B2 (en) | 2003-10-23 | 2007-11-27 | International Business Machines Corporation | Method and structure for replacing faulty operating code contained in a ROM for a processor |
| EP1983429A1 (en) | 2007-04-19 | 2008-10-22 | Proton World International N.V. | Implementation of corrective programs by a processing unit |
| WO2016007027A1 (en) * | 2014-07-10 | 2016-01-14 | Intel Corporation | Method and apparatus for updating a shader program based on current state |
| EP4012554A4 (en) * | 2020-01-17 | 2022-12-21 | Shenzhen Goodix Technology Co., Ltd. | Chip patching method and chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1346219A (en) * | 1970-10-16 | 1974-02-06 | Honeywell Bull Sa | Memory arrangements for digital electronic computers |
| GB2122780A (en) * | 1982-04-26 | 1984-01-18 | Sharp Kk | Program modification system |
| EP0428005A2 (en) * | 1989-10-30 | 1991-05-22 | Kabushiki Kaisha Toshiba | Microcontroller with non-volatile memory error repair |
| GB2245397A (en) * | 1990-05-24 | 1992-01-02 | Schlumberger Ind Ltd | Programme patching in mask-programmable microprocessors |
| GB2250838A (en) * | 1990-12-11 | 1992-06-17 | Honda Motor Co Ltd | Patching a program stored in ROM |
| EP0553733A2 (en) * | 1992-01-24 | 1993-08-04 | Sony Corporation | Electronic apparatus and method for patching a fixed information |
-
1994
- 1994-08-19 GB GB9416815A patent/GB2292470A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1346219A (en) * | 1970-10-16 | 1974-02-06 | Honeywell Bull Sa | Memory arrangements for digital electronic computers |
| GB2122780A (en) * | 1982-04-26 | 1984-01-18 | Sharp Kk | Program modification system |
| EP0428005A2 (en) * | 1989-10-30 | 1991-05-22 | Kabushiki Kaisha Toshiba | Microcontroller with non-volatile memory error repair |
| GB2245397A (en) * | 1990-05-24 | 1992-01-02 | Schlumberger Ind Ltd | Programme patching in mask-programmable microprocessors |
| GB2250838A (en) * | 1990-12-11 | 1992-06-17 | Honda Motor Co Ltd | Patching a program stored in ROM |
| EP0553733A2 (en) * | 1992-01-24 | 1993-08-04 | Sony Corporation | Electronic apparatus and method for patching a fixed information |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2309324A (en) * | 1996-01-17 | 1997-07-23 | Motorola Inc | Method for storing repair data in a microprocessor |
| GB2309324B (en) * | 1996-01-17 | 2000-09-06 | Motorola Inc | Method for storing repair data in a micro processor system |
| DE19781620B4 (en) * | 1996-02-28 | 2005-09-08 | Intel Corporation, Santa Clara | Bus patcher |
| GB2330428A (en) * | 1997-09-23 | 1999-04-21 | Winbond Electronics Corp | ROM program patching in an embedded microprocessor |
| GB2330428B (en) * | 1997-09-23 | 2000-05-24 | Winbond Electronics Corp | Apparatus for repairing faulty program segments in embedded microprocessor systems |
| US6463549B1 (en) * | 2000-09-28 | 2002-10-08 | Motorola, Inc. | Device and method for patching code residing on a read only memory module utilizing a random access memory for storing a set of fields, each field indicating validity of content of a group, and for receiving an address of a memory portion of the read only memory |
| US7302605B2 (en) | 2003-10-23 | 2007-11-27 | International Business Machines Corporation | Method and structure for replacing faulty operating code contained in a ROM for a processor |
| EP1983429A1 (en) | 2007-04-19 | 2008-10-22 | Proton World International N.V. | Implementation of corrective programs by a processing unit |
| WO2016007027A1 (en) * | 2014-07-10 | 2016-01-14 | Intel Corporation | Method and apparatus for updating a shader program based on current state |
| EP4012554A4 (en) * | 2020-01-17 | 2022-12-21 | Shenzhen Goodix Technology Co., Ltd. | Chip patching method and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9416815D0 (en) | 1994-10-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |