GB2291992A - Method of producing memory modules using partial memory circuits - Google Patents

Abstract

A method of producing a memory module such as Single In-line Memory Modules using partial memory circuits by routing the working planes in the memory circuits to the edge connector of the SIMM and leaving the defective planes unconnected. The routing being accomplished during the fabrication stage of the SIMM so that no memory management means or control means are required to ensure perfect operation of the SIMM. Switching arrangement 46 connects working planes of DRAM circuit 42 to an edge connector 32. Short circuit connections may be provided by a resistor, a conductive strip or a removable jumper. The DRAM's 42 may be tested and sorted before they used on the SIMM circuit board. Special printed circuits could be then used with appropriate connections made for memory circuits with two specified defective planes. <IMAGE>

Description

Method of Producing SIMMs using Partial Memory Circuits This invention relates to the field of memory modules for use in computer systems.

The present invention relates to a method of producing Single In-line Memory Modules from partial memory circuits without needing any control apparatus to ensure that the module works correctly.

The present invention is applicable in particular, though not exciusively, to Single In-line Memory Modules.

With the increase in processing power of modern personal computers there has also been an increase in complexity of the software used on these personal computers. This has given rise to a huge demand for memory modules called SIMMs (Single In-line Memory Modules).

SIMMs are made from a number of DRAM (Dynamic Random Access Memory) integrated circuits. In a DRAM fabrication process wafers of silicon containing a large number of DRAM circuits are processed in batches. Once all of the process stages are complete the DRAM circuits are tested and scribed into individual circuits. The DRAM circuits which are perfect or which can be made to work perfectly are packaged and sold. Those circuits which contain one or more faulty cells, even after any on-chip redundancy techniques have been applied, may be parametrically or functionally graded, and if suitable sold as partially working chips. These partially working chips may contain a number of different errors. To understand these errors it is necessary to consider the physical structure of a DRAM circuit.

Conventionally, DRAMs are organised in planes, with each plane consisting of row and column drivers and memory cells. For exarnple, a four bit wide 1 6Mbit memory die comprises four planes of 2048 rows by 2048 columns, or 4096 rows by 1024 columns. When an address is received by the four bit chip, one bit is read from the appropriate row and column of each plane, thus giving four data bits.

Some partially working chips have perfect row and column drivers but contain single bit errors in the memory array, whereas other partially working memory chips have faulty row and/or column drivers and/or single bit errors.

A number of memory replacement techniques have been proposed. Some of these techniques are based on individual cell replacement, some are based on replacement of defective row and column drivers, others are based on replacement of entire planes.

If memory chips with random faulty cells (rather than just defective row and column drivers) are to be used in a memory replacement system then there are a number of possible ways of substituting for the faulty rows and columns. Most of these ways require some type of control mechanism (often in the form of additional control circuitry) to identify which cells need replacing and to substitute for them on demand. If rows and columns are being replaced then control circuitry is also needed. The present invention, however, relies on replacement of entire bit planes and so can avoid using additional control circuitry. The present invention does not use substitute storage means to replace faulty planes in a partial DRAM, it merely uses the good planes in a DRAM and ignores the defective planes.

One advantage of the present invention is that it enables SIMMs to be produced cheaply and efficiently from partial memory circuits.

Another advantage of the present invention is that it enables SIMMs to be produced without requiring any customised control circuitry to manage the bit replacement.

A further advantage of the present invention is that it enables SIMMs to be manufactured which use partial memory circuits with a very large number of individual errors.

It is an object of the present invention to provide a method of producing a perfect working SIMM from partial DRAM circuits.

The substance of the invention is the use of a customised printed circuit board with a plurality of partial DRAM circuits for every perfect DRAM circuit that is required. The number of DRAM circuits required to emulate one perfect DRAM circuit is determined by the number of faulty planes in the partial DRAM circuits that are used. If DRAM circuits with three faulty planes are used then four partial DRAM circuits are needed. If DRAM circuits with two faulty planes are used then only two partial DRAM circuits are required. Four working bit planes are needed to emulate a working four bit plane DRAM.

For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example, to the accompanying drawings in which: Figure 1 shows part of a standard SIMM; and, Figure 2 shows a SIMM based on the present invention. For clarity, only one four bit DRAM circuit (having two defective planes) is shown.

Figure 1 shows part of a standard SIMM 10. It shows a standard four bit DRAM circuit 12 having twelve address lines 14 which are connected to a system address bus 16. A typical SIMM might have eight or nine such DRAM circuits. The system address bus 16 connects to every DRAM circuit 12 on the SIMM 10. The twelve address lines 14 are multiplexed to provide a row and column address. The DRAM circuit 12 has standard power 18, ground 20 and control lines 22. The DRAM has four input/output lines 24, 26, 28 and 30, one for each data plane in the DRAM circuit 12. There is one bit on each plane corresponding to each address on the address bus 16. Thus for any given row and column address combination there are four bits accessed in the DRAM circuit 12. These data bits are sent to and received from the edge connector 32 on the SIMM 10.The edge connector 32 has four edge fingers 34 per DRAM circuit 12.

Figure 2 shows a partial SIMM 40 based on the present invention. The partial SIMM 40 is populated with four bit DRAM circuits 42. Each four bit DRAM circuit 42 is identical to the DRAM circuit 12 shown in Figure 1 except that the DRAM circuit 42 of Figure 2 has two defective data planes, whereas the DRAM circuit 12 of Figure 1 is a perfect DRAM circuit.

This means that two of the data planes cannot be used for storing data.

Thus, the partial SIMM 40 based on the present invention contains twice as many DRAM circuits 42 as the standard SIMM 10 of Figure 1. Standard SIMMs typically use eight or nine DRAM circuits (although smaller SIMMs are available which use only two or three DRAM circuits). To create a perfectly working SIMM from partial DRAM circuits with only two planes working per partial DRAM would require sixteen or eighteen partial DRAM circuits per SIMM.

The edge connector 32 on a partial SIMM 40 populated with devices such as the partial DRAM circuit 42 of Figure 2 only uses two edge fingers 34 per chip because only two data planes actually work, however, there will be twice as many chips so the total number of edge fingers 34 on the edge connector 32 is the same as for the edge connector on a standard SIMM.

This must be the case otherwise the partial SIMM 40 and the standard SIMM 10 would not be compatible.

This embodiment assumes that there are only two working data planes in each four bit DRAM circuit. However, the modifications required to allow the use of DRAM circuits with three working data planes or only one working data plane would be immediately apparent to one skilled in this particular art.

The partial DRAM circuit 42 has four input/output (hereinafter referred to as I/O) lines 24, 26, 28, and 30. In the standard SIMM 10 these I/O lines go directly to the standard edge connector 32; however, in the partial SIMM 40 these four I/O lines go to a switching arrangement 46. The switching arrangement 46 is used to select which data planes will be routed from the partial DRAM circuit 42 to the edge connector 32. The switching arrangement 46 can be considered as two blocks, one block 48 routes one data plane to a first edge finger 34A on the edge connector 32, the other block 50 routes one data plane to a second edge finger 34B on the edge connector 32.

The first block 48 has three inputs coming from three of the I/O lines 26, 28 and 30 in this embodiment of the invention, and a common output 52. There is an open circuit between these three inputs and the common output 52 of the first block 48. The common output 52 of the first block 48 goes to the first edge finger 34A on the edge connector 32.

The second block 50 has three inputs coming from three of the I/O lines 24, 26, and 28 in this embodiment of the invention, and a common output 54. There is an open circuit between these three inputs and the common output 54 of the second block 50. The common output 54 of the second block 50 goes to the second edge finger 34B on the edge connector 32.

It is not important which three of the four I/O lines 24, 26, 28, and 30 go to the first block 48.

The important point is that the one I/O line which did not go to the first block 48 must go to the second block 50 along with any other two of the I/O lines that went to the first block 48. It is important that three of the I/O lines go to each block to ensure that each block can be routed to one working plane. If one block could not be routed to one working plane then one of the edge fingers 34 on the edge connector 32 would be unconnected, with the result that the partial SIMM 40 would not work.

Once the partial SIMM 40 has been populated with partial DRAM circuits 42 the next stage in the process is to connect the working data planes to the edge connector 32. This connection is made by short circuiting one of the three input lines of each block to the common output of each block. This has the effect of connecting one data plane to one of the edge fingers on the edge connector. The other two input lines of each block are left as open circuit paths. For example, in Figure 2 a short circuit may be placed between I/O line 30 and the common output 52 of the first block 48. This would route line 30 to edge finger 34A. A short circuit may be placed between I/O line 28 and the common output 54 of the second block 54. This would route line 28 to edge finger 34B.The partial SIMM would then be tested to determine whether or not data could be written to and read from the two planes in the partial DRAM 42 represented by I/O lines 28 and 30. If data can be correctly written to and read from both planes then the short circuits are in the correct position so no change of position is needed. If neither plane can be written to and read from correctly then both planes are defective and the short circuits must be removed from I/O lines 28 and 30 and placed in lines 24 and 26. The system would then work correctly.If one plane could be written to and read from correctly (for example the plane connected to line 30) but one plane could not be written to and read from correctly (for example the plane connected to line 28) then the short circuit must be removed from the line that did not work (line 28) and placed in one of the other two possible working lines (either line 24 or 26). Assume that the short circuit was placed in line 24. If the plane still could not be written to and read from then the short circuit would be removed form line 24 and placed in line 26. Thus a maximum of two changes to the short circuit path are required to produce connections to two working planes.

The short circuit arrangement described could be achieved in a number of ways, for example a resistor could be inserted to act as a short circuit, a conducting strip could be used, or a removable "jumper" common in personal computer cards could be used.

In other embodiments of this invention the partial DRAM circuits 42 are tested and sorted according to which of the planes are defective before they are used to populate the partial SIMM 40. For four bit DRAM circuits with two defective planes the circuits would be sorted into six useful sets (there may also be other sets, for example for useless circuits, and perfect circuits). These six sets would be for the following defective planes: one and two, one and three, one and four, two and three, two and four, and finally three and four. Thus, the short circuit links can be placed in the correct position immediately (because they have already been sorted into sets which have the same planes defective), without the need for the trial and error process indicated above.

In yet another embodiment of this invention the partial DRAM circuits 42 are tested and sorted before they are used to populate the partial SIMM 40, as described above. However, instead of placing the partial DRAM circuits 42 onto the circuit board shown in Figure 2 which has space for short circuiting the appropriate connection, a special printed circuit board is used.

The special printed circuit board has the appropriate connection built-in because it is designed to be used with circuits with two specific defective planes (for example planes one and three).

Six different printed circuit boards would be needed, one for each possible faulty plane permutation.

It will be appreciated that various modifications may be made to the above described embodiments within the scope of the present invention.

Claims (5)

Claims

1. A method of producing a computer memory module using memory circuits containing one or more defective planes by routing only working planes in the said memory circuits to an edge connector of the said computer memory module and leaving the said defective planes unconnected, the routing means being extemal to the said memory circuits and permanent so that no additional control or management circuitry is required.

2. A method of producing a computer memory module according to claim 1, wherein the memory module is a Single In-line Memory Module (SIMM).

3. A method of producing a computer memory module according to any preceding claim wherein the memory circuits are tested prior to assembly onto the said computer memory module and sorted according to which of the planes in each said memory circuit are defective.

4. A method of producing a computer memory module according to claim 3, wherein the said sorted circuits are assembled onto computer memory modules which are specifically designed to be used in conjunction with the said sorted circuits,

5. A method of producing a computer memory module according to any preceding claim wherein the routing is accomplished by short circuiting a previously open circuit link.