GB2291716A

GB2291716A - Early detection of cell failures

Info

Publication number: GB2291716A
Application number: GB9508488A
Authority: GB
Inventors: Alexander Roger Deas
Original assignee: Memory Corp PLC
Current assignee: Memory Corp PLC
Priority date: 1995-04-26
Filing date: 1995-04-26
Publication date: 1996-01-31
Also published as: GB9508488D0; WO1996034395A1

Abstract

A method of detecting cell irregularities in a cell array by determining whether the drain current required to read from or write to a cell differs from the drain current required to read from or write to other cells in a cell array. If the current required for a cell array differs from that required for one of the cells in the array then the cell is marked as irregular. <IMAGE>

Description

Early Detection of Cell Failures The invention relates to the field of testing semiconductor memory devices.

The present invention is applicable in particular, though not exclusively to memory systems that use test procedures for detecting faulty cells and cells liable to become faulty in memory devices. One particular application for which the present invention is ideally suited is for use with partial DRAM (dynamic random access memory) cell arrays. Partial DRAM circuits are DRAM circuits that contain a number of faulty row drivers column drivers or memory cells. Usually, the proportion of faulty cells is very small compared with the cells that work perfectly.

When partial memory circuits are used in applications requiring a perfect memory then it is imperative that all of the defects within the partial memory cell are discovered. This presents a problem because not all faults are manifest using functional tests particularly under normal operating conditions. Sometimes a cell may work correctly under normal conditions but when the device is being stressed in some way, for example due to high operating temperatures or temperature cycling, a fault may develop. Thus, if a partial memory circuit is tested under normal conditions then some latent defects may not be disclosed by the test. Previously, exhaustive tests have been employed in an attempt to find all of the defective cells, but a total fault coverage has not been attainable.However, the present invention provides a method of locating defective cells and cells that are liable to becoming defective. The present invention provides for early detection of cell failures by measurement and analysis of the peak drain current to supplement traditional functional testing.

The advantages of the present invention include the ability to predict which cells in an array may become defective. This ability of locating potentially bad cells, even before they become defective, has the effect of greatly reducing the cost of testing partial memory circuits. and therefore the cost of using partial memory circuits as replacements for perfect memory circuits. One disadvantage of some test regimes is that they require a substrate bias to be applied for the test to proceed. A further advantage of the present invention is that it can also be used to test memory circuits that have been assembled and packaged into parts.

Thus the invention provides a method of detecting cell irregularities in a cell array by determining whether the drain current required to read or write to a particular cell differs from the drain current required to read or write to other cells in a cell array. The invention also provides a method of detecting cell irregularities in a cell array, where the drain current is compared with the average drain current required to read or write to a cell in the array.

For a better understanding of the present invention and to show how the same may be carried into effect reference will now be made by way of example to the accompanying drawings in which: Figure 1 shows a diagram of a typical row address control line (row address strobe. RAS) and the current flowing in the drain of a typical transistor (cell) of a DRAM circuit in response to the switching of the row address control line (RAS); and Figure 2 shows a circuit for measuring the peak current through a DRAM cell.

Figure 1 shows the effect of the RAS line going active (low). When the RAS line goes low there is a short delay (typically of the order of 100 nanoseconds) before the drain current rises sharply to I, then falls back to its quiescent level. This drain current rise is associated with the charge amplifiers in the DRAM cells receiving charge from the DRAM cells.

When the RAS line goes inactive (high) there is another short delay (typically of the order of 50 nanoseconds) before the drain current rises sharply again then falls back to its quiescent level. The second sharp rise in the drain current (the rise occurring when the RAS line goes inactive) to 12 is associated with the charge amplifiers writing their contents to the cells to be charged; that is the write back" stage. Usually the second peak is lower than the first peak.

The test algorithm adopted in this embodiment of the present invention proceeds as follows. An entire circuit (or a large portion of the circuit) is written to logic level one (high). When RAS goes active then the peak value of in is measured and stored. When RAS goes inactive the peak value of 12 is measured and stored. These values represent the average values of II and 12 for all (or many) of the cells in the circuit. These values are then used as the control values; that is the values with which all subsequent measurements will be compared.

The next stage is to test each cell individually. The same procedure for testing individual cells is adopted as was used for testing the whole array. When RAS goes active I, is measured, when RAS goes inactive 12 is measured. The values of I, and I2 for the individual cell are compared with the values for the entire circuit. If there is a large difference between the values measured for the whole circuit and the values for an individual cell then this suggests that the individual cell differs from the normal cells and so may be liable to failure under stress or after a certain length of time. The magnitude of the difference needed before an individual cell is declared faulty may vary from chip to chip or it may vary depending on how catastrophic cell failure would prove in a particular application.

Figure 2 shows one possible circuit for measuring the peak values of11 and I,. Resistor R1 is a series resistor which is used to provide a voltage measurement when current flows to the DRAM cells. As current flows a capacitor C1 charges until the current flow reaches a peak. The capacitor C1 then discharges at a rate governed by the time constant of the system in this case the product of R2 and C1. A differential amplifier is used to measure the voltage across the plates of the capacitor. The output of the differential amplifier represents the peak value of the current flowing, in effect it produces a dc output. It is envisaged that in some embodiments of the present invention the peak value would be obtained by averaging over a number of write cycles. This would produce a periodic voltage across R1, which would have the effect of generating a sawtooth-like voltage waveform across the capacitor. The output of the differential amplifier would then represent the average value over a number of write cycles.

It will be appreciated that various modifications may be made to the above described embodiment within the scope of the present invention. For example when the control (or average) value of in is being determined then individual rows or columns could be used instead of entire chips. Another modification within the scope of the invention is when entire rows or columns are tested instead of each cell being tested individually. This would have the effect of speeding up the testing process.

Claims

Claims:

1. A method of detecting cell irregularities in a cell array by determining whether the drain current required to read or write to a cell differs from the drain current required to read or write to other cells in a cell array.

2. A method of detecting cell irregularities in a cell array according to claim 1, where the drain current is compared with the average drain current required to charge a cell in the array.

3 A method of detecting cell irregularities in a cell array according to claim 1, where the peak value of the drain current is used in comparing a cell with other cells in an array.