GB2289829A - A decoder for broadcast transmissions - Google Patents
A decoder for broadcast transmissions Download PDFInfo
- Publication number
- GB2289829A GB2289829A GB9411846A GB9411846A GB2289829A GB 2289829 A GB2289829 A GB 2289829A GB 9411846 A GB9411846 A GB 9411846A GB 9411846 A GB9411846 A GB 9411846A GB 2289829 A GB2289829 A GB 2289829A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- primary
- decoder
- processing network
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/60—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals
- H04N5/607—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals for more than one sound signal, e.g. stereo, multilanguages
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
Abstract
A decoder for broadcast transmissions including an input analogue-to-digital converter (2) having an output port connected to a signal processing network (7) capable of demodulating a digital signal in accordance with input control data, an output digital-to-analogue converter (5) connected to an output port of the signal processing network (7) for providing an analogue output signal from the decoder and a control circuit (6) for controlling the decoder. The invention enables the decoder to be used with any of a plurality of standards of communication signals, e.g. TV by selection of internal settings alone. The decoder preferably includes a primary FM demodulating circuit and a secondary FM demodulating circuit for processing a modulated signal including primary and secondary carriers. The decoder includes a DQPSK demodulation and pilot tone detection circuit connected to a deinterleave and a digital phase locked loop circuit. <IMAGE>
Description
"A Decoder for Broadcast Transmissions"
The invention relates to a decoder for receiving and processing broadcast transmissions, especially television sound transmissions.
Broadcast transmissions, for example, television sound transmissions can conform to any one of a plurality of available standards and, as a rule, since carrier frequencies differ from one standard to another, decoding circuitry capable of receiving and processing broadcast transmissions of one standard cannot be converted to receive and process broadcast transmissions of another standard without changing one or more components of that circuitry. That poses a difficulty for manufacturers in that a different design of decoder is required for each standard for which equipment is being manufactured.
It is an object of the present invention to provide a decoder for broadcast transmissions that is capable of being set to conform with any selected standard by the choice of selected internal settings alone.
The invention provides a decoder for broadcast transmissions including an input analogue-to-digital converter having an output port connected to a signal processing network capable of demodulating a digital signal in accordance with input control data, an output digital-to-analogue converter connected to an output port of the signal processing network for providing an analogue output signal from the decoder and a control circuit for controlling the decoder.
Preferably, the decoder includes an input amplifier, having its output port connected to an input port of the analogue-to-digital converter, wherein the input amplifier is capable of providing an output signal of substantially constant envelope amplitude from an input signal of varying envelope amplitude.
Preferably, a demultiplexing circuit is connected between the signal processing network and the output digital-to-analogue converter and, preferably, the control circuit is connected to control the signal processing network, the demultiplexing circuit and the digital-to-analogue converter.
Preferably, the signal processing network is capable of demodulating a dual signal including a primary signal component carried on a primary carrier and a secondary signal component carried on a secondary carrier.
Preferably, the decoder includes a signal processing network including a primary demodulating circuit capable of being set by input control data to demodulate a primary signal component of a dual signal, combining means for so combining a form of the primary signal component with the dual signal as to provide a combined signal having a reduced primary signal component relative to the dual signal and a secondary demodulating circuit capable of demodulating the combined signal in accordance with input control data applied to the secondary demodulating circuit.
A second aspect of the invention is the provision of a signal processing network including a primary demodulating circuit capable of being set by input control data to demodulate a primary signal component of a dual signal, combining means for so combining a form of the primary signal component with the dual signal as to provide a combined signal having a reduced primary signal component relative to the dual signal and a secondary demodulating circuit capable of demodulating the combined signal in accordance with input control data applied to the secondary demodulating circuit.
Preferably, the primary demodulating circuit includes a primary voltage controlled oscillator connected in a primary phase-locked-loop capable of generating a form of the primary signal component that is substantially antiphase to the primary signal component of the dual signal along with the demodulated primary signal component, combining means connected to the primary phase-locked-loop and to a source of the dual signal for combining the antiphase form of the primary signal component with the dual signal and a secondary voltage controlled oscillator connected in a secondary phase-locked-loop which is connected to an output port of the combining means.
Preferably, the signal processing network includes scaling circuits capable of adjusting the amplitudes of partly processed signals as they pass through the signal processing network.
Preferably, the signal processing network includes a system frequency clock and means responsive to input signals for deleting selected system frequency clock pulses in order to provide a reduced frequency clock signal synchronised with the input signals.
The signal processing network is capable of demodulating a dual signal including a primary signal component carried on a primary carrier and a secondary signal component carried on a secondary carrier.
One form of decoder for broadcast transmissions constructed in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings in which:
Fig. 1 is a block diagram representation of a decoder capable of demodulating a dual broadcast television sound signal;
Fig. 2 is a more detailed representation of a part of the decoder of Fig. 1;
Fig. 3 is a block diagram representation of an automatic gain control (AGC) system for the decoder;
Fig. 4 is a block diagram representation of signal processing circuit for the decoder;
Fig. 5 is a representation of a dual broadcast television sound signal showing a primary and a secondary signal component; and
Fig. 6 is a representation of a dual broadcast television sound signal with substantial removal of the primary signal component.
Referring to Fig. 1 of the accompanying drawings, the decoder includes an input amplifier 1 having an output port which is connected to an input port of an analogue-to-digital converter 2, a signal processing network 3 connected between an output port of the analogue-to-digital converter 2 and an input port of a demultiplexing circuit 4, a digital-to-analogue converter 5 having an input port connected to the output port of the demultiplexing circuit 4 and a control circuit 6 connected to the demultiplexing circuit 4, to the signal processing network 3 and to the digital-to-analogue converter 5 which provides an output signal from the decoder on an output port. The decoder includes a further signal processing network 7 connected between an output port of the analogue-to-digital converter and an input port of the demultiplexing circuit 4 and there is a connection between the control circuit 6 and the further signal processing circuit 7.
The decoder shown in Fig. 1 operates on the baseband sound carrier of broadcast television, the amplifier 1 providing amplitude control of an incoming modulated carrier and providing an output signal of substantially constant envelope amplitude from an input signal of varying envelope amplitude. The output signal from the amplifier 1 is presented to the analogue-to-digital converter 2 the output of which passes to the signal processing network 3 and to the further signal processing network 7. The outputs of the signal processing network 3 and the further signal processing network 7 are demultiplexed, as required, by the demultiplexer 4 in accordance with the form of modulation of the input baseband sound signal and then passed to the digital-toanalogue converter 5 which provides any necessary frequency response sloping such as, for example, highfrequency de-emphasis. The control circuit 6 provides input control data according to the broadcast transmission standard to be received and controls the demultiplexer 4, the digital-to-analogue converter 5, the signal processing network 3 and the further signal processing network 7 as necessary.
Referring to Fig. 2 of the accompanying drawings, the decoder includes a dual channel demodulation and automatic gain control (AGC) circuit 20 connected to a data-reduction filter circuit 24 which is itself connected to a digital-to-analogue converter 25. A differential quadrature phase shift keyed (DQPSK) demodulation and pilot tone detection circuit 21 is connected to a deinterleave circuit 22 and to a digital phase locked loop circuit (DPLL) 23. A first output port of the digital phase locked loop circuit 23 is connected to the digital-to-analogue converter 25, a second output port of the digital phase locked loop circuit 23 is returned to the DQPSK demodulation and pilot tone detection circuit 21 and an output port of the interleave circuit 22 is connected to the digital-to-analogue converter 25. The dual channel demodulation and AGC circuit 20 and the DQPSK demodulation and pilot tone circuit are connected to each other.
The dual channel demodulation and AGC circuit 20 performs the functions of primary signal component demodulation, addition of the antiphase primary signal component to provide primary signal component reduction in a combined signal for secondary signal component demodulation, secondary signal component demodulation, scaling and AGC control.
The data-reduction filter circuit 24 reduces the number of samples supplied to the digital-to-analogue converter 25 to 1 out of 512 of the number of samples provided by the dual channel demodulation and AGC circuit 20. A NICAM signal supplied to the dual channel demodulation and AGC circuit 20 passes on to the DQPSK demodulation and pilot tone circuit 21 which depends on the DPLL circuit 23 to achieve alignment of the NICAM signal. The deinterleave circuit 22 separates the data output signal from the DQPSK demodulation and pilot tone detection circuit 21 into two channels for the digital to-analogue converter 25.
The principal function of the DQPSK demodulation and pilot tone circuit 21 is the processing of phase-shiftkeyed signals such as NICAM signals. When the decoder is provided with control data setting it for the processing of conventional frequency-modulated signals, the DQPSK demodulation and pilot tone circuit 21 interacts with the dual channel demodulation and AGC circuit 20 and extracts the pilot carrier from the frequency-modulated signal.
The system frequency is not an integer multiple of
NICAM symbol rate nor is it an integer multiple of NICAM audio and digital-to-analogue converter (DAC) audio sample rate. Clock cycle deletion of the system frequency clock is used to produce a reduced clock frequency that is an integer multiple of NICAM audio and
DAC audio sample rate, deletion being synchronised with the DAC sample input shown in order to minimise distortion. The reduced frequency clock is used by the deinterleave circuit 21 and the digital-to-analogue converter 25 when the decoder is set up for receiving a
NICAM carrier. The system frequency clock is used at times when the decoder is set up to receive signals not including a NICAM carrier. The DQPSK demodulation and pilot tone detection circuit 21, the dual channel demodulation and AGC circuit 20, the control circuit 6 of
Fig. 1 and the data reduction filter 24 always use the system frequency clock.
When the DQPSK demodulation and pilot tone detection circuit 21 is operating to demodulate a NICAM signal, that is, a PSK signal, an input signal "slip request" from the digital phase-locked-loop circuit 23 causes selective deletion of input samples in order to achieve a virtual processing rate that is frequency-locked to the
NICAM symbol rate. In that mode, the DQPSK demodulation and pilot tone detection circuit 21 produced a control signal for the digital phase-locked-loop 23 that locks it to the incoming NICAM symbol rate.
The DQPSK demodulation and pilot tone detection circuit 21 is capable of performing a similar fwtction in the presence of non-NICAM signals to that performed on
NICAM signals, allowing the decoder to demodulate and process frequency-modulated audio both on primary and on secondary carriers, in addition to NICAM signals, employing the same system frequency clock.
Referring to Fig. 3 of the accompanying drawings, the automatic gain control system for the decoder includes a variable gain amplifier 31 an output port of which is connected to an analogue-to-digital converter 32, a first scaling circuit 33 which is connected to an output port of the analogue-to-digital converter 32, an
AGC control circuit 38 which receives digitised samples from the analogue-to-digital converter 32, a primary demodulator 36 which is connected to an output port of the first scaling circuit 33, an addition circuit 34 which is connected to the same output port of the first scaling circuit 33 as is the primary demodulator 36 and, also, to an output port of the primary demodulator 36, a second scaling circuit 35 connected to an output port of the addition circuit 34, an a secondary demodulator 37 connected to an output port of the second scaling circuit 35. Output ports of the AGC control circuit 38 are connected to respective control ports of the first and the second scaling circuits 33, 35 and of the variable gain amplifier 31. A further output port of the AGC control circuit 38 is connected to an input port of the primary modulator 36 an output port of which is connected to a control port of the addition circuit 34.
The primary demodulator 36 receives data determining its operating frequency and demodulates the primary signal component of a dual signal received from the first scaling circuit 33 which has received and scaled digitised samples of an intercarrier sound signal by way of the variable gain amplifier 31 and the analogue-todigital converter 32.
The primary demodulator 36 demodulates the primary signal component and passes the primary signal, with reversed phase to the addition circuit 34 where the signals are combined, resulting in the removal of substantially all of the primary signal component from the signal leaving the addition circuit 34, that signal being scaled by the second scaling circuit 35.
The scaly g signal leaving the second scaling circuit 35, that signal being substantially a secondary signal component alone, passes to the secondary demodulator 37 which demodulates that signal employing second input control data that determines its operating frequency.
Output signals from the primary demodulator 36 and the secondary demodulator 37 go to the AGC control circuit 38 which provides gain and scaling control signals for the variable gain amplifier 31, the first scaling circuit 33 and the second scaling circuit 35.
The AGC control circuit 38 also provides a control signal to the primary demodulator 36 according to whether or not the addition circuit 34 needs to be operative. In the event that the input signal to the system is not a dual signal there is no secondary signal and the addition circuit 34 need not be operative.
The control circuit 6 of Fig. 1 provides input control data for setting the operating frequencies of the primary demodulator 36 and the secondary demodulator 37.
The input control data for the demodulators 36, 37 may be stored in the control circuit 6 or may be stored elsewhere and sent by way of an interface circuit to the control circuit 6.
The provisions of the sealing circuits 33, 35 in addition to the variable gain amplifier 31 permits to the accommodation of a wide range of signals. In particular, the automatic gain control system is able to accommodate frequency-modulated signals including (i) a primary carrier alone, (ii) a primary and a secondary carrier or (iii) a secondary carrier alone. In addition, the automatic gain control system can accommodate a NICAM signal alone or the combination of a NICAM signal with a frequency-modulated signal on a primary carrier.
The primary and secondary demodulators 36, 37 include digital word-controlled oscillators comprising a network of digital adders and digital accumulators which add the respective input control data repeatedly and from respective accumulated totals, the accumulators being cleared when full and the frequency of clearing being the word-controlled frequencies of the respective primary and secondary oscillators.
Referring to Fig. 4 of the accompanying drawings, the signal processing circuit includes a primary demodulator consisting of a first signal combiner 41 and a primary phase-locked-loop detector 42. An output port of the phase-loop-detector 42 is connected to a summation circuit 43, which also receives an input dual signal, and an output port of the summation circuit 43 is connected to a second signal combiner 44 which is connected to a secondary phase-locked-loop detector 45.
The input dual signal is applied to the first signal combiner 41 from which it passes to the primary phaselocked-loop detector 42 which operates in accordance with input control data and provides a demodulated primary signal component. An output from the primary phaselocked-loop detector 42 that is an antiphase phase of the primary signal component is applied to the summation circuit 43 along with the input dual signal. The output from the summation circuit 43 is a combined signal which contains substantially no primary signal component and the combined signal, which is substantially the secondary signal component alone, is demodulated, in accordance with input control data, by the secondary phase-lockedloop detector 45 which receives the secondary signal component by way of the second signal combiner 44.
Referring to Fig. 5 of the accompanying drawings, the dual broadcast television sound signal includes a primary signal extending from about 5400 kHz to 5600 kHz and a secondary signal extending from about 5700 kHz to 5800 kHz, the carrier spacing being about 250 kHz. The primary signal is 20 dB higher than the secondary signal.
As is explained above, a primary phase-locked-loop demodulator is used to demodulate the stronger primary signal component and an antiphase form of the primary signal component, generated by the primary phase-lockedloop demodulator, is added to the dual signal in order to provide a combined signal with substantially no primary signal component.
Referring to Fig. 6 of the accompanying drawings, the combined signal includes the original secondary signal component which is about 10 dB higher than the residual primary signal component, permitting demodulation of the secondary signal component by means of a secondary phase-locked-loop detector.
The gain control system from the primary and secondary phase-locked-loops is such that the primary signal component of the dual signal is matched to a quadrature output signal from a voltage-controlled oscillator of the primary phase-locked-loop which tracks the primary signal component of the dual signal. Also, the phase error in the primary phase-locked-loop is low in order that cancellation of the primary signal component of the dual signal is not disturbed in the presence of strong primary signal component modulation.
The frequencies indicated in Figs. 5 and 6 are typical of the frequencies that the decoder is capable of processing and the relative amplitude indicated in those figures represent worst-case conditions.
Claims (15)
1. A decoder for broadcast transmissions including an input analogue-to-digital converter having an output port connected to a signal processing network capable of demodulating a digital signal in accordance with input control data, an output digital-to-analogue converter connected to an output port of the signal processing network for providing an analogue output signal from the decoder and a control circuit for controlling the decoder.
2. A decoder as claimed in claim 1, including an input amplifier having its output port connected to an input port of the analogue-to-digital converter, wherein the input amplifier is capable of providing an output signal of substantially constant envelope amplitude from an input signal of varying envelope amplitude.
3. A decoder as claimed in claim 1 or claim 2, including a demultiplexing circuit connected between the signal processing network and the output digital-toanalogue converter.
4. A decoder as claimed in claim 3, wherein the control circuit is connected to control the signal processing network, the demultiplexing circuit and the digital-to-analogue converter.
5. A decoder as claimed in any one of claims 1 to 4, including sealing circuits capable of adjusting the amplitudes of partly processed signals as they pass through the signal processing network.
6. A decoder as claimed in any one of claims 1 to 5, wherein the signal processing network includes a system frequency clock and means responsive to input signal for deleting selected frequency clock pulses in order to provide a reduced frequency clock signal synchronised with the input signals.
7. A decoder as claimed in any one of claims 1 to 6, wherein the signal processing network is capable of demodulating a dual signal including a primary signal component carried on a primary carrier and a secondary signal component carried on a secondary carrier.
8. A decoder as claimed in claim 7, wherein the signal processing network includes a primary demodulating circuit capable of being set by input control data to demodulate a primary signal component of a dual signal, combining means for so combining a form of the primary signal component with the dual signal as to provide a combined signal having a reduced primary signal component relative to the dual signal and a secondary demodulating circuit capable of demodulating the combined signal in accordance with input control data applied to the secondary demodulating circuit.
9. A decoder as claimed in claim 8, wherein the primary demodulating circuit includes a primary voltage controlled oscillator connected in a primary phase locked-loop capable of generating a form of the primary signal component that is substantially antiphase to the primary signal component of the dual signal along with the demodulated primary signal component, combining means connected to the primary phase-locked-loop and to a source of the dual signal for combining the antiphase form of the primary signal component with the dual signal and a secondary voltage controlled oscillator connected in a secondary phase-locked-loop which is connected to an output port of the combining means.
10. A decoder substantially as described herein with reference to and as shown by Figs. 1 to 4 of the accompanying drawings.
11. A signal processing network including a primary demodulating circuit capable of being set by input control data to demodulate a primary signal component of a dual signal, combining means for so combining a form of the primary signal component with the dual signal as to provide a combined signal having a reduced primary signal component relative to the dual signal and a secondary demodulating circuit capable of demodulating the combined signal in accordance with input control data applied to the secondary demodulating circuit.
12. A signal processing network as claimed in claim 11, wherein the primary demodulating circuit includes a primary voltage controlled oscillator connected in a primary phase-locked-loop capable of generating a form of the primary signal component that is substantially antiphase to the primary signal component of the dual signal along with the demodulated primary signal component, combining means connected to the primary phase-locked-loop and to a source of the dual signal for combining the antiphase primary signal component with the dual signal and a secondary voltage controlled oscillator connected in a secondary phaselocked-loop connected to an output port of the combining means.
13. A signal processing network as claimed in claim 11 or claim 12, including sealing circuits capable of adjusting the amplitudes of partly processed signals as they pass through the signal processing network.
14. A signal processing network as claimed in any one of claims 11 to 13, including a system frequency clock and means responsive to input signals for deleting selected system frequency clock pulses in order to provide a reduced frequency clock signal synchronised with the input signals.
15. A signal process network substantially as described herein with reference to and as shown by Fig. 4 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9408759A GB9408759D0 (en) | 1994-05-03 | 1994-05-03 | Using high level cad tools to design application specific standard products for tv sound decoder systems |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9411846D0 GB9411846D0 (en) | 1994-08-03 |
| GB2289829A true GB2289829A (en) | 1995-11-29 |
| GB2289829B GB2289829B (en) | 1999-02-10 |
Family
ID=10754488
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9408759A Pending GB9408759D0 (en) | 1994-05-03 | 1994-05-03 | Using high level cad tools to design application specific standard products for tv sound decoder systems |
| GB9411846A Expired - Fee Related GB2289829B (en) | 1994-05-03 | 1994-06-14 | A decoder for broadcast transmissions |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9408759A Pending GB9408759D0 (en) | 1994-05-03 | 1994-05-03 | Using high level cad tools to design application specific standard products for tv sound decoder systems |
Country Status (1)
| Country | Link |
|---|---|
| GB (2) | GB9408759D0 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2106734A (en) * | 1981-09-15 | 1983-04-13 | Standard Telephones Cables Ltd | Radio receiver |
| GB2149244A (en) * | 1983-10-29 | 1985-06-05 | Standard Telephones Cables Ltd | Digital demodulator arrangement for quadrature signals |
| EP0437965A2 (en) * | 1989-12-21 | 1991-07-24 | Samsung Electronics Co. Ltd. | Broadcast receiving apparatus for television signals |
| US5202766A (en) * | 1987-11-06 | 1993-04-13 | Deutsche Itt Industries Gmbh | Sound channel circuit for digital television receivers |
-
1994
- 1994-05-03 GB GB9408759A patent/GB9408759D0/en active Pending
- 1994-06-14 GB GB9411846A patent/GB2289829B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2106734A (en) * | 1981-09-15 | 1983-04-13 | Standard Telephones Cables Ltd | Radio receiver |
| GB2149244A (en) * | 1983-10-29 | 1985-06-05 | Standard Telephones Cables Ltd | Digital demodulator arrangement for quadrature signals |
| US5202766A (en) * | 1987-11-06 | 1993-04-13 | Deutsche Itt Industries Gmbh | Sound channel circuit for digital television receivers |
| EP0437965A2 (en) * | 1989-12-21 | 1991-07-24 | Samsung Electronics Co. Ltd. | Broadcast receiving apparatus for television signals |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2289829B (en) | 1999-02-10 |
| GB9411846D0 (en) | 1994-08-03 |
| GB9408759D0 (en) | 1994-06-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20100614 |