GB2288956A

GB2288956A - Error detection circuit

Info

Publication number: GB2288956A
Application number: GB9408441A
Authority: GB
Inventors: Alexandre Saper; Gil Patel; Itzhak Barak
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1994-04-28
Filing date: 1994-04-28
Publication date: 1995-11-01
Anticipated expiration: 2014-04-28
Also published as: GB9408441D0; FR2719430A1; DE19515572A1; GB2288956B; FR2719430B1

Description

2288956 ERROR DETECTION CIRCUIT

FIELD OF THE INVENTION

This invention relates to an error detection circuit and particularly, but not exclusively, to a bit-segment error detection circuit.

BACKGROUND OF THE INVENTION

Data bits of a digital data signal are created to be in one of two well defined states., denoting either a logical 1 (high state) or a logical 0 (low state). However, noisy circuits and data paths give rise to the states of the data bits of a data signal becoming less well defined as they propagate through circuits and paths. Data errors often occur when data bits become corrupted in this way.

Bit error detection circuits are known which can cheek the validity of incoming bits and identify errors when a defined validity threshold is exceeded. However, a problem with such circuits is that the defined threshold for detecting an error is typically fixed and as a result, the error detection is often excessively sensitive, leading to unnecessary resending of valid data bits which slow down the data transfer. Moreover, the error detection may not be sensitive enough, thereby allowing erroneous data bits to be received undetected.

This invention seeks to provide an error detection circuit in which the above mentioned disadvantages are mitigated.

SUMMARY 0 THE INVENTION

According to the present invention there is provided an error detection circuit comprising an input terminal coupled to receive a data signal having a level that varies between higher and lower limits; sampling means coupled to the input terminal for sampling the data signal over a predetermined period to provide a plurality of samples of the data signal, each sample having either a first or a second signal level depending on whether the level of the data signal, when sampled, is nearer the higher or lower limit, respectively; counting means coupled to the sampling means for counting the number of samples having the first signal level and the number of samples having the second signal level; comparing means coupled to receive a predetermined value and coupled to the counting means for comparing the number of samples having the first signal level and the number of samples having the second signal level with the predetermined value and for generating a first output signal if the number of samples having the first signal level exceeds the predetermined value and for generating an error signal if both the number of samples having the first signal level and the number of samples having the second signal level exceed the predetermined value.

Preferably the comparing means is arranged for generating a second output signal if the number of samples having the first signal level does not exceed the predetermined value. Alternatively, the comparing means can be preferably arranged for generating a second output signal if the number of samples having the second signal level exceeds the predetermined value.

The sampling means preferably comprises logic means coupled to detect the level of the data signal, the logic means comprising a first AND gate coupled to receive a clock signal and the data signal and a second AND gate coupled to receive the clock signal and coupled to a NOT gate to receive the data signal inverted; wherein the first AND gate generates said first signal level when the data signal is nearer to one of the higher and lower limits and the second AND gate generates said second signal level when said level of the data signal is nearer the other of the higher and lower limits.

The counting means preferably comprises a first counter arranged to count the number of samples having the first signal level and a second counter arranged to count the number of samples having the second signal level.

Preferably the comparing means comprises a first and a second comparator, a first and second latch and a control means) the control means for providing the predetermined number; wherein if the number of samples having the first signal level exceeds the predetermined number, then the first comparator sets the first latch, and if the number of samples having the c 0 second signal level exceeds the predetermined number, then the second comparator sets the second latch.

In a preferred embodiment, the predetermined period corresponds to the period of one data bit. Preferably, the counting means and the comparing means are reset at the beginning of each predetermined period.

In this way, by varying the predetermined number a range of validity threshold values are available with which to verify the validity of incoming 10 data bits.

BRIEF DESCRIPTION OF THE DRAWINGS

An exemplary embodiment of the invention will now be described with 15 reference to the drawing in which:

FIG. 1 shows a preferred embodiment of an error detection circuit in accordance with the invention.

FIG.2 shows a profile view of a typical data bit operated on by the error detection circuit of FIG. 1.

FIG.3 shows a truth table pertaining to the error detection circuit of FIG. 1.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Referring to FIG. 1, there is shown an error detection circuit 10. A data input terminal 15 of the circuit 10 is coupled to receive a digital data signal from a serial data source, such as a serial bus or data port. A clock input terminal is coupled to receive a clock signal. The clock signal is synchronised to the digital data signal so as to divide a single bit of the data signal into a number of segments.

A first AND gate 25 has a first input coupled to the data input terminal 15, a second input coupled to the clock input terminal 20 and an output. Similarly, a second AND gate 35 has a first input coupled to the data input terminal 15 via a NOT gate 30, a second input coupled to the clock input terminal 20 and an output.

In this way a sampled segment of the digital data signal is taken at every occurrence of the clock signal. The sampled segment will have a value of either logical 1 (high) or logical 0 (low). If the sampled segment value is high (logical 1), then the two inputs of the first AND gate 25 will be high and therefore the output thereof will also be high. Conversely if the sampled segment is low (logical 0), then the two inputs of the second AND gate 35 will be high and therefore the output thereof will also be high. Thus, the level of the data bit is sampled several times over the period of the data bit.

A first counter 40 and a second counter 45 are coupled to the outputs of the first and second AND gates 25 and 35 respectively. The first counter 40 is therefore arranged to count the number of sampled segments which are high and the second counter is arranged to count the number of sampled segments which are low.

A control input terminal 60 is coupled to receive a control signal from a user device or switch, the control signal to be further described below.

A first comparator 50 is coupled to receive the control signal from the control input terminal 60 and is further coupled to the first counter 40 and to a first latch 52. The control signal indicates a value corresponding to a number of sampled segments. If the first counter 40 counts up to the value indicated by the control signal, then the first comparator 50 sets the first latch 52. Similarly a second comparator 55 is coupled to receive the control signal from the control input terminal 60 and is further coupled to the second counter 45 and to a second latch 57. In the same way if the second counter 45 counts up to the value indicated by the control signal, then second comparator 55 sets the second latch 57.

The first latch 52 and the second latch 57 have outputs which are switched on if the latches are set. A data output terminal 70 is coupled to receive the output from the first latch 52.

cl 0 A third AND gate 65 has an input coupled to the output from the first latch 52, an input coupled to the output from the second latch 57 and an output coupled to an error signal output terminal 75. In this way if both latches 52 and 57 are set, the AND gate has a high output which generates a signal at the error signal output terminal 70.

With reference also to FIG.2 there is shown a graph of voltage V against time T for a typical data bit. Ideally the data bits on the data path connected to the data input terminal 15 would be in a well defined state, either high or low. In reality however, due to noise on the data path and possibly other factors, the data bits have a less than idealised profile, as depicted in the data bit of FIG.2. If a sample taken from the middle of the data bit were used to determine the state, then the result would be high. However, inspection of the profile shows that the data bit, whilst not conclusively in either of the two well defined states, is more likely to represent a low state.

In operation, the data bit of FIG.2 is received at the data input terminal 15.

The clock signal received at the clock input terminal 20 has a first clock pulse which identifies a first segment 80 of the data bit. Subsequent second, third, fourth and fifth clock pulses identify further segments 85, 90, 95 and 100 respectively.

The clock signal is generated by an internal pre-scaler from the internal clock of a device to which the error detection circuit 10 is coupled.

The control input terminal 60 receives the control signal continuously during the operation of the error detection circuit 10. Thus the comparators 50 and are supplied with a threshold value. If the number of samples counted by the counter 40 exceeds this threshold value, then the first comparator 50 sets the first latch 52. Similarly if the number of samples counted by the counter exceeds the threshold value, then the second comparator 55 sets the second latch 57. In this way, the tolerance of the error detection circuit 10 is variable, being dependent upon the threshold value contained within the control signal.

Taking the first clock pulse, the value of the data signal at a first segment 80 is less than a threshold median 105 and therefore constitutes a low state.

The threshold median 105 is determined by the internal threshold of the AND gates 25 and 35. The arrangement of the AND gates 25 and 35 and the NOT gate 30 is such that the AND gates 25 and 35 operate in a mutually exclusive manner. The first input of the first AND gate 25 is low, so the output thereof is also low. Conversely, the first input of the second AND gate 35 is high by virtue of the NOT gate 30, so the output thereof is also high. Therefore the second counter 45 is incremented by one.

The above sequence is repeated for subsequent segments of the data bit generated by the clock pulses, the first counter 40 being incremented if the segment value is high, and the second counter being incremented if the segment value is low. Hence for the data bit of FIG.2 the first counter is incremented at the third segment 90, and the second counter is incremented at all of the other segments (80, 85, 95 and 100).

At the end of the period of sampling of the data bit, the first counter has the value 1 and the second counter 45 has the value 4, indicating the number of sampled segments which were high and low respectively.

If the value set by the control signal is 2, then only the second latch 57 will be set. Therefore the data output terminal 70 has a low (logical 0) signal, the third AND gate 65 output is low and the error signal is not generated at the error signal output terminal 70. Therefore the result is a logical 0 with no error.

error.

If the value set by the control signal is 1, then both the first latch 52 and the second latch 57 will be set. Therefore the data output terminal 70 has a high (logical 1) signal, the third AND gate 65 output is high and the error signal is generated at the error signal output terminal 70. Therefore the result is an Thus for the same data bit, as shown in FIG.2, an error can be detected or disregarded depending on the value of the control signal.

At the end of the sampling period of the data bit, the first and second counters 40 and 45 and the first and second latches 52 and 57 are reset, in preparation for the next data bit.

VIP 0 BY way of example, and with reference also to FIG.3, there is shown a truth table of results for a five segment data bit, having a control signal value of 1. Each of the possibilities of segment values is shown. A row 5 of FIG.3 represents the data bit of FIG.2. In the row 5 there are four segments having the low value and one segment having the low value The error detection circuit 10 is thus arranged to operate with a variable error tolerance as provided by the control signal. Furthermore it is 10 independent of the number of segments sampled.

It will be appreciated that alternative embodiments to the one hereinbefore described may be achieved, such as the use of a shift register to replace the first and second counters 40 and 45.

Furthermore, a discrete logic implementation of the truth table of FIG.3 could be used instead of the first and second comparators 50 and 55, the first and second latches 52 and 57 and the third AND gate 65.

In addition, the first and second latches 52 and 57 and AND gate 65 could be arranged, with the use of inverters or similar, such that the second latch 57 provides the output to the data output terminal 70.

Claims

1. An error detection circuit comprising an input terminal coupled to receive a data signal having a level that varies between higher and lower limits; sampling means coupled to the input terminal for sampling the data signal over a predetermined period to provide a plurality of samples of the data signal, each sample having either a first or a second signal level depending on whether the level of the data signal, when sampled, is nearer the higher or lower limit, respectively; counting means coupled to the sampling means for counting the number of samples having the first signal level and the number of samples having the second signal level; comparing means coupled to receive a predetermined value and coupled to the counting means for comparing the number of samples having the first signal level and the number of samples having the second signal level with the predetermined value and for generating a first output signal if the number of samples having the first signal level exceeds the predetermined value and for generating an error signal if both the number of samples having the first signal level and the number of samples having the second signal level exceed the predetermined value.

2. The error detection circuit of claim 1 wherein the comparing means is arranged for generating a second output signal if the number of samples having the first signal level does not exceed the predetermined value,

3. The error detection circuit of claim 1 wherein the comparing means is arranged for generating a second output signal if the number of samples 30 having the second signal level exceeds the predetermined value,

4. The error detection circuit of any preceding claim wherein the sampling means comprises logic means coupled to detect the level of the data signal.

5. The error detection circuit of claim 4 wherein the logic means comprises a first AND gate coupled to receive a clock signal and the data 1 -f signal and a second AND gate coupled to receive the clock signal and coupled to a NOT gate to receive the data signal inverted; wherein the first AND gate generates said first signal level when the data signal is nearer to one of the higher and lower limits and the second AND gate generates said second signal level when said level of the data signal is nearer the other of the higher and lower limits.

6. The error detection circuit of any preceding claim wherein the counting means comprises a first counter arranged to count the number of samples having the first signal level and a second counter arranged to count the number of samples having the second signal level.

7. The error detection circuit of any preceding claim wherein the comparing means comprises a first and a second comparator, a first and second latch and a control means, the control means for providing the predetermined number.

8. The error detection circuit of claim 7 wherein if the number of samples having the first signal level exceeds the predetermined number, then the first comparator sets the first latch, and if the number of samples having the second signal level exceeds the predetermined number, then the second comparator sets the second latch.

9. The error detection circuit of any preceding claim wherein the predetermined period corresponds to the period of one data bit.

10. The error detection circuit of any preceding claim wherein the counting means and the comparing means are reset at the beginning of each predetermined period.

11. An error detection circuit as ubstantially hereinbefore described and with reference to the drawings.