GB2288015A

GB2288015A - An optical encoder with an improved photodiode array

Info

Publication number: GB2288015A
Application number: GB9505456A
Authority: GB
Inventors: Tatsuhiko Matsuura
Original assignee: Mitutoyo Corp
Current assignee: Mitutoyo Corp
Priority date: 1994-03-31
Filing date: 1995-03-17
Publication date: 1995-10-04
Anticipated expiration: 2015-03-17
Also published as: DE19512258A1; GB9505456D0; GB2288015B; DE19512258C2

Description

2288015 OPTICAL ENCODER HAVING A PHOTODIODE ARRAY THAT SERVES BOTH FOR A

LIGHT DETECTOR AND AN INDEX SCALE The present invention relates to an optical encoder for use with a linear encoder and a rotary encoder, in particular, an optical encoder having a photodiode array that serves both for a light detector and an index scale.

An optical encoder as shown in Fig. 10 is known. An LED 81 emits a light beam to an concave mirror 82. The concave mirror 82 reflects a collimated light beam 83 to a main scale 84. The main scale 84 has a scale formed of an optical lattice. The optical lattice has slits formed at predetermined pitches. In parallel with the main scale 84, an index scale 85 having an optical lattice that is same as the optical lattice of the main scale 84 is disposed. Behind the index scale 85, a light detector is disposed.

When the main scale 84 is relatively moved in arrow directions of Fig. 10 against the Index scale 85, the light detector 85 can detect a bright/dark pattern that takes place due to an overlap of the optical lattices of the main scale 84 and the Index scale 85. Thus, by processing the output current of the light detector 86, the displacement of the main scale can be measured.

In the optical encoder, as shown in Fig. 11, to obtain a zero point signal, zero point detecting patterns P1 and P2 are formed on the main scale 84 and the index scale 85, respectively as shown in Fig. 11. The zero point detecting patterns P1 and P2 are formed of a plurality of slits that are non-uniformly aligned. To detect the overlap of the zero point detecting patterns P1 and P2, in addition to the light detector 86 shown In Fig. 10, a zero point light detector 86b is disposed. When the two zero point detecting patterns P1 and P2 completely overlap with each other, since 1 the zero point detecting light detector 86b detects a peak current, the position at which the peak-current is detected is defined as a zero point position (measurement reference point).

The advantages of the zero point detecting patterns that are formed of a plurality of slits non-uniformly aligned are described in USP 4,451,731.

The zero point detecting circuit is constructed as shown in Fig. 12. Referring to Fig. 12, the output current of the zero point detecting light detector 86b, is supplied to a current-voltage converter 101 that has an operational amplifier OP31. The current-voltage converter 101 converts the output current of the zero point detecting light detector 86b into a voltage value. The voltage value is supplied to a comparing circuit 102 that has an operational amplifier OP32. The comparing circuit 102 compares the voltage value with a predetermined reference voltage VREF and outputs a zero point signal Z.

Fig. 13 is a graph showing an output FZ-OUT of the current-voltage converter 101 of the detecting circuit shown In Fig. 12 and the wave form of the zero point signal z. In the graph, the horizontal axis represents a displacement X. Since a peak voltage P shown in Fig. 13 is obtained at the position where the zero point detecting pattern P1 of the main scale 84 accords with the zero point detecting pattern P2 of the index scale 85, the peak voltage P is compared with a comparing voltage VC so as to obtain the zero point signal Z.

In the related art reference, as shown in Fig. 13, as the output FZ-OUT of the current-voltage converter, a nonpeak voltage NP2 with the same polarity as the peak voltage P takes place before and after the zero point position. This is because even if the position of the zero point detecting pattern P1 of the main scale 84 and the position of the zero point detecting pattern P2 of the index scale 85 deviate from the completely overlap position thereof, part P X p of the slits thereof overlaps with each other. Since the non-peak voltage NP becomes a noise in obtaining the peak voltage P, a comparison voltage VC of the comparing circuit 102 should be set in the range of V2 shown in Fig. 13 so as to prevent the non-peak voltage NP from being mistakenly output as the zero point signal Z.

In the related art reference, to securely output the zero point signal, the construction of the zero point detecting circuit becomes complicated. When the light amount of the light source, the sensitivity of the light detector, and so forth fluctuate, the absolute values of the peak voltage P and the non-peak voltage NP2 shown in Fig. 13 are not determined. Thus, to prevent the non-peak voltage from being detected as the zero point signal, the level of the detecting circuit and the light amount should be adjusted. Specifically, in Fig. 12, the level of the nonpeak voltage NP2 is adjusted by a variable resistor VRl of the current-voltage converter 101. The caparison voltage VC is adjusted by a variable resistor VR2 of the comparing circuit 102.

Techniques for preventing a noise of zero point detection due to an output obtained at a position where two zero point detecting patterns deviate from the completely overlap position thereof are disclosed in for example USP 4,451,731 and USP 4,691,101. For example, an index pulse generating means in USP 4,691,101 has an interdigitated structure in which light detectors are disposed at spaces of a plurality of zero point detecting light detectors corresponding to a multiple slits pattern for detecting the zero point on a code wheel. By obtaining the difference between push-pull outputs I and I generated by an interdigitated light detectors, an index pulse (namely, the zero point signal) can be generated.

However, in the interdigitated light detectors of USP 4,691,101, since the light detectors are additionally disposed only in spaces of the zero point detecting light JI detectors, the noise cannot be completely suppressed. To suppress the noise, in USP 4,691,101, as with USP 4,451,731, a dummy transmitting portion is formed in all the scale so T that I of the push-pull outputs I and I always exceeds a predetermined level at other than the zero point position.

An object of the present invention is to provide an optical encoder that securely detects the zero point without need to adjust the light amount and the zero point detecting circuit.

Another object of the present invention is to provide an optical encoder that prevents a non-peak voltage with the same polarity as a peak voltage from taking place in the vicinity of the zero point so as to securely detect the zero point.

The present invention is an optical encoder having a photodiode array that serves both for a light detector and an index scale, comprising a light emitting means for emitting a collimated light beam, a photodiode array having a plurality of photodiodes disposed opposite to the light emitting means at predetermined pitches and adapted for receiving the collimated light beam from the light emitting means and for serving for the index scale, a main scale disposed between the photodiode array and the light emitting means, the scale being relatively movable in the directions of an arrangement of the photodiodes and having slits formed at predetermined pitches, and a signal processing means for processing an output signal of the photodiode array so as to obtain the amount of displacement, wherein the main scale has a first zero point detecting pattern in which a plurality of transmitting portions are nonuniformly formed, wherein the Rhotodiode array has a plurality of photodiodes of a first group that constructs a second zero point detecting pattern that is substantially the same as the first zero point detecting pattern, wherein the photodiode array further has a plurality of photodiodes of a second R group disposed in spaces and at outside of both edges of the photodiodes of the first group, and wherein the signal processing means has zero point detecting means for obtaining the difference between all outputs of the photodiodes of the first group and all outputs of the photodiodes of the second group and for generating a zero point signal at a scale potion where the first zero point detecting pattern overlaps with the second zero point detecting pattern.

According to the present invention, at the position where the first zero point detecting pattern of the main scale completely overlaps with the second zero point detecting pattern of the photodiode array that also serves for the index scale, the zero point signal is obtained. In the present invention, the photodiodes of the second group are disposed not only at spaces adjacent to the photodiodes of the first group, but at outside of both edges of the arrangement of the photodiodes of the first group.

Preferably, the width of each of the non-zero point detecting photodiodes of the second group is set to be larger than the width of each of the photodiodes of the first group. Thus, the polarity of the peak voltage (current) that is obtained at the scale position where the first zero point detecting pattern of the main scale completely overlaps with the second zero point detecting pattern of the index scale can be reverse of the polarity of the non-peak voltage (current) obtained at a non-overlap position. In other words, at the zero point position, only the outputs of the photodiodes of the first group are obtained. At other than the zero point position, the total output of the photodiodes of the second group is always larger than the total output of the photodiodes of the first group. Thus, when the difference between the total output of the photodiodes of the first group and the total output of the photodiodes of the second group is obtained, if the peak voltage of the zero point signal is negative, the non- peak voltage at other than the zero point position is always positive.

According to the present invention, it is not necessary to adjust the comparison voltage of the comparing circuit that obtains the zero point signal corresponding to the fluctuation of the light amount of the light source and the sensitivity of the light detectors. In other words, the comparison voltage can be fixed. Consequently, the variable resistors for adjusting the light amount and level of the comparing circuit can be omitted. In addition, the photodiodes of the first and second groups can be integrally disposed on the semiconductor chip that constructs the photodiode array that serves for the index scale, the entire size of the encoder can be reduced.

These and other objects, features and advantages of the present Invention will become more apparent in light of the following detailed description of best mode embodiments thereof, as illustrated in the accompanying drawings, in which:

Fig. 1 Is a schematic diagram showing a construction of an optical system of an optical encoder according to an embodiment of the present invention; Figs. 2A and 2B are schematic diagrams showing a zero point detecting pattern of a main scale according to the embodiment of the present invention; Figs. 3A and 3B are schematic diagram showing a zero point detecting pattern of an index according to the embodiment of the present invention; Fig. 4 is a schematic diagram showing a construction of a zero point detecting circuit according to the embodiment of the present invention; Fig. 5 Is a graph showing an output voltage wave f orm of the zero point detecting circuit according to the embodiment of the present invention; Figs. 6A, 6B, and 6C are schematic diagrams showing overlaps of the zero point detecting pattern of the main scale and the zero point detecting pattern of the index according to the embodiment of the present invention; Fig. 7 is a schematic diagram showing an overlap of the zero point detecting pattern of the main scale and the zero point detecting pattern of the index according to the embodiment of the present invention; Fig. 8 is a graph showing the difference between nonpeak voltage wave forms with a non-zero point detecting pattern; Fig. 9 is a schematic diagram showing a construction of a zero point detecting circuit according to another embodiment of the present invention; Fig. 10 is a schematic diagram showing a construction of an optical system of an optical encoder of a related art reference; Fig. 11 is a schematic diagram showing a zero point detecting pattern of the related art reference; Fig. 12 is a schematic diagram showing a construction of a zero point detecting circuit of the related art reference; and Fig. 13 is a graph showing an operating wave form of the zero point detecting circuit of the related art reference.

Fig. 1 shows a construction of an optical system of an optical encoder according to an embodiment of the present invention. In Fig. 1, a light emitting means is constructed of an LED 11 and a concave mirror 12. The LED 11 emits a light beam to the concave mirror 12. The concave mirror 12 outputs a collimated light beam 13. The collimated light beam 13 is radiated to a main scale 14. The main scale 14 has a scale of an optical lattice formed of slits at predetermined pitches. The light beam that passes through the main scale 14 Is transmitted to a photodiode array 15.

The photodiode array 15 is composed of a silicon substrate and a plurality of photodiodes that are integrally disposed thereon corresponding to the slit arrangement of the main scale 14. The photodiode array 15 functions as an index scale. The output of the photodiode array 15 is supplied to a signal processing circuit 16. The signal processing circuit 16 calculates the amount of displacement corresponding to the output current that varies as the scale moves.

Figs. 2A and 2B are a side view and a plan view of a first zero point detecting pattern formed at a predetermined position of the main scale 14, respectively. In this embodiment, as shown in Fig. 2B, f our slits Sl to S4 are non-uniformly aligned as transmitting portions. The width of each of the slits Sl to S4 is 45 pm.

Figs. 3A and 3B are a side view and a plan view showing a second zero point detecting pattern (referred to as a Z phase pattern) and a non-zero point detecting pattern (referred to as a ZB phase pattern) formed on the photodiode array 15 corresponding to the f irst zero point detecting pattern of the main scale shown in Fig. 2, respectively. Photodiodes ZPD1, ZPD2, ZPD3, and ZPD4 of a f irst group construct the Z phase pattern. The arrangement of the photodiodes ZPD1, ZPD2, ZPD3, and ZPD4 accords with the arrangement of the slits Sl, S2, S3, and S4 that construct the zero point detecting pattern of the main scale, respectively. In wide spaces adjacent to the photodiodes ZPD1 to ZPD4 of the first group, the photodiodes ZBPD1, ZBPD2, ZBPD3, and ZBPD4 of the second group that construct the ZB pattern are disposed. An important feature of the present invention is in that at not only the spaces of first group, but both edges of the arrangement thereof, the photodiodes ZBPD1 and ZBPD4 of the second group are disposed. The output currents of the photodiodes ZPD1 to ZPD4 of the first group are added and become a Z phase output current. Likewise, the output currents of the v photodiodes ZBPD1 to ZBPD4 of the second group are added and become a ZB phase output current.

Specifically, in this embodiment, as shown in Fig. 3B, each of the photodiodes ZPD1 to ZPD4 that construct the Z phase pattern has a light detecting surface of 45 pm that is the same as the width of each slit of the zero point detecting pattern of the main scale. At the spaces adjacent to the photodiodes ZPD1 to ZPD4 and at the spaces larger than 45 pm at outside of both edges of the arrangement thereof, the photodiodes MPD1 to MPD4 are disposed so that spaces larger than 45 pm are not left.

The width of each of at least the photodiodes ZBPD1 and ZBPD4 placed at both edges in the photodiodes UPD1 to ZBPD4 that construct the ZB phase pattern is larger than the width of each of the photodiodes ZPD1 to ZPD4 that construct the Z phase pattern. Specifically, as shown in Fig. 3B, a pitch al of the photodiode ZBM at the left edge of the second group is larger than a pitch a2 of the photodiode ZPD4 at the right edge of the first group. A pitch bl of the photodiode ZBPD4 at the right edge of the second group is larger than a pitch b2 of the photodiode ZPD1 at the left edge of the first group. Thus, as will be described later, a non-peak voltage that takes place at a position apart from the zero point position is prevented from becoming the same polarity as a peak voltage that takes place at the zero point position.

Fig. 4 shows a construction of a zero point detecting circuit of the signal processing circuit 16. The zero point detecting circuit processes the Z phase output and the ZB phase output of the photodiode groups that construct the Z phase pattern and the ZB phase pattern, respectively, so as to detect the zero point. The zero point detecting circuit comprises two current-voltage converters 41 and 42, a differential amplifier 43, an a comparing circuit 44. The differential amplifier 43 obtains the difference between the outputs of the current-voltage converters 41 and 42. The comparing circuit 44 compares the output of the differential amplifier 43 with a predetermined comparison voltage and outputs the zero point signal Z.

The light detected currents of the photodiodes ZPD1 to ZPD4 that construct the Z phase pattern are obtained as the Z phase output. The Z phase output is supplied to the current-voltage converter 42 that has an operational amplifier OP2. The light detected currents of the photodiodes UPD1 to ZBPD4 that construct the ZB phase pattern are obtained as the ZB phase output. The ZB phase output is supplied to the current-voltage converter 41 that has an operational amplifier OP1. The current-voltage converter 41 converts the ZB output to a voltage value.

The outputs of the two current-voltage converters 41 and 42 are supplied to the differential amplifier 43. The differential amplifier 43 comprises an operational amplifier OP3, and resistors R3, R4, R5, and R6. The differential amplifier 43 obtains the difference between the outputs of the two current-voltage converters 41 and 42 and outputs a differential output FZ-OUT. The differential output signal FZ-OUT varies from positive to negative against the reference voltage of the detecting circuit corresponding to the movement of the main scale as shown in Fig. 5. However, as will be described later, the polarity of only the peak voltage P that represents the zero point position becomes negative.

The differential output signal FZ-OUT is supplied to the comparing circuit 44. The comparing circuit 44 comprises an operational amplifier OP4 and resistors R7, R8, and R9. The comparing circuit 44 compares the differential output signal FZ-OUT with a predetermined fixed comparison voltage VC corresponding to the ratio of the resistors R7 and RB, detects only the peak voltage P as shown in Fig. 5, and outputs the peak voltage P as the zero point signal Z.

Figs. 6A, 6B, and 6C show overlaps of the zero point detecting pattern of the main scale 14 and the Z phase 1 f pattern and the ZB phase pattern of the photodiode array 15 in the case that the main scale 14 of the encoder according to the embodiment is relatively moved against the photodiode array 15. In Figs. 6A, 6B, and 6C, the hatched portions represent light patterns that transmit the slits S1 to S4 constructing the zero point detecting pattern of the main scale and that are formed on the photodlode array 15.

Fig. 6A shows a complete overlap of the slits S1 to S4 and the photodiodes ZPD1 to ZPD4 that construct the Z phase pattern on the photodiode array 15 at the zero point position. In this case, light detected currents flow in all the photodiodes ZPD1 to ZPD4. These currents are added and a large Z phase output is obtained. At this point, since a light beam is not radiated to the photodiodes ZBPD1 to ZBPD4 that construct the ZB phase pattern, the ZB phase output is zero.

Fig. 6B shows an overlap of the slit S2 and the photodiode ZPD1 of the Z phase in the case that the main scale 14 slightly moves leftward against the position shown in Fig. 6A. In this case, although a light detected current is obtained from the photodiode ZPD1, since the slits S1, S3, and S4 overlap with the photodiodes ZBPD1, ZBM2, and MPD3 of the M phase, respectively, a ZB phase output that is larger than the Z phase output is obtained.

Fig. 6C shows an overlap of the slit S4 and the photodiode ZPD3 of the Z phase in the case that the main scale 14 further moves leftward. In this case, as is clear from Fig. 6C, the ZB phase output is larger than the Z phase output.

Fig. 6B and 6C show two cases of overlaps in which the main scale moves from the zero point position. The photodiodes UPD1 to ZBPD4 that construct the ZB phase pattern and the photodiodes ZPD1 to ZPD4 that construct the Z phase pattern are laid out - through a simulation so that the ZB phase output is always larger than the Z phase output at other than the zero point position shown in Fig. 6A.

When the output of the current-voltage converter 41 of the Z phase shown in Fig. 4 is compared-with the output of the current-voltage converter of the ZB phase, the former output is always larger than-the later output at other than the zero point position. Thus, as shown in Fig. 5, the output FZ-OUT of the differential amplifier 43 is a negative large peak voltage P at only the zero point position. The non-peak voltage NP1 that takes place at other than the zero point position is always positive.

In the case of the related art reference shown in Fig. 13, the selective range of the comparison voltage VC is V2 between the peak voltage P and the nonpeak voltage NP2 that have the same polarity. On the other hand, in this embodiment, as is clear from Fig. 5, the comparison voltage VC can be selected from a wide range of voltage V1 from the reference voltage VREF to the peak value P of the peak voltage P. Thus, the comparison voltage VC can be fixed and the zero point signal Z can be securely obtained. Consequently, the adjustment of light amount can be omitted. In addition, variable resistors for adjusting the level and the so forth can be omitted.

Especially, in this embodiment, as shown in Fig. 3B, since the photodiodes ZBPD1 and ZBPD4 that obtain the ZB phase output are disposed outside the photodiodes PD1 to PD4 that obtain the Z phase output, the polarity of the non-peak voltage NP1 is always reverse of the polarity of the peak voltage P. Next, with reference to Figs. 7 and 8, the reverse relation of polarities of the non-peak voltage NP1 and the peak voltage P will be described in detail.

Figs. 6A, 6B, and 6C show the relation between the main scale 14 and the photodiode array 15 at a position close to the zero point position. Fig. 7 shows the relation between the main scale 14 and the photodiode array 15 at a position apart from the zero point position. In other words, Fig. 7 shows the case that the main scale 14 moves rightward in the X direction and that the slit S4 at the right edge on the main scale overlaps with the photodiode ZPD1 at the left edge of the zero point detecting pattern on the photodiode array 15. Before this situation takes place, the slit S3 at the second right position of the main scale 14 overlaps with the non-zero point detecting photodiode ZBPD1 on the left of the photodiode ZPD1. Thus, as shown in Fig. 8, when the two zero point detecting patterns start overlapping with each other, the positive non-peak voltage NP1 is obtained.

If the non-zero point detecting photodiode ZBPD1 is not provided, in the situation shown in Fig. 7, only the Z phase output is obtained. When the scale further moves, the slit S2 overlaps with the second photodiode ZPD2, thereby generating the next Z phase output. Thus, as denoted by a dotted line of Fig. 8, A-negative non-peak voltage NP3 takes place. As with the related art reference, the negative nonpeak voltage NP3 becomes a noise against the detection of the negative peak voltage P.

In contrast to the case shown in Fig. 7, when the main scale 14 moves leftward to the photodiode array 15 and both the zero point detecting patterns thereof overlap with each other, the same situation takes place. In this case, since the non-zero point detecting photodiode ZBPD4 is disposed on the right of the photodiode ZPD4, a negative non-peak voltage can be prevented from taking place.

The condition to prevent the non-peak voltage with the same polarity as the peak voltage from taking place is in that arrangement pitches al, a2, bl, and b2 at both edges of all the photodiodes of the Z phase pattern and the ZB phase pattern satisfy the relations of al > a2 and bl > b2.

Fig. 9 shows a construction of a zero point detecting circuit according to another embodiment of the present invention. The construction of the optical system of the first embodiment is the same as that of the second embodiment. In the first embodiment, the Z phase output current and the ZB phase output current are individually converted into voltage values and the difference thereof is obtained. On the other hand, in the second embodiment, the difference of current levels is obtained. In other words, a parallel circuit of photodiodes ZPD1 to ZPD4 of the Z phase and a parallel circuit of photodiodes ZBPDl to ZBPD4 are connected in series.

When the photodiodes ZPD1 to ZPD4 of the Z phase are connected to the photodiodes ZBPD1 to ZBPD4 of the ZB phase, the difference between the Z phase output current and the ZB phase output current is obtained at the connecting node. The current difference is converted into a voltage value by a current-voltage converter 45 that has an operational amplifier OP5. The current-voltage converter 45 outputs FZOUT that is equivalent to the output FZ-OUT of the first embodiment. Thus, by a-comparing circuit 44 similar to that of the first embodiment, the zero point signal Z can be obtained.

It should be noted that the present invention is not limited to the abovedescribed embodiments. In the abovedescribed embodiments, a concave mirror is used as a collimate means. However, the present invention can be applied to an optical encoder using an convex lens that collimates a light beam.

As described above, according to the present invention, a plurality of photodiodes that construct a ZB phase pattern are disposed in spaces adjacent to a plurality of photodiodes that construct a Z phase pattern of a photodiode array. With the difference between the Z phase output and the B phase output, the zero point is detected. Thus, until the zero point is detected, a zero point detecting signal that exceeds a reference voltage of a zero point detecting circuit can be prevented from being generated. Co nsequently, a comparison voltage of a comparing circuit that obtains the zero point signal can be fixed and variable resistors for adjusting the light amount and level can be omitted. In addition, the photodiodes of i -is- the Z phase and the photodiodes of the ZB phase can be integrally formed on a semiconductor chip that constructs a photodiode array that also serves for an index scale. As a result, the overall size of the encoder can be reduced.

Claims

1. An optical encoder having a photodiode array that serves both for a light detector and an index scale, comprising:

light emitting means for emitting a collimated light beam; a photodiode array having a plurality of photodiodes disposed opposite to said light emitting means at predetermined pitches and adapted for receiving the collimated light beam from said light emitting means and for serving for the index scale; a main scale disposed between said photodiode array and said light emitting means, said scale being relatively movable in the directions of an arrangement of the photodiodes and having slits formed at predetermined pitches; and signal processing means for processing an output signal of said photodiode array so as to obtain the amount of displacement, wherein:

said main scale has a first zero point detecting pattern in which a plurality of transmitting portions are nonuniformly formed; said photodiode array has a plurality of photodiodes of a first group that constructs a second zero point detecting pattern that is substantially the same as the first zero point detecting pattern; said photodiode array further has a plurality of photodiodes of a second group disposed in spaces and at outside of both edges of the photodiodes of the first group; and said signal processing means has zero point detecting means for obtaining the difference between all outputs of the photodiodes of the first group and all outputs of the photodiodes of the second group and for generating a zero point signal at a scale potion where the first zero point r detecting pattern overlaps with the second zero point detecting pattern.

2. The optical encoder according to claim 1, wherein:

the width of each of the transmitting portions that construct the first zero point detecting pattern is constant; the width of each of the photodiodes of the first group that construct the second zero point detecting pattern is substantially the same as the width of each of the transmitting portions; and the width of at least two photodiodes of the second group, each of the two photodiodes being placed at outside of each edges of the photodiodes of the first group, is larger than the width of each of the photodiodes of the first group.

3. The optical encoder according to claim 1, wherein:

a pitch al of the photodiode at the left edge of the second group is larger than a pitch a2 of the photodiode at the right edge of the first group; and a pitch bl of the photodiode at the right edge of the second group is larger than a pitch b2 of the photodiode at the left edge of the first group.

4. The optical encoder according to claim 1, wherein said zero point detecting means includes:

first current-voltage converting means for inputting output currents of the photodiodes of the first group and for converting the currents into a voltage value; second current-voltage converting means for inputting output currents of the photodiodes of the second group and for converting the currents into a voltage value; a differential circuit means for obtaining the difference between outputs of said first current-voltage converting means and said second current- voltage converting means; and comparing circuit means for comparing the output of said differential circuit means with a predetermined comparison voltage and for outputting the zero point signal.

5. The optical encoder according to claim 1, wherein said zero point detecting means includes:

a first parallel circuit having the photodiodes of the first group that are connected in parallel; a second parallel circuit having the photodiodes of the second group that are connected in parallel, said second parallel circuit being connected to said first parallel circuit in series; current-voltage converting means connected to a connecting node of said first parallel circuit and said second parallel circuit and adapted for converting the difference of output currents of said first parallel circui and said second parallel circuit into a voltage value; and comparison circuit means for comparing an output of said current-voltage converting means with a predetermined comparison voltage and for outputting the zero point signal c