GB2284954A - Self-biasing data bus driver - Google Patents

Abstract

In order to allow the transmission of low amplitude data signals on a bus 211 between a peripheral 111 and a central node 107 despite differences in earth potential, a bias level is sent to each peripheral along the bus 211 or another bus line (figure 3). The driver 243 filters 231, 229 the bus signal and uses it to bias the divided 217, 223 output signal 233. The bus may link a radiotelephone to peripherals within a car. <IMAGE>

Description

Data Bus Interface Apparatus Field of the Invention Generally, this invention relates to data bus drivers and more specifically to a self-biasing data bus driver circuit for a highspeed, low-amplitude digital data bus contained within a radiotelephone.

Background of the Invention Currently, in the field of radiotelephones, there is one technique of transmitting voice and data between the transceiver and the handset of a radiotelephone. This technique includes two individual busses, the first bus containing data signals, and the second bus containing audio or voice signals. This allows for a relatively low speed data signal bus which does not have an electromagnetic interference (EMI) or radio frequency interference (RFI) problem.

Today and in the future, as microprocessor communications within microprocessor based systems becomes faster, the radiotelephone is capable of integrating digital audio signals and the data signals onto one bus. This one bus allows for new developments in radiotelephone technology for adding peripherals, for example answering machines, fax machines, and modems, onto the one bus without separating the voice signals from the data signals prior to sending them to the transceiver. This reduces the number of wires necessary for the interconnection between the peripheral and the transceiver and allows for a common interface technique. However, this data bus must be capable of high speed data transition rates with minimal RFI and EMI radiation and a high tolerance to interference from other subsystems surrounding the radiotelephone.An automobile environment is a prime example of where interference between other subsystems is a great concern because of the close proximity to other systems such as engine control modules and electronically controlled suspension systems.

One way in which to reduce the amount of RFI and EMI radiation is to reduce the amplitude ofthe signal level on the data bus from 5 volts peak to peak (Vpp) to 0.5 Vpp. This reduction in the amplitude significantly reduces the amount of radiation but also produces several problems: first, the system becomes extremely sensitive EMI and RFI interference and second, it becomes sensitive to differences in the voltage potentials of the peripheral ground references. Other complications in designing a high speed data bus include: the distance between the transceiver and the peripheral device; the difference in supply voltage for the transceiver and the peripheral device; and the differing environmental conditions between the transceiver and the peripheral devices.First, the distance between the transceiver and the peripheral devices creates a need for the bus to extend this distance. This distance increases the opportunity for the bus to induce noise from other systems and for a change in the voltage potential of the ground. Second, the peripherals can be located in different environmental conditions, for example, the transceiver can be located in the trunk and the handset located inside the passenger compartment, the difference in temperature can severely effect the operation of some components and their voltage levels. Finally, the different power supplies for different devices increases the opportunity for deviations in the voltage potential of the ground.

Therefore, a need exists for a high speed digital data bus driver which transmits signals having an amplitude less than 0.5 volt and is immune to differences in environmental characteristics, power supplies, ground potential and signal levels.

Summary of the Invention According to the present invention there is provided a bus interface apparatus having a first end and a second end, the first end coupled to a data bus and the second end coupled to an output of a peripheral device, the output of the peripheral device generating a first data signal, the bus interface apparatus comprising: means for biasing the first data signal to a biased voltage level; means for adjusting the amplitude of the first biased data signal to a predetermined peak-to-peak voltage, the means for adjusting coupled to said means for biasing; and means, responsive to the first biased and adjusted data signal, for accessing the data bus, a first end of said means for accessing coupled to said means for adjusting and a second end of said means for accessing coupled to the data bus and transmitting the biased and adjusted data signal.

The present invention is a data bus interface driver which interfaces between one of a plurality of peripheral units and a data bus. The data bus interface driver is capable of accepting data signals having different amplitudes and is immune to differences in ground voltage potentials caused by induced noise and differing environmental conditions. The data bus interface driver is capable of data transition rates in excess of 1 MHz and has low EMI and RFI emissions.

An exemplary embodiment of the present invention will now be described with reference to the accompanying drawings.

Brief Description of the Drawings FIG.1 is a block diagram of a radio frequency data communication system.

FIG.2 is a schematic of a bus driver circuit in accordance with the present invention.

FIG.3 is schematic of an alternate bus driver circuit in accordance with the present invention Description of a Preferred Embodiment FIG. 1 is a radio frequency (RF) data communications system having a fixed site transceiver 101 and a mobile or portable transceiver 103. The mobile or portable transceiver 103 sends and receives RF signals from the fixed transceiver 101.

The RF signals are coupled by the antenna 105 and are demodulated and transformed into data signals by the transceiver 107. The transceiver 107 can send or receive the data signals to peripherals on a serial digital data bus 109. The peripherals in this example are a handset 111 and a fax machine 113, but other peripherals should not be excluded.

FIG. 2 reveals an exploded view of the digital data bus between the transceiver 107 and the peripheral handset 111.

Although only the transceiver 107 and the handset 111 are shown in FIG.2, the data bus can be used in a multi-peripheral configuration. The digital data bus 109 is shown as uplink 211 and downlink 203. These links allow for data transmission between the handset 111 and the transceiver 107. The data bus driver circuit 243 is common to all of the peripheral devices and serves two main purposes. First, the data bus driver circuit 243 is used to create a single voltage bias level for the data bus uplink 211, eliminating the varying references points from each individual peripheral device on the data bus by feeding the DC voltage level of the data bus signal on the uplink 211 into the data bus drive circuit 243. Second, it divides the voltage level of the data signal output from the bus interface chip (BIC) 207 down to the amplitude of the data signals used on the data bus 109. In the preferred embodiment, the amplitude of the voltage out of the chip is 5 Vpp and it is divided down to an amplitude of 0.5 Vpp, however, any other comparable voltage divider scheme may be employed in the present invention.

Since the data bus 109 uses small amplitude signals, the data bus 109 must be driven around the same reference point to insure proper priority control of the data bus 109. The priority scheme for attaining control of the data bus 109 is realized by the peripheral with the lowest Q2 base voltage potential forcing the base emitter junction of Q2 on all of the other peripherals to be reversed biased, therefore, preventing the other peripherals from driving the bus. The common bias point of all the peripherals is accomplished between with the feedback through the transistor Q1 227 and Q2 213. The circuit, including the resistor 231 and the capacitor 229 and the transistor Q1 227, removes the AC component of the data signal on the bus 211. At the ernitter of Q1 the common bias voltage ofthe bus uplink 211 is present.

This common bias voltage level is then used to bias Q2. As a result of this feedback operation, variances in components or ground levels or power supply potentials is eliminated with concern to this bus uplink 211 and also variances in the voltage signal levels of the data coming out of the bus interface chip 207.

The data signals output from the bus interface chip 207 on signal line 233 have an amplitude which varies from one peripheral device to another, in this example, the data signals output from the peripheral device has an amplitude between 0 to 5 volts. The resistor 217 and the resistor 223 provide a voltage divider network which reduces this amplitude down to a 0.5 Vpp about the bias voltage present at the emitter of Q1 227. Resistor 221 and capacitor 219 form a filtering mechanism for removing noise from the line. The inductor 215 also contributes as a filtering mechanism.

Once the peripheral device obtains control of the bus by pulling 233 to its lower state and holding it for a specified amount of time, it turns on the transistor Q2 213 and the data is driven out the uplink 211 to the transceiver 107. The voltage supply of the peripheral 225 can be different than the power supply of the transceiver 237. Regardless of the differences, the data bus will still have a common bias voltage. The original bias level is generated by the transceiver power supply 237 and the resistor 239. The on/offswitch 201, and the downlink 203 is switched on when a peripheral is first turned on. This grounds the downlink signifying to the transceiver 107 that a new peripheral device 111 has linked to the serial bus 109. The downlink is used to send a common clocking source from the transceiver 107 to all the peripheral devices.All the data signals driven out by a peripheral device 111 must have an effective duty cycle of approximately 50%. An effective duty cycle of 50% is defined as an average value of the data signal equal to 1/2 the voltage peak to peak.

This allows the bias point to stabilize at the middle of the transition levels, allowing for proper recovery of the data by the transceiver. If the output signal line 233 remains in a high or low state for a significant length of time, then the DC bias level at the emitter of Q1 227 will eventually adjust to the voltage level at which the data is held, causing errors in the data transmission.

This potential problem is solved by sending manchester encoded data which guarantees transitions in the data signal.

FIG. 3 is alternative embodiment to FIG. 2. The only significant change in this embodiment is that the master or the transceiver 107 determines the bias level at the output of the emitter Q1 315 to determine the bias level by referencing the bias level off the downlink 303 which comes from the master transceiver 107. The rest of the circuit contained here is identical to FIG.2.

There are two essential parts of this invention. First, the use of the DC voltage level of the data bus to bias the data signal output from the peripheral devices. This biasing eliminates the differences in environmental characteristics, power supplies, ground potential and signal levels of the individual peripheral devices from the data signals. Second, adjusting the amplitude of the signal output from the individual peripheral device to a common low amplitude signal. By adjusting this amplitude, there is a known voltage for prioritizing the bus access and lower EMI and RFI emissions.

Claims (6)

Claims

1. A bus interface apparatus having a first end and a second end, the first end coupled to a data bus and the second end coupled to an output of a peripheral device, the output ofthe peripheral device generating a first data signal, the bus interface apparatus comprising: means for biasing the first data signal to a biased voltage level; means for adjusting the amplitude of the first biased data signal to a predetermined peak-to-peak voltage, the means for adjusting coupled to said means for biasing; and means, responsive to the first biased and adjusted data signal, for accessing the data bus, a first end of said means for accessing coupled to said means for adjusting and a second end of said means for accessing coupled to the data bus and transmitting the biased and adjusted data signal.

2. A bus interface apparatus in accordance with claim 1, wherein said means for biasing further comprises: a first transistor having a base, an emitter and a collector, said collector coupled to a first voltage level and said emitter coupled to a second voltage level; a second capacitor having a first end and a second end, said second end coupled to said second voltage level; and a first resistor having a first end and a second end, said first end coupled to the data bus, said second end coupled to said first end of said second capacitor and said base of said first transistor.

3. A bus interface apparatus in accordance with claim 1 or 2, wherein said means for adjusting further comprises: a third resistor having a first end and a second end, said first end coupled to said means for filtering; and a fourth resistor having a first end and a second end, said first end coupled to said second end of said third resistor and said second end coupled to the at least one output of the first peripheral device.

4. A bus interface apparatus in accordance with claim 1,2 or 3, wherein said means for accessing further comprises a second transistor having a base, a collector and an emitter, said base coupled to said first end of said means for adjusting, said collector coupled to a second voltage level, said emitter coupled to the data bus.

5. A bus interface apparatus in accordance with any preceding claim, wherein said first transistor is a NPN transistor.

6. A bus interface apparatus in accordance with any preceding claim, wherein said second transistor is a PNP transistor.