GB2283846A

GB2283846A - Arrangement for interfacing a keyboard with a microprocessor

Info

Publication number: GB2283846A
Application number: GB9422696A
Authority: GB
Inventors: Ian Murray Garth
Original assignee: Alcatel Australia Ltd
Current assignee: Nokia Services Ltd
Priority date: 1993-11-11
Filing date: 1994-11-10
Publication date: 1995-05-17
Anticipated expiration: 2014-11-10
Also published as: GB2283846B; HK1000493A1; GB9422696D0

Abstract

An arrangement for interfacing a keyboard comprising an array of keys operatively associated with a matrix of rows (11 - 15) and columns (6 - 10) of conductive elements with control line terminals (P1 - P5) of a microprocessor (16) programmed to decode key operations from signal conditions applied to the control line terminals. Each row is connected to a respective control line terminal via a diode (D1 - D5) and each column is connected to a respective control line terminal. Pull-up resistors (R17 - R21) couple a voltage source to the columns. Upon operation of a key (22) a current path is established via an associated diode (D4) to a control line terminal (P2) rendered LOW by a scanning cycle routine of the microprocessor. The forward bias current of the diode causes another control line terminal (P4) to be pulled LOW. The microprocessor decodes the state of the two charged control line terminals and identifies the operated key in a known manner. The arrangement permits a reduction in the number of control lines required for a given number of keys. <IMAGE>

Description

ARRANGEMENT FOR INTERFACING A KEYBOARD WITH A MICROPROCESSOR This invention relates to keyboards, and in particular, to an arrangement for interfacing keyboards elements with control lines of a microprocessor or microcontroller for decoding and identifying a particular key operation. Conventional keyboards comprise a matrix of rows and columns of conductive tracks whose respective intersections are electrically contacted by manual operation of a pushbutton of an array of operatively associated pushbutton keys.

Conventionally, to identify which push-button has been operated, each of the rows of the matrix is connected to a respective output pin of a microprocessor, and each of the columns of the matrix is connected to a respective input pin of the microprocessor, the distal ends of the columns being respectively connected to pull-up resistors. The microprocessor is programmed to cause a LOW condition to sequentially appear across the output pins, one pin at a time, sometimes known as scanning". When an operated key connects a row to a column the corresponding input pin is pulled LOW. This combination of LOW's on particular input and output pins is decoded by the microprocessor to identify the operated key.

The availability of pins on a microprocessor is fixed and typically a large proportion of the available pins is dedicated to scanning an associated keyboard. As a result there is only a limited number of pins remaining for controlling other associated devices. On the other hand, the pin requirements for a matrix of rows and columns limits the number of keys that can be decoded by a conventional microprocessor.

The present invention seeks to provide an arrangement for interfacing keyboard elements with control pins of a microprocessor using fewer pins than known arrangements.

According to the invention, there is provided an arrangement for interfacing a keyboard comprising an array of keys operatively associated with a matrix of rows and columns of conductive elements with control line terminals of a processor means programmed to decode and identify key operation from signal conditions applied to said terminals, intersections of predetermined rows and columns being selectively contacted by manual operation of said keys, wherein one end of each column is coupled to a DC voltage source via respective resistor means and the other end of each column is connected to respective control line terminals rendered into a high impedance state by said DC voltage source, each row being coupled to said control line terminals via respective serially connected diode means the polarity of which being such that a respective diode means is rendered forward biased by said DC voltage source upon a current path being established between said DC voltage source and a control line terminal connected to a column that is connected to said forward biased diode means by operation of a selected key when that control line terminal is pulled into a low impedance state by a scanning means included in said processor means, said scanning means periodically and at a predetermined rate pulling each said terminal in turn into the low impedance state.

In order that the invention and its various other preferred features may be understood more easily, some embodiments thereof will now be described, by way of example only with reference to the accompanying drawings, in which: Figure 1 shows an arrangement known to us for interfacing a keyboard matrix with control line pins of a microprocessor.

Figure 2 shows an arrangement for interfacing a keyboard matrix with control line pins of a microprocessor, constructed in accordance with the invention.

Figure 3 shows another arrangement for interfacing a keyboard matrix with control line pins of a microprocessor, constructed in accordance with the invention.

Referring to Figure 1, this arrangement comprises a matrix 1 of rows 2 and columns 3 of conductive tracks on a substrate (not shown). At each intersection of the rows and columns a push-button key is arranged, all keys forming an array operatively associated with the matrix. Each column is coupled at one end to a positive voltage rail +ve via respective pull-up resistors R1, R2, R3, and R4. The other ends of the rows are respectively connected to give output pins X1, X2, X3, X4, and X5 of microprocessor 5. One end of each column is connected to respective input pins Y1, Y2, Y3 and Y4 of the microprocessor.

In operation, upon actuation, for example, of push-button key 4a, when the microprocessors scanning cycle renders the condition on output pin X1 momentarily LOW input pin Y1 is pulled LOW thereby providing a combination of conditions which can be decoded by the microprocessor in a known manner to identify the key operated.

In this known arrangement, if a total of n input/output pins is available, the maximum number of keys that can be decoded by the microprocessor is: nxn if n is even 4 (anti) x (n-1) if if n is odd.

4 Referring to Figure 2, the arrangement comprises a matrix of five columns 6,7,8,9 and 10, and five rows 11,12,13,14 and 15 of conductive tracks on a substrate (not shown). One end of each of the rows is respectively connected to I/O pins P1, P2, P3, P4 of microprocessor 16 via respective diodes D1, D2, D3, D4 and D5. One end of each column is connected to a positive voltage rail +V via respective pull-up resistors R17, R18, R19, R20 and R21. The other end of each column is connected to respective control line pins P1 - P5 which are capable of being configured as either inputs or outputs. An array of twenty keys is operatively associated with intersections of the rows and columns. Those intersections having a common control line pin, for example, the intersection of row 11 and column 6, are not associated with a key.

In operation, a scanning cycle produced in a known manner by the microprocessor's software causes each of the control lines P1 - P5 to be configured, one line at a time at a predetermined rate, as an output and rendering it into a LOW impedance, the remaining control lines being rendered into a HIGH state by the positive voltage connected to them via the pull-up resistors.

Current from positive voltage rail + ve "sinks into each control line as it is configured as an output by the scanning cycle; this current flows via a pull-up resistor and the column connected to the control line configured as an output.

Upon operation of key 22, current flows from + ve, R18, column 7, the junction of pin P4 and diode D4, the anode of diode D4, which is forward biased1 the contacted intersection of column 6 and row 14, contacted by the operation of key 22, the junction of P2 and the anode of diode D2. The current "sinks" into the low impedance output configuration at control line pin P2 when that control line is configured as an output by the scanning cycle. A voltage, typically 0.7V, produced at the anode of forward biased diode D4 is extended to control line pin P4 pulling that control line LOW. The resulting LOW states of control lines P2 and P4 is decoded by the microprocessors software in a known manner to identify the operation of key 22. Operation of other keys are decoded and identified in a similar way and will not be described.

Using the arrangement of the present invention, if n is the number of control line pins available, then the maximum number of keys that can be decoded and identified is: n x (n - 1 ).

Referring to Figure 3, rows 11 to 13 are coupled to an interrupt pin INT of the microprocessor, programmed to remain in an idle mode until interrupted, via respective diodes D6, D7, D8, D9 and D10. The interrupt pin is held HIGH by a voltage coupled thereto via pull-up resister R22 until any key is operated whereupon the interrupt key is pulled LOW causing the microprocessor to scan the control lines for a predetermined number of cycles. This embodiment has the advantage that the microprocessor does not scan the control lines continuously and thereby reduces power consumption and processing workload.

While the present invention has been described with regard to many particulars it is understood that equivalents may be readily substituted without departing from the scope of the invention.

Claims

CLAIMS:

1. An arrangement for interfacing a keyboard comprising an array of keys operatively associated with a matrix of rows and columns of conductive elements with control line terminals of a processor means programmed to decode and identify key operation from signal conditions applied to said terminals, intersections of predetermined rows and columns being selectively contacted by manual operation of said keys, wherein one end of each column is coupled to a DC voltage source via respective resistor means and the other end of each column is connected to respective control line terminals rendered into a high impedance state by said DC voltage source, each row being coupled to said control line terminals via respective serially connected diode means the polarity of which being such that a respective diode means is rendered forward biased by said DC voltage source upon a current path being established between said DC voltage source and a control line terminal connected to a column that is connected to said forward biased diode means by operation of a selected key when that control line terminal is pulled into a low impedance state by a scanning means included in said processor means, said scanning means periodically and at a predetermined rate pulling each said terminal in turn into the low impedance state.

2. An arrangement substantially as described herein with reference to Figure 3 of the drawings.

2. An arrangement as claimed in claim 2, wherein said processor includes an interrupt routing arranged such that the source scanning means is initiated upon the operation of any key.

3. An arrangement substantially as described herein with reference to Figure 2 of the drawings.

4. An arrangement substantially as described herein with reference to Figure 3 of the drawings.

Amendments to the claims have been filed as follows An arrangement for interfacing a keyboard comprising an array of keys operatively associated with a matrix of rows and columns of conductive e elements with control line terminals cf a processor means cramme to decode and identify key operation from signal conditions applied to said terminals, intersections of predetermined rows and columns being selectively contacted by manual operation of said keys, wherein one ena or each column is coupled to a DC voltage source via respective resistor means and the other end of each column is connected to respective control ine terminals which may be rendered into either a high impedance input state or a low output state by said processor means, each row b eing coupled to saic control line terminals via respective serially connected first diode means the polarity of which being such that a respective first diode means is rendered forward biased b said DC voltage source upon a current path being established between said DC voltage source and a control line terminal connected to a column that is connected to said forward biased first diode means by operation of a selected key when that control line terminal is pulled into a low output state by a scanning means included in said processor means, said scanning means pernodically an at a predetermined rate pullIng each said terminal in turn into the low output state, while all other said terminals are placed into a high impedance input state, and wherein said processor means includes an interrupt routine whose control line terminal is coupled to respective said rows via respective second diode means such that said scanning means is initiated upon the operation of any said key.