GB2283119A

GB2283119A - Sorting apparatus with buffer storage

Info

Publication number: GB2283119A
Application number: GB9423782A
Authority: GB
Inventors: Yasunori Kasahara
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1993-02-15
Filing date: 1994-02-07
Publication date: 1995-04-26
Anticipated expiration: 2014-02-07
Also published as: GB9423782D0; GB2283118A; GB2283118B; GB9423781D0; GB2283119B

Description

--i - 2283119 SORTING APPARATUS This invention relates to an apparatus for

sorting a large quantity of data at high speed, and more particularly to an apparatus for continuously sorting a large quantity of data with sort-dedicated processors connected in a pipeline fashion.

A sorting apparatus is currently known in which a number of sort processors are connected in a pipeline fashion to sort a large quantity of data at high speed. In the conventional sorting apparatus shown in FIG. 4 of the accompanying drawings, a device in which two sort cores are contained in a package (i.e., doublestage sort processor) is used. An alternative device in which one sort core is contained in a single package (i.e., a singlestage processor) may be used for the same operation.

As shown in FIG. 4, firstly data to be sorted from an input/output path 1 is inputted in series. One item of data Inputted to a sort processor 6 via the input/output it 1 a path I is then stored in a front end internal storage 4 corresponding to a front end sort core portion 2 in the sort processor 6.

Vilien another item of data is inputted from the input/output path 1, the front end sort core portion 2 merge-sorts one item of such newly inputted data and the data stored in the front end internal storage 4 as mentioned above, and outputs the sorted output string. Namely, this output string contains two Items of data. Thus the front end sort core portion 2 outputs successively the sorted strings each containing two items of data. The storage situated at an each end is called a local memory.

The output string containing these two items of data is then supplied to the back end sort core portion 3. The back end sort core portion 3 stores the string, which is to be outputted from the front end sort core portion 2, firstly in the back end internal storage 5 corresponding to the back end sort core portion 3. When another output string is outputted from the front end sort core portion 2, the stored string and the new string inputted to the back end sort core portion 3 are merge-sorted, and an A output string containing four items of (sorted) data is outputted.

Thus the back end sort core portion 3 merge-sorts two strings, i.e. those containing two items of data, which are to be outputted from the front sort core portion 2, and outputs successively an output string containing four items of data. As shown in FIG. 9, the back end internal storage 5 has a capacity two times larger than that of the front end internal storage 4. This is because the back end internal storage 5 is required to have a larger capacity in order that the back end sort core portion 3 can deal with longer strings, compared to the front end sort core portion 2.

FIG. 5 is a timing chart showing the access timing for the front end and back end internal storages (local memories) 4, 5 in the conventional sorting apparatus.

In either the front end or the back end sort core portion 2, 3. sorting by 2-way merging takes place so that the strings each containing two items of sorted data are outputted successively in the J-th front end (or back end) sort core portion 2 ( or 3).

In the conventional art, two connected sort core a portions, i.e. front end and back end sort core portions 2, 3, are stored in a single sort processor 6. A number of sort processors 6 are connected in series to form a pipeline. In FIG. 4, a nineteen-step pipeline is shown. In order to constitute the nineteen-step pipeline, as shown in FIG. 4 and 6, ten sort processors are used, and the front end sort core portion 2 of the first sort processor 6 is not used.

According to the conventional arrangement of FIG. 4, on the back side of the back end sort core portion 3 of the fourth sort processor 6, external memories 7, 8, 9 are situated outside the sort processor 6 as local memories. This is because as merge-sort is repeated, the string will become progressively longer towards the last sort processor so that the front end and back end internal storage 4, 5 situated in the sort processor 6 will not suffice.

Generally, for the front end and back end internal storages 4, 5 in the sort processor 6, high speed SRAMs are often used. For the external memories 7, 8, 9, whose capacity is large, it is more usual to use DRAMs.

In FIG. 5, of the storage, thb portion to be used as a a local memory is indicated by hatching. Specifically, at the step in which the external.memories 7, 8, 9 are to be used as a local memory, none of the front end or back end internal storages 4, 5 are used at all. This is because it is difficult to make addresses continuous between the internal and external memories.

In the conventional art of FIG. 5, ten sort processors 6 are used, and nineteen sort core portions ar connected in a pipeline fashion. Therefore the result of si.-ting 2-3-0 items of data can be obtained as the final Citput.

With this conventional arrangement, at the step in ih ich the external memories are used as a local memory, n-ne of the front end or back end internal storages 4, 5 are used. Also at the step in which only the front end and back end internal storages 4, 5 are used, the local memory requires a different capacity for every step so that an unused portion will inevitably be created.

As shown in FIG. 5, for example, in the first sort processor 6-1 including the first and second sort core portions 2, 3. such an unused portion is larger than in the second sort processor 6-2 including the third and e d1K 6 fourth sort core portions 2, 3. This problem can be avoided by using a dedicated processor for every step, but it would result in a massive increase in production costs.

In the conventional sorting apparatus, since all the sort processors constitute a pipeline, operations at the individual steps must take place in synchronism. Consequently, it has been customary to supply a common clock signal to the sort core portions at the individual steps; this clock signal must be set so as to be usable by the lowest speed component in the system. In this conventional art, since the step in which DRAM situated outside as a local memory is used will become slowest,;he entire operating speed will be adjusted to the operatin., speed at the-stage whose local memory's access speed is the slowest. This is because generally an external DRAM has a slower access speed than the internal SRAM.

Further, when a fault occurs in a local memory, it is necessary to stop operation of the sorting apparatus and to specify the location of the fault, whereupon the faulty part must be changed with a new one. As a result, it used to take rather a long time for the apparatus to recover from the faulty condition.

a 4 h.

With the foregoing problems in mind, the objective of this invention is to provide a sorting apparatus which enables downsizing.

Another objective of the invention is to provide 5 sorting apparatus which enables high speed operation.

Still another objective of the invention is to provide a sorting apparatus which can improve RAS for the entire apparatus.

According to the present invention, there is provided a sorting apparatus equipped with a number of sort processors, wherein each of the sort processors comprises: a local memory for storing the first output string, which is to be output from the preceding sort processor, as the first data string, the local memory including a low speed portion whose access speed is slow, and a high speed portion whose access speed is fast; a sort core unit for merge sorting the second output string, which is to be output from the preceding sort processor next to the first output string, and the first data string stored in the local memory and for outputting the merge sort result to the succeeding sort processor; and the sort core unit including transfer means for, when reading of the first data string from the high speed portion of the local memory is started, transferring data from the low speed portion to an address in the high speed portion from which the data has been read, and access adjusting means for, when data from the low speed portion is read, returning the data, which is transferred by the transfer means, to the sort core unit at high speed.

With the invention, since the high speed portion of the local memory acts as a buffer storage for the low speed portion, it is possible to improve the access speed - a - to the low speed portion remarkably.

Thus, since the high speed portion is used as a high speed buffer storage, it is possible to reduce the access time to the low speed portion whose access time is long. An a result, it in possible to realize a sorting apparatus which in inexpensive to manufacture and enables improved performance.

The invention will be further described by way of non-limitative example, with reference to the accompanying drawings, in which:- Figure 1 is a block diagram showing one of the sort processors to be used in a sorting apparatus according to an embodiment of the invention; Figure 2 in a diagram showing the data transfer between an internal storage and an external memory in the sorting apparatus of Figure 1; Figure 3 is a timing diagram showing the operation of the sorting apparatus of Figure 1; Figure 4 is a block diagram showing a conventional sorting apparatus; Figure 5 is a timing diagram showing the memory access of the conventional sorting apparatus; and Figure 6 is a block diagram showing another conventional double-sorting apparatus.

A preferred embodiment of this invention will now be described with reference to the accompanying drawings.

Figure 1 is a block diagram showing one of the sort processors 106 to be used in a sorting apparatus according to the embodiment. As shown in Figure 1, according to the sort processor 106 of the embodiment, switching signals output from the sort core portion 102 as local memory address signals are supplied to the front end internal storage 104 via an internal bug 110 and to the external memory via an external bus 120, respectively.

The data read from the front end internal storage 104 is input to the front end sort core portion 102 via an internal read bus 115. In this embodiment, for data writing, a block pointer, which indicates the next address, is stored in the local memory, together with the data.

is A feature of this embodiment is that the front and back end internal storages 104,105 are used as a highspeed buffer storage.

j 0 In merge sort, addresses are continuously accessed. Therefore, the data stored in the external memory 107 can be read after it has been read from the front end or back end internal storage 104, 105. In this embodiment, with a view to this point, every time data is read from the front end internal storage 104, data from the external memory 107 will be transferred to the front internal storage 104. When access is made to the external memory 107, the data transferred to the front end internal storage 104 will be read.

FIG. 2 is a diagram showing the access timing in the case where the front end internal storage 104 is used as a high-speed buffer storage. In FIG. 2, the boxes shown on the left side indicate the front end internal storages 104 serving as high-speed buffer storages, while the boxes shown on the right side indicate the external memories 107.

The operation of the sorting apparatus of the embodiment will now be described in detail.

FIG. 2 shows the block transfer of data between the a 1 1L 11 front end internal storage 104 and the external memory 107 as mentioned above. In the example of operation shown in FIG. 2, a string A is stored in the external memory 107, and it will then be read before the next string B is stored there. In FIG. 2, time lapses vertically, i.e., from (1) toward (6).

At (2) of FIG. 2, the front end or back end sort core portion 102, 103 reads one block of data from the front end internal storage 104. Then at (3), one block of d-ta is transferred from the external memory 107 to the f ont end internal storage 104. Since the block of data r ad at (2) v-ill not read again, another block data read f-,)m the extcrnal memory 107 will be stored if one block oi data has been read from the front end internal storage 101.

According to this embodiment, in the sorting apparatus In which the highspeed front end internal storage 104 and the low-speed external memory 107 are used as local memories, It is possible to make the access time to the external memory 107 considerably short by previously transferring the data of the external memory 107 to the front end internal storage 104 every time the a data is read from the external memory 107. Figure 3 is a timing diagram showing the operation of the sorting apparatus of this embodiment.

In the embodiment, either the front end internal storage 104 or the external memory is used as a local memory. Alternatively, only the external memory 107 may be used as a local memory. Namely, in this alternative case, since the front end internal storage 104 Is unused, not only effective use of hardware but also improved performance can be achieved by using the entire front end internal storage 104 as a high-speed buffer storage for the external memory 107.

Attention is directed to Application No 94 02281.1 (Publication No 2 275 122) from which this application is divided and which claims other sorting apparatus, including apparatus having the features cla--ned herein combined with other features. Attention in alsc directed to Application No 94 (Publication NO) which is also divided from Application Lo 94 02281.1 and which claims other sorting apparatus.

1 C L A 1 M S 1. A sorting apparatus equipped with a number of sort processors wherein each of said sort processors comprises:

(a) a local memory for storing a first output string, which is to be output from the preceding sort processor, as a first data string, said local memory including a low speed portion whose access speed is slow, and a high speed portion whose access speed is quick; (b) a sort core unit for merge sorting a second output string, which is to be output from said preceding sort processor next to the first output string, and the first data string stored in said local memory and for outputting the merge sort result to the succeeding sort 15 processor; and (c) said sorting core unit including (i) transfer means for, when reading of the first data string from said high speed portion of said local memory is started, transferring data from said low speed portion to an address in said high speed portion from which data has been read, and (ii) access adjusting means for, when data from said low speed portion is read, returning the data, which is transferred by said transfer means, to said sort core unit at high speed.

2. A sorting apparatus according to claim 1, and constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in Figures 1 to 3 of the accompanying drawings.