GB2281474A - A method and circuit for maintaining saturation of a field effect line switch of a telephone subset - Google Patents

Abstract

A method of and circuit for maintaining a telephone subsets' field-effect transistor line switch (TR1) saturated during initial line seizure period when the voltage drop across the subsets' line terminals (L1, L2) is momentarily reduced in order to provide sufficient current to seize exchange equipment. The circuit comprises a voltage source (V1) a capacitor (C1) and a switch (TR3) which apply a voltage which exceeds the pinch-off voltage of the field effect transistor line switch during the line seizure period generated by the line seizure circuit. <IMAGE>

Description

A METHOD AND CIRCUIT FOR MAINTAINING SATURATION OF A FIELD EFFECT LINE SWITCH OF A TELEPHONE SUBSET This invention relates to telephone subsets and more particularly to telephone subsets incorporating a line seizure circuit with a field effect transistor line switch which is required to be saturated during an initial line seizure period.

A telephone subset is connected to an exchange via an exchange line whose resistance relates to its length and therefore cannot be predetermined. Further, the DC characteristics of various types of telephone subsets may differ.

When a telephone subset that is connected to an exchange line is initially brought into the off-hook mode and its line switch completes a DC loop to seize exchange equipment via the exchange line, sufficient current must flow in the loop to overcome inertia and positively operate electromagnetic relays in line equipment at the exchange.

In order to ensure such operation under all normal line and subset DC characteristics, the subsets must comply with a so called "Line Seizure Condition" specification whereby during line seizure, for a minimum duration of 0.3s the DC characteristics must fall within predetermined values of voltage and current.

In order to comply with the aforementioned "Line Seizure Condition" telephone subsets may incorporate a line seizure circuit, which, in effect, momentarily switch into the subsets circuit a shunt circuit, which is located between the subsets' line switch and speech circuit, to momentarily reduce the voltage drop across the subsets' line terminals so that at least a predetermined minimum value of current flows in the loop.

For some time, processor controlled semiconductor line switches of the bipolar type have been used in some telephone subsets.

A disadvantage of semiconductor line switches of the bipolar type is that current is required to control such a line switch. This current is subtracted from a current supply used to drive other circuit elements of the subset.

Although the current requirement can be greatly reduced by utilising a Darlington configuration, such a configuration introduces a further problem of excessive voltage drop across the line switch.

To avoid these disadvantages, the bipolar transistor line switch may be replaced by a field-effect transistor (FET) line switch, as FETs require no control (gate) current and therefore more current is available from the subsets' supply to drive the other circuit elements, and introduces minimal voltage drop.

For the subset to function correctly, however, the FET must be saturated, i.e. Vgs must exceed the transistor manufacturers specified vp (pinch-off voltage) typically 4 volts. To maintain Vgs greater than vp the subsets line terminal voltage must exceed the vp plus any series voltage drops between the line terminals and the source terminal of the FET, such as the polarity guard diodes In a subset incorporating a FET line switch and a line seizure circuit a problem arises in that during the momentary operation of the line seizure circuit whereby the voltage drop across the subsets' line terminals is reduced by the shunt circuit, this reduced voltage may be of a magnitude which is less than Vgs plus any series voltage drops and the FET line switch is no longer saturated.

It is an object of the present invention to provide a method of maintaining FET line switch saturation during the period of line seizure.

According to the invention there is provided in a telephone subset comprising line terminal means, a controllable line-switch means in the form of a field-effect transistor means a control element of which is coupled to a first signal output of a processor means, a hook-switch means coupled to an input of said processor means, and a controllable line seizure shunt means having a control means coupled to a second signal output of said processor means for applying a line seizure circuit across said line terminal means for a predetermined period upon generation of a second signal at said second signal output when the subset is brought into an off-hook mode upon operation of said hook-switch means, said line seizure circuit including said shunt means and said field-effect transistor means conductive path, a method of maintaining said field-effect transistor means in a saturated mode during the application of said line seizure circuit, said method comprising the steps of: a) Provide a storage capacitor means one plate of which is coupled to a DC voltage source of a predetermined magnitude and of a first polarity, whereby a corresponding voltage of said first polarity appears on said one plate, and the other plate of which is coupled to said control element of said field-effect transistor means and having zero voltage appearing thereon; b) Provide a first controllable semiconductor switch means a control element of which is coupled to said second signal output of said processor means and a switching path of which couples said one plate of said storage capacitor means to a zero voltage point with reference to said DC voltage source; whereby upon generation of said second signal by said processor means the said first controllable semiconductor switch means is rendered conducting thereby pulling said corresponding voltage on said one plate to zero voltage and driving said other plate to said corresponding voltage of the opposite polarity, said corresponding voltage being of such a magnitude that the voltage applied to said control element of the field-effect transistor means exceeds said field-effect transistor means pinch-off voltage thereby maintaining said saturation mode.

In order that the invention may be readily carried into effect, an embodiment thereof will now be described, by way of example only, with reference to the accompanying drawing the single figure of which shows a schematic circuit of part of a telephone subset incorporating an arrangement for maintaining line switch saturation constructed in accordance with the present invention.

Referring to the drawing, the circuit comprises subset line terminals L1 and L2, polarity guard diodes D1 and D2, serially connected to the source (S) element of a P channel enhancement-mode type MOSFET. TR1 whose drain (D) element is coupled to the subsets speech IC (not shown), MOSFET TR1 forming the subsets line-switch. Across the source and gate elements of MOSFET TR1 are connected a resistor R1 and a voltage protection zener diode D3. Gate element G is connected via a resistor R2 to the switching path of a semiconductor switch TR2 whose control element is coupled via a resistor R3 to an off-hook signal output of the subsets processor (not shown) . A boost circuit comprising capacitor C1, having an "a" plate and a "b" plate, resistor R4, voltage source V1, typically 4.0 volts, and the switching path of a semiconductor switch TR3 is coupled to the switching path of semiconductor switch TR2.

The control element of semiconductor switch TR3 is connected via resistor R5, to the "DC characteristic" signal output of the subsets processor. Connected between the drain element D of MOSFET TR1 and line terminal L2 is a known line seizure circuit comprising a switchable shunt arrangement (not shown) controlled by the "DC characteristic" signal generated by the subsets processor In operation upon the subset going off-hook, the processor senses an offhook mode, whereupon it extends a "decadic pulse" (DP) signal to the control element of semiconductor switch TR2 which is rendered conducting, thereby operating MOSFET TR1.At the same time the processor extends a "DC characteristic" signal to a control input of the line seizure circuit as well as to the control element of semiconductor switch TR3 for a period of 0.3s. The shunt circuit (not shown) in the line seizure circuit is connected across the drain element D of MOSFET TR1 and line terminal L2 lowering the voltage drop across the line terminals to create the line seizure condition and at the same time semiconductor switch TR3 is rendered conducting whereupon a positive 4 volt charge on plate "b" of capacitor C1 is dragged to 0 volts thereby forcing plate "a" of capacitor C1 to negative 4 volts charge.This negative 4 volts is extended via conducting semiconductor switch TR2 and resister R2 to the gate (g) of MOSFET TRl thereby providing the required Vgs to maintain saturation of the MOSFET.

After 0.3s the "DC characteristic" signal is removed by the processor and the shunt circuit in the line seizure circuit is removed causing the voltage drop across line terminals L1 and L2 to rise. Also semiconductor switch TR3 is turned off causing plate "b" of capacitor C1 to recharge to positive 4 volts.

It will be understood that an N channel enhancement-mode type MOSFET could be adapted with obvious modifications to the circuit.

Some subsets may include a circuit, sometimes called a "cold start" circuit, that upon operation of the hookswitch determines whether the subset's processor is in an un-powered state, such as, for example, when it is initially connected; and if it is determined that the processor is in the un-powered state, the "cold start" circuit thereupon provides sufficient current from the exchange line to powerup the processor. Such a circuit is disclosed in Australian Patent Application No. 21322/92.

During such a "cold start" it is preferable that the application of the line seizure circuit be delayed for a predetermined period (typically 150 ms) to allow the large storage capacitor connected across the processor's power terminals to fully charge so that when the line seizure circuit is applied and current shunted away from the processors power terminals, the charge on the capacitor can reliably maintain the processor powered-up during the line seizure period.

The line seizure delay is accomplished in a known manner by the processor's software. Upon operation of the hook switch, the processor can detect whether it requires a "cold start" by comparing bytes in its non-volatile ROM with bytes in its volatile RAM. A disparity between these bytes will indicate that the processor is in an un-powered state and thus a "cold start" is required, and as a consequence, line seizure delay is required. The processor then delays the application of the "DC characteristic" signal for a predetermined time.

Claims (8)

CLAIMS:

1. In a telephone subset comprising line terminal means, a controllable lineswitch means in the form of a field-effect transistor means a control element of which is coupled to a first signal output of a processor means, a hook-switch means coupled to an input of the processor means, and a controllable line seizure shunt means having a control means coupled to a second signal output of the processor means for applying a line seizure circuit across the line terminal means for a predetermined period upon generation of a second signal at the second signal output when the subset is brought into an off-hook mode upon operation of the hook-switch means, the line seizure circuit including the shunt means and the field-effect transistor means conductive path, a method of maintaining the fieldeffect transistor means in a saturated mode during the application of the line seizure circuit, the method comprising the steps of: a) Providing a storage capacitor means one plate of which is coupled to a DC voltage source of a predetermined magnitude and of a first polarity, whereby a corresponding voltage of the first polarity appears on said one plate, and the other plate of which is coupled to the control element of the field-effect transistor means and having zero voltage appearing thereon, b) Providing a first controllable semiconductor switch means a control element of which is coupled to the second signal output of the processor means and a switching path of which couples said one plate of the storage capacitor means to a zero voltage point with reference to the Dc voltage source, whereby upon generation of said second signal by the processor means the first controllable semiconductor switch means is rendered conducting thereby pulling said corresponding voltage on said one plate to zero voltage and driving said other plate to said corresponding voltage of the opposite polarity, said corresponding voltage being of such a magnitude and polarity that the voltage applied to the control element of the field-effect transistor means exceeds the field-effect transistor means pinch-off voltage thereby maintaining the saturation mode.

2. A telephone subset comprising line terminal means, a controllable lineswitch means in the form of a field-effect transistor means a control element of which is coupled to a first signal output of a processor means, a hook-switch means coupled to an input of the processor means, and a controllable line seizure shunt means having a control means coupled to a second signal output of the processor means for applying a line seizure circuit across the line terminal means for a predetermined period upon generation of a second signal at said second signal output when the subset is brought into an off-hook mode upon operation of the hook-switch means, the line seizure circuit including the shunt means and the field-effect transistor means in a saturated mode during the application of the line seizure circuit, wherein the subset further includes saturation means for maintaining the field-effect transistor means in a saturated mode during the application of the line seizure circuit, the saturation means comprising a storage capacitor means one plate of which is coupled to a DC voltage source of a predetermined magnitude and of a first polarity, whereby a corresponding voltage of said first polarity appears on said one plate, and the other plate of which is coupled to the control element of the field-effect transistor means and having zero voltage appearing thereon, a first controllable semiconductor switch means a control element of which is coupled to said second signal output of the processor means and a switching path of which couples said one plate of the storage capacitor means to a zero voltage point with reference to the DC voltage source, whereby upon generation of the record signal by the processor means the first controllable semiconductor switch means is rendered conducing thereby pulling said corresponding voltage on said one plate to zero voltage and driving said other plate to said corresponding voltage of the opposite polarity, said corresponding voltage being of such a magnitude and polarity that the voltage applied to the control element of the field-effect transistor means exceeds the field-effect transistor means pinch-off voltage thereby maintaining the saturation mode.

3. A telephone subset as claimed in claim 2, wherein a diode means is connected between said other plate of the storage capacitor means and said switching path of the first controllable semiconductor, the diode being reverse biased by said corresponding voltage of the opposite polarity.

4. A telephone subset as claimed in claim 2 or 3, wherein the control element of the field-effect transistor means is coupled to said other plate of the storage capacitor means via a switching path of a second controllable semiconductor switch means a control element of which is coupled to said first signal output of the processor.

5. A telephone subset as claimed in any one of claims 2-4, wherein the field-effect transistor means is a P channel enhancement-mode type.

6. A telephone subset as claimed in any one of claims 2-5, including delay means arranged to delay the application of the line seizure circuit across the line terminal means when the processor means is being powered-up after detection of an un-powered state.

7. A telephone subset substantially as herein described will reference to the drawing.

8. A method of maintaining a field effect transistor means in a saturated mode during the application of the line seizure circuit in a telephone subset the method being substantially as described herein.