GB2281462A

GB2281462A - Output driver responsive to earthed or high-side sensor switches

Info

Publication number: GB2281462A
Application number: GB9416454A
Authority: GB
Inventors: Thomas Hirth; Ulrich Thelen
Original assignee: Daimler Benz AG
Current assignee: Daimler Benz AG
Priority date: 1993-08-19
Filing date: 1994-08-15
Publication date: 1995-03-01
Anticipated expiration: 2014-08-15
Also published as: IT1272789B; ITRM940536A1; DE4327867C1; FR2709212A1; GB9416454D0; ITRM940536A0; FR2709212B1; GB2281462B

Description

?_r 1 2281462 A device for the switching drive of an electronic unit The

invention relates to a device for the switching drive of an electronic unit, having at least one switching input, means for applying interrogating current to at least one switch, which can be connected to the at least one switching input, and having comparing means for comparing a signal level, occurring due to said interrogating current along the switching path, with a reference value, and having at least one switching output from which the electronic unit can be driven as a function of the result of comparison, and it being the case that the at least one switching input can be connected via the switching path of the at least one switch at least indirectly to a potential close or equal to the potential of one of the two supply voltage terminals of the device.

Circuits are known which can, in particular, be connected upstream of electronic units which are to be driven by sensor switches, in order to protect said units against undefined signal values or to limit the range of values of the switching input variables to a permissible range and/or to a range which can be processed nondestructively.

Examples of this are the circuits L 9703, L 9704 (Octal Ground/Supply Contact Monitoring circuits), as described on pages 317-327 in the "AUTOMOTIVE PRODUCTS DATABOOK, 2nd Edition/January 1993 from SGS-Thomson. In these circuits, a test current which is compared in a currentcomparing device with a reference current produced internally in this circuit is applied to the switching contact; the comparison result signal is output as switching signal via a complementary switching output stage.

It is disadvantageous in this case that these circuits are suitable either only for switching contacts connected to ground (low-side switching contacts) or only for switching contacts connected to the supply voltage 2 (high-side switching contacts). Thus, it is necessary, for example, f or respectively eight switching contacts of the same type (low-side or highside) to be present in order to be able to fully utilize a corresponding circuit.

This disadvantage is compensated only partially by other known circuits, which each contain a respective half of the number of corresponding circuits f or low-side and high-side switches in a component. An example of this is the circuit L 9705 (double quad contact interface circuit) as described on pages 329-333 of the abovementioned DATABOOK. This circuit, too, can also be optimally utilized only if four high-side and four lowside switches are to be interrogated. In the case of five high-side and three lowside switches, two specimens of this circuit would therefore already be required, in which case 50% of the circuit capacity used - that is to say, the total capacity of a complete circuit - would go to waste.

The present invention proposes a device for the switching drive of an electronic unit, which dispenses with the need to tune the number and type of switches to available low-side and/or high-side inputs of the device, that is to say in which it is immaterial which category of switches finally comes to be applied, and the power/space ratio of a corresponding device no longer depends on the type of the switches which come to be applied, but only on the total number of all the switches and on the input channel width of a corresponding circuit.

According to the present invention there is provided a device for the switching drive of an electronic unit, having at least one switching input, means for applying interrogating current to at least one switch, which can be connected to the at least one switching input, and having comparing means for comparing a signal level, occurring due to said interrogating current along the switching path, with a reference value, and having at least one switching output from which the electronic unit can be driven as a function of the result of comparison, and it being the case that the 3 at least one switching input can be connected via the switching path of the at least one switch at least indirectly to a potential close or equal to the potential of one of the two supply voltage terminals of the device, wherein - the comparing means are operationally connected on the input side to the input of the device, and the means f or applying current comprise at least outputs both of a current source and of a current sink, and the device further comprises:

- sequence control means drivable by a clock generator; - at least one pair of changeover switches comprising in each case first and second changeover means; - at least first and second storage means and at least one evaluation logic unit, which latter is connected on the input side to the outputs of the storage means and represents with its output the output of the device, and - it being the case that, as controlled by the sequence control means, the input of the device can be connected alternately via the f irst changeover means to the said current source output and current sink output, and the output of the comparing means can be connected via the second changeover means in a fashion alternating synchronously therewith to the input of the f irst and second storage means.

The device according to the invention has the advantage that it can evaluate both high-side switches and low-side switches. In the case of implementation using suitable waf er technology, it can easily be completed by function components for overvoltage protection and inverse polarity protection of the inputs, and can be designed as an arbitrarily compilable standard cell, and can be integrated together with known control functions in a space-saving fashion. It can therefore be produced in a particularly economic fashion. The elimination of the particular space requirement for special circuits according to the prior art opens up advantages of space which cooperate with the

4 targeted reduction in the size of electronic control units. Preferably, at least the storage means or the evaluation logic unit is also controllable by the sequence control means. A current-passing circuit for protecting the device against overvoltage and/or erroneous polarity of its input may be provided as operationally connecting means between the input of the device and the input of the comparing means and the said f irst changeover means. A defined capacitor for debouncing switching contacts and/or filtering may also be provided between the input terminal and at least one of the two operating voltage terminals. The device may be defined and available as a freely compilable semiconductor standard cell. Pref erably, the device comprises a plurality of inputs and outputs and the same plurality of pairs of changeover switches, paired memories and evaluation logic units.

The device may be integrated in a plurality of specimens on a semiconductor chip. Further, the plurality of paired changeover means or the plurality of specimens of the device may be used in common to drive a single clock generator. Preferably, the plurality of specimens of the device have and use common current- impressing means which feed current source outputs and current sink outputs. Preferably, the evaluation logic unit does not change its output state until with reference to the changeover cycle prescribed by the sequence control means a new input signal, formed from the two output signals of the storage means, of the evaluation logic unit was present at the latter longer than the period of a changeover cycle.

An exemplary embodiment of the invention is explained in the following description and illustrated in the drawing, in which:-

Figure 1 shows a block diagram of the invention; and Figure 2 shows a state table for the purpose of explaining the functioning.

In accordance with Figure 1, the device 10 which can be driven alternatively by a switch 8 or 9 connected respectively to the supply voltage potential U BAT or to ground potential GND comprises an impressed current source 11 connected to the supply voltage potential U BAT and an impressed current sink 12 connected to ground potential GND. It is possible within the framework of the invention in conjunction with multiply parallel provision of the device 10 f or the current source 11 and the current sink 12 or components thereof also to be present only singly and to be co-used in the same way by all specimens of the device which are present, with the result that, for example, only current-carrying collector, emitter, drain or source outputs of a central current source or current sink structure are apportioned to each individual device. The current source and current sink assumed with respect to the exemplary embodiment described here to that extent do not represent any sort of restriction.

The output of the current source 11 and of the current sink 12 are led to the two switching terminals 13A.1 and 13A.2, used as inputs, of a changeover switch 13A whose common terminal 13A.3 acts as output and is connected operationally to the input terminal 18 of the device.

The input terminal 18 is, on the other hand, also led to the input of a comparator 14 with an internal, preferably fixed response threshold. The output of the comparator 14 is led to the terminal, acting as common input 13B.3, of a second changeover switch 13B whose two switching terminals 13B.1 and 13B.2, used as outputs, are led in each case to data inputs of a f irst and second storage cell 15 and 16, respectively. The outputs of the two storage cells are led to an evaluation logic unit 17, which latter is, for its part, operationally connected to the output 19 of the device.

Furthermore, the device 10 also comprises a clock generator 21 which f eeds a sequence control system 20, which latter synchronously drives the two changeover switches 13A and 13B via an operational connection 22. It can further be provided that the sequence control system 20 also controls 6 the evaluation logic unit 17, and is further also operationally connected to set inputs of the storage cells 15 and 16 - to the extent that the storage cells 15 and 16 are ones which have separate set inputs.

since - as explained later below - no high demands are placed on the constancy of the switching rate, the clock generator 21, for example, can also be co-integrated very cost effectively and can, in common with the sequence control system 20, which can likewise be co-integrated, be centrally provided/used for/by a multiplicity of such devices.

According to a development, it is possible to arrange in the input line a further current-passing circuit 24 for protecting the device against overvoltage and/or polarity reversal of the input terminal 18. Furthermore, a defined capacity 25 can also be provided at the input. It can, nevertheless, also be integrated in the circuit 24 or be formed therein "partially electronically", for example, for instance by "amplifying" a smaller integrable capacitor to a practically useful value by means of amplifying elements which can possibly simultaneously further fulfil protective functions for the input of the comparator 14. The pair 13 of changeover switches can, for example, be designed in the manner of multiplex cells of a multiple analog switch, which take up particularly little of the chip area in CMOS technology, for example.

The functioning of the device is rendered clear with the aid of Figure 2.

The sequence control system 20 operates in rapid sequence the changeover switches 13A and 13B and drives the memories 15 and 16 synchronously therewith in order to store the respective output signal of the comparator 14, and the evaluation logic unit 17 for the purpose of decoding the memory contents. The frequency of the switchover is not critical in this case: it need only be large enough in relation to the minimum closing time of the switches 8 and 9 for an only brief closure of one of the switches 8 and 9 W 7 not to remain undetected.

If, for example, the switch 8 is closed, because of a lack of potential difference no source current ILI or only a vanishing one, f lows f rom UBAT via the switching path 13A.1-13A.3, whereas because of a sufficient potential dif f erence the sink current IH f lows to ground GND f rom UBAT via the switch 8 and the switching path 13A.3-13A.2 and the current sink 12. This means that both in the upper and in the lower position of the changeover switch 13A the point 13A. 3 has a high potential close to UBAT and that with respect to its internal reference potential the comparator thus outputs the logic state 11HII in both switch positions and charges via the switching paths 13B.3-13B.1 and 13B.3 13B.2 into the storage cells 15 and 16. The evaluation logic unit 17 is constructed in such a way that it converts and outputs two appropriately readable IIHII states, for example into the logic output state IIHII to the terminal 19, which denotes "high-side switch closed".

If, for example, the switch 9is closed, because of a lack of potential difference no sink current IH, or only a vanishing one, flows via the switching path 13A.3-13A.2, whereas because of a sufficient potential difference the source current IL flows to ground GND via the current source 11 and the switching path 13A.1-13A.3 and the switch 9. This means that both in the upper and in the lower position of the changeover switch 13A the point 13A.3 has a low potential close to GND and that with respect to its internal reference potential the comparator thus outputs the logic state 'ILI' in both switching positions and charges via the switching paths 13B.3-13B.1 and 13B.3-13B.2 into the storage cells 15 and 16. The evaluation logic unit 17 is constructed in such a way that it converts two appropriately readable ILI' states, for example into the logic output state 'ILI' and outputs them to the terminal 19, which denotes "low-side switch closed".

It may be seen that a distinct third state exists whenever none of the two switches 8 and 9 is closed and the 8 input 18 to that extent experiences no input or output of current. Specifically, in this case the potential of the point 13A.3 at the upper or lower position of the changeover switch 13A is always close to UBAT or GND, because to be precise the current carrying capacity of the current source 11 or current sink 12 is substantially higher than the sum of all the leakage currents which can be led of f from the input 18 past the comparator 14.

The comparator 14 therefore conducts the logic output potential 11H11 during the synchronous upper positions of the changeover switches 13A and 13B, and the logic output potential "Ll' during the synchronous lower positions of the changeover switches 13A and 13B. Consequently, it is always the logic state 11H11 which is written into the memory 15 via the switching path 13B.3-13B.1, and always the logic state "Ll' which is written into the memory 19 via the switching path 13B.3-13B.2. The evaluation logic unit 17 is constructed in such a way that it evaluates a logic state 11H11, which can be read out from the memory 15, and a logic state "Ll' which can be read out simultaneously from the memory 16, and thus evaluates the output of a highresistance circuit "Z11 (so-called tristate output).

It may further be seen that it is impossible given proper functioning for the state "Ll' to be written into the memory 1 and the state "H11 into the memory 16. The evaluation logic unit 17 can therefore further be constructed in such a way that a logic state 111,11 which can be read out from the memory 15 and a logic state 11H11 which can be simultaneously read out from the memory 16 are either ignored by it or else evaluated as an alarm signal indicating faulty functioning, for example as a burst of "LH" and "H-L" transitions or a continuous frequency signal at the output 19, which can be conditioned by a downstream electronic system to form an alarm signal.

It is thus possible using the device according to the invention to transmit other switching signals via an appropriate bus (not represented), to which its output 19 is 9 connected, during the opening times of the switches 8 and 9, as a result of which, for example, it is possible to implement very simple plausibility tests within the framework of bus management by means of appropriate monitoring switches (not represented) for the switches 8 and 9 and multiply parallel provision of the device 10.

For the sake of completeness, the invention also further comprises a circuit of the input 18 which has a defined debouncing capacitor 25. In this case, such a capacitor can be connected both to ground GND and to the other operating voltage pole U BAT, or can be formed from two appropriately connected individual capacitors. The device can be designed in a particularly current-saving fashion provided the capacitance value is suitably matched to the fundamental, in practice specifically not arbitrarily small source resistance of the charging and discharging current path in which respective switches 8 and 9 are situated, and to the switching rate.

This is conditioned by the fact that such a capacitor acts as a hold capacitor which is precharged or pre-discharged by the upstream switch circuit, and that the potential at the input of the comparator 14 thereby changes more slowly than at the input 18. It is possible in this case by providing and suitably dimensioning a certain time offset in the sequence control system 20 between the drive 22 of the changeover switches 13A and 13B and the charging or overwriting of the storage cells 15 and 16 to ensure that the comparator output is in each case not read into the storage cells until possible parasitic overshooting at the capacitor 25 has decayed.

Furthermore, it is possible to achieve by appropriate design of the evaluation logic unit 17 and/or of its drive 23 on the side of the sequence control system 20 that its output stage does not change until after multiply repeated reading-in of the same output status of the storage cells 15 and 16. In this way, both debouncing of the switching paths of the switches 8 and 9 and overshooting, which even in the case of conventional wiring without the def ined capacitor 25 can then occur in a more or less uncontrolled f ashion, can be f iltered out as f ar as possible and thus rendered harmless.

The device according to the invention may be seen to comprise only function elements which take up little integration area on a semiconductor chip. It is to this extent within the framework of the invention to define and construct the device as a standard cell which within the framework of chip design of circuits f or electronic units which are to be driven by switches can be freely compiled and is to this extent arbitrarily available and can be arbitrarily used.

This holds, in particular, for multi-parallel forms of construction which centrally require and use only once the elements, essential in a way which saves semiconductor chip area, of the current source 11 and current sink 12 for providing the two currents IL and IH and/or the clock generator and the sequence control system 20.

Claims

1 A device f or the switching drive of an electronic unit, having at least one switching input, means for applying interrogating current to at least one switch, which can be connected to the at least one switching input, and having comparing means for comparing a signal level, occurring due to said interrogating current along the switching path, with a reference value, and having at least one switching output from which the electronic unit can be driven as a function of the result of comparison, and it being the case that the at least one switching input can be connected via the switching path of the at least one switch at least indirectly to a potential close or equal to the potential of one of the two supply voltage terminals of the device, wherein - the comparing means are operationally connected on the input side to the input of the device, and the means for applying current comprise at least outputs both of a current source and of a current sink, and the device further comprises:

- sequence control means drivable by a clock generator; - at least one pair of changeover switches comprising in each case first and second changeover means; - at least first and second storage means and at least one evaluation logic unit, which latter is connected on the input side to the outputs of the storage means- and represents with its output the output of the device, and - it being the case that, as controlled by the sequence control means, the input of the device can be connected alternately via the first changeover means to the said current source output and current sink output, and the output of the comparing means can be connected via the second changeover means in a fashion alternating synchronously therewith to the input of the first and second storage means.

12 17

2. A device according to Claim 1, wherein at least the storage means or the evaluation logic unit is also controllable by the sequence control means.

3. A device according to Claim 1, wherein a current passing circuit for protecting the device against overvoltage and/or erroneous polarity of its input is provided as operationally connecting means between the input of the device and the input of the comparing means and the said first changeover means.

4. A device according to Claim 1, wherein a def ined capacitor for debouncing switching contacts and/or filtering is provided between the input terminal and at least one of the two operating voltage terminals.

5. A device according to Claim 1, wherein the device is defined and available as a freely compilable semiconductor standard cell.

6. A device according to Claim 1, wherein the device comprises a plurality of inputs and outputs and the same plurality of pairs of changeover switches, paired memories and evaluation logic units.

7. A device according to Claim 1, wherein the device is integrated in a plurality of specimens on a semiconductor chip.

8. A device according to Claim 6 or 7, wherein the plurality of paired changeover means or the plurality of specimens of the device are used in common to drive a single clock generator.

9. A device according to Claim 7, wherein the plurality of specimens of the device have and use common currentimpressing means which feed current source outputs and 13 current sink outputs.

10. A device according to Claim 1, wherein the evaluation logic unit does not change its output state until with reference to the changeover cycle prescribed by the sequence control means a new input signal, formed from the two output signals of the storage means, of the evaluation logic unit was present at the latter longer than the period of a changeover cycle.

11. A device for the switching drive of an electronic unit, substantially as described herein with reference to and as illustrated in the accompanying drawing.