GB2279528A

GB2279528A - Current amplifier circuits

Info

Publication number: GB2279528A
Application number: GB9313085A
Authority: GB
Inventors: Gary Miller
Original assignee: Individual
Current assignee: Individual
Priority date: 1993-06-25
Filing date: 1993-06-25
Publication date: 1995-01-04
Also published as: GB9313085D0

Abstract

An amplifier has a signal combiner G1 having three inputs and two outputs, a first output is coupled to the input of an output amplifier Gr, a second output is coupled to a second input, an input signal is coupled to the first input and the third input is coupled to the output of the output amplifier by a feedback means B. Further aspects are described. Embodiments are described using bipolar and FET's and circuits employing both negative and positive feedback are described. <IMAGE>

Description

CURRENT MODE CIRCUITS This invention relates to circuits which use current as the internal, input or output controlled variable and can be used to implement a wide range of circuit functions including: (1) Transconductance amplifiers with current feedback (2) Constant bandwidth transconductance amplifiers with current feedback (3) Voltage controlled voltage amplifiers (4) Current controlled voltage amplifiers (5) Instrumentation amplifiers with voltage or current outputs.

(6) Industrial current transmitters.

(7) Feedforward current output amplifiers (8) Operational amplifiers.

(9) Signal faders/wipers.

(10) Multiplexors (11) Variable gain transconductance amplifiers(gain controlled by a current or voltage input) This invention is based on two core ideals which use current as the controlled variable in an electronic circuit ie: (1) A current sampler which has one or two inputs and two outputs. The main feature of the sampler is that the output current from its aux output is some linear proportion of its main output. For example if the main output current swing is + or - lOOmA and the aux output current swing is + or - lmA then the ratio of aux current over main output current is 0.01 (2) A current amplifier which provides high current gain by using two current mirrors in its simplest form coupled such that they form a positive feedback loop.The mirrors are designed so that the resultant loop gain is as close as possible to unity and thus provide high current gain.

Features of this core ideal are both high zero frequency current gain ( typically 60dB ) and wide unity bandwidth C typically 200Mhz ) with low distortion and supply current.

More advanced versions use feedforward current gain correction which increase the zero frquency current gain without the requirement of mirror gain trimming.

This document also shows how the two core ideals can be combined to produce a range of amplifiers with either voltage or current inputs or outputs ie V.C.V.S, V.C.C.S, C. C. V.5 or C.C.C.S amplifiers.

Also included are a large number of end products based on the Multiple loop feedback amplifiers which can primarily be implemented as monolithic integrated circuits.

Pages 3 to 43 describe the positive feedback current amplifier.

Pages 44 to 123 describe the multiple feedback amplifiers.

Pages 124 to 138 describe the current sampler.

Pages 139 to 214 describe a large number of possible products which are based on the multiple feedback arrangments.

Positive feedback current amplifier The first core ideal presented in this document is a high current gain positive feedback loop amplifier. To construct a high current gain amplifier a circuit arrangment is proposed as shown in fig 1 and 2.

Fig 1 comprises two internal current amplifiers Xa and #b. The input current Iin sums with the feedback current at node 1. The output current is: Io=(Iin+If)#a - - - - 1 and If is If=(lin+If)#b - - - - 2 also Ie=Iin+If - - - - - - 3 Sub 3 into 1 Io=Ie#a - - - - - - - 4 Sub 3 into 2 If=Ie#b - - - - - - - 5 sub 5 into 3 Ie=Iin+IeXb Ie=Iin - - - - - - - 6 1-#b Sub 6 into 4 Io=#a - - - - - - - 7 Iin 1-#b Setting the #b variable to unity ie ensureing that the current amplifier has a unity current gain gives:: Io=#a = # current gain lin 1-1 ie by setting the positive feedback loop to unity gain, results in infinite current gain.

In practice Xb will not exactly equal unity due to factors which include component tolerence in #b which effect the the gain of Xb and drift of these components with temperature.

For example if #a = 1 and #b = 0.999 ie #b accurate to 0.17. of unity gain then: Io = 1 = 1000 Iin 1- 0.999 Also in any practical implementation of fig 1 both #a and #b will be a function of frequency.For the cases where both #a and wb have a single responce pole:

where fpa and fpb are the poles of #a and #b. Rearranging the above equation as detailed on page 10 and assuming fpa=fpb=fp ie identical poles in #a and #b:-

With the magnitude of the gain being:

and the phase shift is:

LIo = - arctan r f for Kb < 1 Iin Io = - arctan rfp(l-Kb3 for Kbcl / Io = 180 + arctan r f fp(1-Kb)for Kb > 1 with the gain at zero frequency being:: Io = Ka Iin 1-Kb If Kb is smaller than 1 then the resultant gain is non-inverting ie the positive feedback loop gain is less than unity. Lf Kb is greater than unity then the resultant current gain is inverting ie the positive feedback loop gain is greater than unity. For the case where l a is inverting then with Kb < 1 the overall gain is inverting and if Kb > 1 the overall gain is non-inverting.

In practical positive feedback current amplifier circuitry it is only possible up to some finite positive or negative output value for I(f/b), for the gain Kb (#b) to be greater than unity. Therefore as the positve or negative current limit is reached the gain will drop from a value greater than unity to a value less than unity. This results in the output current Iout switching phase from inverting to non-inverting if Aa is non-inverting and from non-inverting to inverting if Ab b is inverting. This action will result in amplifier latching and is therefore a undisirable effect. To ensure this effect doesnot occur all practical amplifiers operate with Kb < 1. With Kb < 1 the resultant positive current feedback amplifier provides a linear responce with no latching at saturation, with fast recovery from overdrive.

Fig 2 expands on fig 1 by using two circuit means b an c to represent the positive feedback current amplifier arrangment.

Fig 2 represents a positive feedback current amplifier whereby the amplifier can be implemented using two current mirrors with b representing mirror &num;1 and c representing mirror &num;2. Input signal current to this arrangment can be applied to the input of mirror &num;1 and also to the input of mirror &num;2, with outputs from both mirrors if required. Therefore one can have single ended or differential inputs and single ended or differential outputs. With this arrangment the ,two mirrors provid high current gain for differential inputs and low current gains for common mode inputs.

Pages g to q derive the transfer function for fig 2, output &num;1 is: Iout&num;1 = (IinZ-Iin)c(l+Aa) + (Iin1+Iin2)#c(1-#a) 2K 2K where K = 1-iazb Inpection of the equation shows that if Aa=1 then the common mode gain, as given by the second term is zero , with the differential mode gain (first term) being ditermined by K (l-XaAb: In accoordance with invention there is provided a current mode circuit arrangment comprising: : A current amplifying means with one current input and first and second current outputs, the input of the said current amplifying means whose input impedence is low relative to the output impedence of the first and second outputs of the said current amplifying means, with the second output of the said current amplifying means being coupled to the input of the said current amplifying means, with the signal path from the input of the said current amplifying means through the said current amplifying means to the second output of the said current amplifying means being non-inverting,

ctrre,, the input of the said current amplifying means forming

czrrcA the input of the said arrangment, with the first output of the said current amplifying

forming the current output of the said arrangment, with the said non-inverting signal path current gain being of a value such that the resultent current gain from the input of the said arrangment to output of the said arrangment is substantially greater than unity.

Fig 3 is a circuit diagram of a positive feedback current amplifier which is used to provide a PSPICE simulation, with fig 4 and fig 5 being typical results.

I1 and R4 comprise the input current drive source, with R1, Gv, R2, C1 and Gml forming the basic positive feedback loop.

Gm2 is a transconductance amplifier and provides an output current drive to the load. R2 and C1 provide a responce pole and result in fpa=fpb=lMhz and with R4=lohm, R1=100ohm, R2=lKohm, RL=100ohm, C1=159.15pF, Gv=1. Loop gain is given by GmlR1 therefore if Gm1=0.0099 L.G= 0.0099x100 =0.99 and if Gml=0.00999 then L.G=0.00999x100 =0.999.

Fig 4 is a bode plot of gain and phase for fig 3 with Gml=Gm2 =0.0099 ie a loop gain of 0.99. Inspection of fig 4 shows that the magnitude of current gain is 40dB which agrees with that given by: Io = #a Iin 1-#b also with a unity current gain frequency of 1Mhz. Phase shift is -45 degress at the closed loop pole of 10khz and reaches a maximum of -90 degress at around 1Mhz.

Fig 5 is a bode plot of gain and phase of fig 3 with Gml=Gm2= 0.00999 ie a loop gain of 0.99. Inspection of fig 5 shows that the magnitude of current gain is 60dB, with a unity current gain frequency of 1Mhz. Phase shift is -45 degress at the pole frequency of 1Khz, and reaches a maximum of -90 degress at a frequency of around 100Khz. From the above results the gain can be seen to increase, as the loop current gain approaches unity and the closed loop pole frequency reduces. Phase shift remains at a maximum value of -90 degress. If the loop gain is set at a theoretical value of unity, an ideal integrator is obtained with a infinite zero frequency current gain, but it practice loop gains of the order of 0.99 to 0.9995 would be the norm.

Fig 6 Fig 6 is a current mode positive feedback amplifier arrangment using two current mirrors M1 and M2. Current mirror M1 has two outputs one of which forms the output &num;1 and the other connects to the input of mirror &num;2.

Current mirror M2 also has two outputs, one of which forms the second output &num;2 and the other connects back to the input of mirror M1.

The input signal current and bias currents (for the mirrors M1 and M2 ) are represented by current sources CS1 and CS2.In any practical implementation of fig 6 M1 is designed to have a current gain (71) from its input to its output which connects to the input of mirror M2 multipled by the current gain of mirror M2 from its input to its output which connects to the back to M1 (72) as close to unity ie X 2 = 1 Pages 17 to J8 derive the current gain for this arrangment which is:: For output &num;1 Io&num;1=(Iin1-Iin2)#3(1+#2)+(Iin2+Iin1)#3(1-#2) - - - -(1) 2K 2 K For output &num;2 Io&num;2=(Iin2-Iin1)#4(1+#1)+(Iin1+Iin2)#4(1-#1) - - - -(2) 2K 2 K The first terms in 1 and 2 give the differential gain ie outputs due to the difference in the input currents for Iin1 and Iin2. The second terms in 1 and 2 give the common mode gain ie outputs due to common mode input currents.

For example if 1=2 2 =X3 =54=0.999 ie a 0.1% gain accuracy from unity then for Io&num;l:- (Iinl-Iin2)=0.999(1+0.999)=499.S 2(1-0.9990 (Iinl+Iin2)=0.999(1-0.999)=0.2498 2(1-0.899) ie the differential mode gain is 499.5 (53.9dB) and the common mode gain is 0.2498 .This gives a common mode rejection ratio of 2010g(499.5/0.2498)=66dB In accordence with the invention there is provide a current mode circuit arrangment comprising first and second current

uXery mirrors XThe first output of the first said current mirror is connected to the input of the second said current mirror and the first output of the second said current mirror IS connected to the input of the first said current mirror.

A connection to the input of the first said current mirror forming the first current input of the said arrangment with a connection to the input of the second said current mirror forming the second current input to to the said arrangment.

Second output of the first said current mirror which forms the first current output of the said arrangment.

Second current output of the second said current mirror which forms the second current output of the said arrangment.

In fig 6 the supply voltages can be transposed also the commons of the current mirrors can be grounded or the common connection to the current sources can be grounded.

In fig 6 the current mirrors can be implemented using NPN,PNP,NMOS or PMOS transistors with the appropriate selection of supply rail voltages.The gain of this circuit arrangment depends on the input signal current sources having a high output impedence so as not to act as a current divider with the input impedence of the current mirrors.The most simplest circuit arrangment suitable to drive the current mirrors is a PNP or PMOS differential amplifier, with the collectors/drains connected to the inputs of the two mirrors and thus providing a differential input signal current drive.

Fig 7 and fig 11 are two implementations of fig using two different types of current mirror. Fig 7 is based on a basic 3 transistor mirror and fig 11 is based on a 5 transistor mirror.

Fig 7 consists of Q1,Q3,Q4 and Q6 which provide the positive feedback current loop. Q2 and Q5 are added to give first and second output current drives.Resistors R1, R3,R4 and R5 set the gains of M1 and M2 and can be trimmed if required. For example if the resistors are thinfilm types then one of these resistors can be laser trimmed to set the loop gain as close as practically possible to unity.

Resistors R2 and R5 can have different values than the loop gain setting resistors and with the peak input currents ditermine the peak output currents from the outputs &num;1 and &num;2. Figs 8 to 10 are PSPICE simulations of fig 6 with R1 to R6. = 2500hms, I1 = I2 = 500uA, and RL1=RL2 =5000hms and transistor FT of 800Mhz.

Fig 8 displays the DC transfer characteristics and demonstrates the highly linear gain for both outputs.

The gain is approximately 34dB and in this simulation a current source I3 is connected from the collector of Q1 to the collector of Q4, thus giving a differential input current drive. The outputs provide an output current swing of around 0.9mA for a total current swing in Q1 and Q4 of lmA. Greater gain and output current swing can be obtained by reducing the values of R2 and R3 and with suitable values output current swings of 5mA or more are possible.

Fig 9 displays the magnitude of the current gain from 1Khz to 1Ghz. The frequency of unity current gain is approximately 100Mhz and a zero frequency gain of 34dB, correlating with the DC characteristics. A point to note is that the slope of the gain is first order (-20dB/decade).

Fig 10 displays the phase shift of both output currents and indicates an excess phase shift of around -8 degress at 100Mhz and -27 degress at 500Mhz from a value indicated by a first order responce ie -90 degress maximum.

Fig 11 is a positive feedback current amplifier based on a 5 transistor current mirror. Q1, Q3, Q4, 46, Q7, Q8, Q8 and Q10 provide the basic positive feedback loop with Q2 and Q5 added to give output current drive signals. Resistors R1, R3, R5 and R6 set the gains of M1 amd M2 and can be trimmed if required.

This arrangment will give typical differential current gains of 50dB to 70dB.

Figs 12 to 14 are PSPICE simulations of fig 11 with a single input drive (CS1), with R1=R3=R4=R6=500ohms, R2=R5=lOOohms, CS1=CS2=250uA, RL=S0ohms, and with Q2 and Q5 xS the emitter areas of Q1, Q3, Q4, and Q6, with transistor FT of 800Mhz.

Fig 12 is a bode plot of the output &num;1. Observation shows that the current gain is very high at around 74dB with an approximate first order slope, and with a unity current gain frequency of 100Mh Fig 13 is the DC transfer characteristics and demonstrateShighly linear current gain for output &num;1, with the gain being around 74dB correlating with fig 12. The output provides an output swing of around 2.3mA for a total current swing in Q1 and Q2 of 500uA, this being due to the greater emitters areas of Q2 and Q5 and the reduced values of R2 and R5.

Fig 14 is a phase plot of output &num;1 and indicates zero excess phase up to 100Mhz and only 15 degress at 500Mhz.

Figs 15 to 17 are PSPICE simulations of fig 11 with a differential input drive with R1 to R6 =2500hms, I1=I2=lmA, Q1 to Q6 same emitter areas, RL1=RL2=500hms and with transistor FT of 800Mhz.

Fig 15 is a plot of the DC transfer characteristics and shows an output current swing of lmA for a total current swing in Q1 and Q2 of lmA, with a current gain of 62dB.

Fig 16 is a bode of the gain magnitude and indicates a gain of 62 dB, correlating with fig15 and a unity gain frequency of 50Mhz.

Fig 17 is a plot of the phase shift at each output with I(RL1) being inverting and I(RL2) non-inverting. Both show about -9 degress of excess phase up to lOOMhz.

To improve the high frequency phase shift of fig 11 additional series CR networks have been added to the PSPICE simulations of 2500hms and 20pF from the emitters of Q1 and Q4 to OV.

Fig 18 It is also possible to get a useful output signal from a positive feedback current amplifier based on two current mirrors by coupling the two current common output connections to the load. Fig 18 shows the basic arrangment. The commons are not connected directly to the -Vs supply but connect to the loads represented by RL1 and RL2. PagesROtoZ2derive the transfer functions for the two outputs and are: Iout&num;1=(Iin1-Iin2)(1+#1)(1+#2)+(Iin1+Iin2)(1+#1)(1-#2) 2K 2K Iout&num;2=(Iin2-Iin1)(1+#2)(1+#1)+(Iin2+Iin1)(1+#2)(1-#1) 2K 2K Where the first terms are the differential mode gains and the second terms are the common mode gains.

In accordance with the invention there is provided a current mode circuit comprising first and second current mirrors, each comprising an input connection, a output connection and a common output connection, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror, the input of the first said current mirror forming the first current input of the said arrangment,the input of the second said current mirror forming the second current input of the said arrangment,the common output of the first said current mirror forming the first current output of the said arrangment, with the common output of the second said current mirror forming the second current output of the said arrangment.

Fig 18 can utilise NPN or NMOS devices and with the supplys transposed PNP or PMOS devices can be used. For example the 3 and 5 transistor current mirrors of figs 7 and 11 can be used also standard 3 or 4 transistor wilson current mirrors can be used.

Fig 19 Fig 19 is a positive feedback current amplifier arrangment with the output taken from the common outputs of current mirrors M1 and M2. Current mirrors M1 and M2 form the basic unity loop gain amplifier, with the inputs &num;1 and &num;2 forming the bias/signal inputs. The common of mirrors M1 and M2 are coupled to the inputs of mirrors M3 and M4 which provide the but current drives &num;1 and &num;2.

A modification to this arrangment is shown dotted as an additional current mirror which is driven by the output current of M3 and provides a push-pull single ended output.

By taking the output from the commons of M1 and M2 allows the use of standard 3 or 4 transistor wilson current mirrors for M1 and M2. This circuit arrangment can also be implemented with PNP , NMOS or PMOS devices with the appropriate supply voltages.

In accordence with the invention there is provided a current operating circuit arrangment as in fig 19 comprising: first and second current mirrors, with the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror whose output is coupled to the input of the first said current mirror, third and forth current mirrors, with the input of the third said current mirror being coupled to the common of the first said current mirror, with the input of the forth said current mirror being coupled to the common of the second said current mirror, the output of the third srd current mirror forming the first currnet output of the said arrangment, the output of the forth said current mirror forming the second current output of the said arrangment, the input of the first said current mirror forming the first current input of the said arrangment, with the input of the second said current mirror forming the second input of the said arrangment.

Pages 25 to 29 derive the transfer functions for this arrangment and are: Io&num;1=(Iin1-Iin2)(1+#1)#3(1+#2)+(Iin1+Iin2)(1+#1)#3(1-#2) 2K 2K Io&num;2=(Iin2-Iin1)(1+#2)#4(1+#1)+(Iin2+Iin1)(1+#2)#4(1-#1) 2K 2K where K=#1#2 With the first terms representing the differential mode gains and the second terms representing the common mode gains. Using the equation for output &num;1 and with #1=#2=#3=#4=0.999 ie a 0.17. gain accuracy from unity: (Iin1-Iin2)=(1+0.999)0.999(1+0.999) = 1996 2(1-0.999) (Iin1-Iin2)=(1+0.999)0.999(1-0.999) = 0.9985 2(1-0.999) ie the differential mode gain is 1996 (66dB) and the common mode gain is 0.9985 (-0.013dB).This gives a common mode rejection ratio of 66dB.

Fig 20 Fig 20 is a positive feedback current amplifier based on the block diagram arrangment in fig 19 . The basic positive feedback loop ( M1 and M2 ) comprises Q1 and Q2 which make up M1 and Q3, Q4 which make up M2. R1 to R4 substantially set the gains of M1- and M2 and can be trimmed ( ie laser trimmed thin film resistors ) to set the loop gain as close as possible to unity. This trimming procedure adjusts the loop to accomandate spreads in the vbe matching of Q1 to Q4.

The output from the unity loop is taken from the output common currents of M1 ad M2, by the current mirror comprising Q11 and Q12 ( M3 ) also Q13 and Q14 ( M4 ).

Q5 tO Q7 also forms a current mirror which senses the total common current of M1. The purpose of Q5 to Q7 is to generate a feedforward current to the output of the current mirror M1 such that the current gain of M1 is closer to unity, by cancelling the base currents of Q1 and Q2 which have to flow into the mirror input. This compensation relies on the matching beta matching of Q1, Q2, Q6, and Q7.

For the purpose of anaylsis assume a current I flows through R1 and R2. With Q6 and Q7 having reasonably matched vbe they will both conduct sutantially the same collector current I.

The collector current of Q5 will be two Ib ( Q6 and Q7 matched Beta ) amd this current will flow in the output circuit of M1. Because the collector currents of Q1, Q3, Q6 are the same the collector current Q5 ( two Ib ) will match the base currents of Q1+Q2, and thus cancel the effect of finite Beta in Q1 and Q2 and bring the current gain ( of M1 closer to unity. The current levels of input and output circuits now match with a total current into the input of 2Ib+IcQ1 and a total output current of 2Ib+IcQ2. The current in R1 is IcQ1+Ib and the current in R2 is IcQL+Ib.

For unity current gain () ) in M1 then ( assuming substantial base current matching ) the collector currents of Q1 and Q2 must also substantially match. This is achived by the at or mentioned resistor trimming. Q8 to Q10 also operate in the same manner as Q5 to Q7 and compensate forthe base currents of Q3 and Q4. CSl and CS2 provide input bias currents and also form the generalised input signal drive, with either CSl or CS2 forming the input signal drive or both giving a differential input drive. Figs 21 to 22 are PSPICE simulations of fig 20, with R1 to R8=2500hms, I1=I2=0.5mA, RL1=RL2=500hms and transistors with a Ft of around 800Mhz.Fig 21 has two plots. Plot (a) shows the total input base currents into the mirror M1 ie IbQ1 and IbQ2 plotted with the feedforward current IcQ5 against the input current I1 ( CS1 ). This plot shows that the feedforward current matches the total base current over the input current range and thus provides the correct compensation. Plot (2) shows the output current swing plotted against the input current giving an output current swing of 0.8mA for an input current swing of 3uA, giving a current gain of 266 t 48.5dB ).

The plots of fig 22 show the phase and frequency responce of the arrangment into one of the loads. Points to note are that the phase shift is less than 110 degrees up to approx 400Mhz , with -20 degress excess phase shift (-90 degrees maximum for a first order responce ) and a bandwidth at unity gain of 80Mhz. The simulation can be compared with the current amplifier arrangment in fig 7 which has a gain at low frequency of 35dB, so it can be seen that by useing base compensation improves the gain to 48.5dB ( for this example ) Both fig 7 and 20 use devives that are perfectly matched, so that in practice actual circuits will have a low frequency gain dependent on the Beta, Vbe and resistor matching etc of the actual production IC process and wether or not the resistors are trimmed.

The peak output current swing depends on the value of CSl and CS2, in this simulation O.5mA giving an output current swing of + or - 0.5mA, and also the current gains of the two output mirrors, which in this simulation are unity. If the output mirrors current gains are increased to x1O then the output swing is increased to + or - 5mA.

In accordance with the invention there is provided a current mode circuit comprising first and second current mirrors with said current mirrors comprising two or more bipolar transistors, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror,a first additional circuit means responsive to the common output current of the first said current mirror for generating a feedforward current substantially equal to that portion of the input current of the first said current mirror attributable to the base currents of the said bipolar transistors which comprise the first said current mirror, with the feedforward current of the first additional circuit means being coupled to the output of the first said current mirror,a second additional circuit means responsive to the common output of the second said current mirror for generating a feedforward current substantially equal to that portion of the input current of the second said current mirror attributable to the base currents of the said bipolar transistors which comprise the second said current mirror, with the feedforward current of the second said additional circuit means being coupled to the output of the second said current mirror, a connection to the input of the first said current mirror forming the first current input of the said arrangment, a connection to the input of the second said current mirror forming the second current input of the said arrangment, a third additional circuit means responsive to the currents of the first said current mirror for generating a first output current, a forth additional circuit means reponsive to the currents of the second said current mirror for generating a second output current.

A modification to fig 20 is to remove Q11 to Q14 and connect the emitters of Q6, Q7, Q9 and Q10 to OV. Output signals can then be obtained by additional transistors in M1 and M2 with there associated emitter resistors, and also additional transistors in M3 and M4 to compensate base currents.

Positive feedback current amplifiers with error feedforward gain correction, Fig 23 The previous mentioned positive feedback current amplifier arrangments rely on the ability to produce current mirrors which have current gains ( ) as close as possible to unity to give high overall current gain. In the case of implementing these arrangments as part of an integrated circuit the mirrors would most likely be trimmed ( eg laser trimming thin film resistors ) to give adequate gain ( #@ accuracy.

A different approach preposed here is to provide an additional circuit means which senses the input current of the current feedback amplifier and also the feedback current of the amplifier and provides an error correction signal which is proportional to the difference of these two currents.

This error current is used as a feedforward current and sums with the feedback current and results in a loop gain closer to unity and therefore greater current gain.

Fig 23 is the proposed circuit arrangment in a block diagram form. #a andab are current amplifiers, with Iout a function of the error input current Ie and #a and the feedback current a function of the error input current Ie and l b. b. S1 and 52 are current samplers and ideally provide sample currents equal to the error current Ie and the feedback current If.

A is a current summing means which sums the sample currents from S1 and 52 and provides the differnce current Id which is the error feedforward current. Pages to derive the transfer function for this arrangment which is: Io = Ii 1-#b-S1A1+#bS2A2 From this equation it can be seen that the terms due to the errorfeedforward error current are S1A1 and S2A2 . These increases the current gain by cancelling or by partial cancelling the unity andb terms.For example if #b=S1=S2 =A=#a= 0.99 ie 17. gain accuracy from unity then: Io = 0.99 Ii 1-0.99-0.99^2+0.99^3 Io = 0.99 Ii 1.99x10-4 Io = 4974 = 73.9dB Without the the error feedforward the gain is: Io = #a = 0.99 = 99 = 39.9dB Ii 1-)b 1-0.99 the error feedforward has therefore increased the current gain of the arrangment from a poor 39.9dB to a respectable 73.9dB.

In accordance with the invention there is provided a current mode circuit arrangment comprising:- a current amplifying means with one current input and first and second current outputs, the input to the said amplifying means whose input impedence is low relative to output impedences of the first and second current outputs of the said amplifiying means, the first output of the said current amplifiying means being coupled to the input of the said current amplifiying means, an additional circuit means responsive to the input current of the said current amplifying means and responsive to the output current of the first output of the said current ampliing means for generating a feedforward current proportional to the difference between the input current of the said current amplifiying means and the output current of the first output of the said current amplifying means, the feedforward current of the said additional circuit means being. coupled to the input of the said current amplifiying means, the second output of the said current amplifying means forming the output of the said arrangment, the input of the said current amplifying means forming the input of the said arrangment.

In practical circuitry the denominator of the transfer function should be a positive value despite the manufacturing tolerences in the gains of Xb, S1 etc.

In price it is possible to have a number of circuit topologies whereby S1 and 52 are exactly unity by coupling the input and feedback currents directly to the comparison amplifier. It is also possible for Al to equal A2, therefore the modified transfer function becomes: Io = b Ii 1-#b+A(#b-1) The denominator is maintained positive by ensuring that b < 1 and A < 1 ie typical values being Ab=0.93 to 0.98 and A=0.99 to 0.999. With current mirrors used to implement the arrangment, they can be designed such that manufacturing tolerence result in ;Xb and A being less than unity by the geometry adjustments in the active devices and gain setting resistors.

Page 41 gives typical results for Xb=O.95 and A=0.99.

With feedforward the current gain is 1900 (65.6dB).

Without the feedforward gain correction the gain is 19 (25.6dB). Therefore with a poor current gain accuracy in Ab of 5% from unity, feedforward gain correction can result in a current gain of 65.5dB which is a very substantial increase and therefore indicates that no gain trimming is required in the basic postive feedback current loop.

Figs 24, 25, 26, 27, 161 and 162 are a number of more detailed circuit arrangments using mirrors M1 and M2 to provide the basic positive feedback current loop and common base or common gateamplifiers to provide the error feedforward current (A).

For the above circuit arrangments to function correctly the mirrors M1 and M2 both must have seperate input and output circuits to allow current sampling of the input and output currents of the amplifier. The common output connections of M1 a nd M2 are split with the input current of M1, I1, flowing into the input and out of its input circuit via C1, with no portion of it flowing out of the the output common C2. Also for M1 the output current only flows in the output commom C2.Therefore Iin(M1) =I(Cl,M1) and Iout(M1)=I(C2,M1). Likewise for M2 Iin(M2)=I(Cl,M2) and Iout(M2)=IC2,M2). Implementing M1 and M2 with MOSFETS ideally provides this input/output circuit isolation due to negligible gate currents and the correct chose of topologies bipolar devices can also be used.

Q2, M2, Q2+Q4 or M2+M4 are the comparison amplifiers in which the input current of the amplifier (C1,M1) and the output feedback current of the amplifier (C2,M2) are compared, the difference current being the emitter/source current of the prev ious mentioned comparison amplifiers. The output current of the comparison amplifier is the error feedforward correction current which is summed with the positive feedback current of the basic loop and therefor increases the low frequency current gain. In practice the said arrangment would be most be implemented as a monolithic integrated circuit which would provide tight device matching. The mirrors M1 and M2 can be dimensioned such that the maximum loop gain is say 0.98, and with A less than 1 due to wafer tolernces and temperature, the resultant denominator will be a positive value.

Modications to figs 26 to 27 and figs 161 and 162 can include a cascode connected transistor in the (bipolar or mosfet) in the collector/drain circuits of the comparison amplifiers which will increase the dynamic output resistance of the amplifier and provide greater signal isolation.

Fig 28 is a basic positive feedback current amplifier using NMOS devices in which no error feedforward is used. Fig 29 and fig 30 are PSPICE simulations with devices being identical except for the parameters VTO and KP, with M2,M3, M5,M6,M7 amd M8 with VTO=1 amd KP=17u and M1 and M4 with VTO=1.01 and KP=17.8U.

These tolernces in the parameters have been included to model mismatch in devices and allows the basic circuit to be compared with the error feedforward gain correction circuit of fig 31. Fig 29 is a plot of the transfer characteristic which indicate a gain of approximately 18 (25dB). Fig 30 has two plots, the upper indicates the phase shift and and the lower indicates a gain of 25dB with unity current gain bandwidth of 1OMhz. These results are compared with to the results of fig 31 and show how the errorfeedfoward arrangment provides superior low frequency gain far above that obtained from the basic circuit for the same device mismatch.

Fig 31 Fig 31 is a positive feedback current amplifier based on the semi-block diagram circuit arrangment in fig 26 . For fig 31 the basic positive current feedback loop comprises mosfets M1, M2, M3, and M7 which form the first current mirror and M4, M5, M6 and M8 which form the second current mirror. Transistor M10 sums the input current tp the positive feedback amplifier ie the source current of M1, with the output current of the positive feedback amplifier ie the source current of M6.

The source current of M10 which is the difference in the source currents of M1 and M6 is the error feedforward current and is coupled to the positive feeback loop via the drain of M10. M9 maintains the the sources of M2, M3, M4, and M5 at a voltage sustantially equal to the source voltages of M1 and ME, as a difference here will increase the current gain error in the first and second current mirrors. CSl and CS2 provide the input bias currents, with CSl also forming the signal input.

CS3 and CS4 provide currents for both mirrors and M9 and M1G.

M2 provides a single output but M5 can also provide an opposite phase output current if required.

Fig 32 and fig 33 show the results of a PSPICE simulation of the above arrangment. Fig 32 contains a plot of the transfer characteristics with RL=5000hms and CS1=150uA, CS2=ll0uA CS3=250uA, CS4=150uA .The input current swing is approximatly lûûnA producing an output current swing of appoximately 150uA wherefore the current gain is x1500 C 63.5dB ).

As for the simulation for fig 28 the simulation of fig 31 has M2=M3=M5=M6=M7=M9=M10 with VTO=1.0 and KP=17U and M1=M4 with VTO=1.01 and KP=17.8U. Fig 31 is the transfer characteristic and shows an improved linearity over fig 28, with a gain of approximately 60dB and an output swing of 150uA. By the adjustment of device geometrys the output current swing can be increased to 5mA or more.

Fig 33 consists of bode gain and phase plots. The upper plot indicates an excess phase of only 15 degress up to 500Mhz and therefore shows good high frequency preformance. The lower plot idicates the magnitude of gain indicating a low frequency gain of 60dB and a unity gain frequency of 20Mhz.

Therefore comparing the gains for fig 28 and fig 31 it can be seen that the use of errorfeedforward not only increases the gain from a very poor 25dB to a useful 63dB but also increases the linearity of the amplifier, with negligible change in phase responce and with a slight increase in bandwidth. The feedforward amplifier can tolerate large spreads in device parameters and can provide a high gain without resulting to mirror gain trimming, and with the need to trim the feedback loop eliminated it is more cost effective to put multiple amplifiers in the same IC package.

Multiple loop feedback amplifiers Fig 34 to fig 59 are a number of multiple loop feedback amplifiers which are based on the use of a positive feedback current amplifier and where appropriate a current sampler ( see pages12tol58). Arrangments shown provide the four basic types ie V.C.V.S , V.C.C.S , C.C.V.S and C.C.C.S. Each have at there core the positive feedback current amplifier of fig 1 or fig 2 to provide (T=6OdB) current gain.

Figs 34, 38, 40, 46, 50, 54, 55, 58, are V.C.V.5 Figs 36, 42, 44, 48, 52,56,57,59 are V.C.C.S Figs 35, 39, 41, 47, 51 are C.C.V.S Figs 37, 43, 45, 49,53 are C.C.C.S Each arrangment contains a number of building circuit blocks which are: Gm This is a transconductance amplifier which converts the input current to a signal current for driving the positive feedback current amplifiers.

Gr This is a transresistance output stage which converts the the positive feedback current amplifier output current to an output voltage for driving a load.

Gi This is a current amplifier which amplifys the output current from the positive feedback current amplifier and drives the load. Also incorporated in this block is a current sampler which provides the main output current that drives the load but also provides an aux feedback current that is some linear proportion of the main output current.

B This is a active or passive feedback attenuation means which attenuates the feedback voltage or current and ditermines the overall gain of the arrangment. In the case where B drives directly the positive feedback amplifier in a voltage output amplifier B would be an active circuit means.

The transfer function for figs 38 to 53 have been derived assuming that G1 and G2 are non-inverting in nature. In practice these arrangments would be implemented using current mirrors, therefore G1 and G2 would both be inverting. The transfer function is the same whether inverting or non-inverting elements are used for G1 and G2. For example if in fig 52 G1 and G2 are inverting then Gi is assumed inverting to give a required negative feedback loop around B, G1, G2, and Gi.

For the arrangments in figs 38 to 45 the signal current Ta is zero if 1-b=0, with Ic containing the input signal current plus an error component which comprises distortion, noise etc generated in the output amplifier. The input signal drive to the output amplifier is exactly predistorted so that the output signal only contains the input signal components, suitable amplified.

These arrangments in theory then behave as though they have infinite open loop gain, an effect due to the positive current feedback amplifier. In practice due to the finite frequency responce of the positive feedback loop and gain tolerences therein, the zero frequency open loop gain will be finite and Ia will contain a greater input signal component as the input frequency increases.

For the arrangments in figs 46 to 49 the signal current Ia will contain a signal current and a signal component due to errors introduced by the output amplifier.

For the arrangments in figs 50 to 53 Ib only contains a signal component due to distortion etc in the output amplifier.

Fig 34 Fig 34 is a voltage controlled voltage source amplifier. Pages So to 51 derive the transfer function for this amplifier which is : -Vo = #aGrGml Vi 1-)b kaGrB If 1-7b=0, then the transfer function reduces to: -Vo = Gml Vi B ie the output Vo is independent of Gr and any errors in Gr or any signals coupled to Gr donot appear at the output.

In accordance with the invention there is provided current mode circuit arrangment as in Fig 34 comprising: an output amplifier Gr hav ing a voltage output and a current input, a feedback means B whose input is coupled to the output of said output amplifier Gr, a signal combining means G1 having first, second and third current

and first and second current

input means Gml whose voltage input forms the input of the said arrangment and whose output current is the input current of the first input of the said signal combining means Gl,the output of the said feedback means B whose output current is the input current of the third input of the said signal combining means G1, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr,the second

of the said signal combining means G1 whose output current is the input current of the second input of the said signal combinings means G1, the said output amplifier Gr whose voltage output forms the voltage output of the said arrangment.

In general -Vo(s) = #a(s)Gr(s)Gml(s) Vi(s) 1-#b(s)+#a(s)Gr(s)B(s) With s=jw -Vo(jw) = #a GrGml(iw) Vi(jw) 1-#b(jw)+#aGrB(jw) If 1-#b(jw) = 0 ie #b(jw)|= 1 ##b(jw) =#0 then the above transfer function reduces to: -Vobjw) = Gml(jw) Vi(jw) B(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed # b(jw) the output voltage Votjw) is independent of Gr(jw). For the circuit to function correctly the signal path formed by B(jW). #d(jw).Gr(jw) must be inverting. Fig 34 also has an additional input transconductance stage Gm2. This can be used to provide feedforward input signal to the output amplifier Gr. By having Gm2 the arrangment can be configured such that Ic only contains the required error signal to compensate for gain error, nonlinearity, noise etc in Gr and thus reduce the total output swing of G1 which in turn wiil increase its linearity.

Fig 35 Fig 35 is a current controlled voltage source amplifier Pages goto S1 derive the transfer function for this amplifier which is: -Vo = #aGr Vi 1-#b+#aGrB If 1-#b=0, then the transfer function reduces to: -Vo = 1 Vi B ie the output Vo is independent of Gr and any errors in Gr or any signals coupled to Gr donot appear at the output.

In accordance with the invention there is provided a mode circuit arrangment as in Fig 35 comprising:an output amplifier Gr having a voltage output and a current input, a feedback means B whose input is coupled to the output of the said output amplifier Gr,a signal combining means G1 having first, second and third current inputs and first and second current outputs,the output of the said feedback means B whose output current is the input current of the third input of the said combining means Cl, the first output of the said combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose outr current is the input current of the second input of the said signal combining means G1, the first input of the said signal combining means G1 forming the current input of the said arrangment, the said output amplifier Gr whose voltage output forms the voltage output of the said arrangment.

In general -Vo(s) = #a(s)Gr(s) Vi(s) 1-#b(s)+#a(s)Gr(s)B(s) With s=jw -Vo(jw) =#aGr(jw) Vi(jw) 1-#b(jw)+#aB(jw) If 1-#b(jw) = 0 ie |b(jw)|= 1 and #b(jw) =#0 then the above transfer function reduces to : -Vo(jw) = 1 Vi(jw) B(jw) ie with a loop gain of unity magnitude and a zero phase shift around the signal loop formed by Ab(jw) the output Vo(jw) is independent of Gr(jw). For the cicuit to function correctly the signal path formed by Xd(jw).Gr(jw).B (jw) must be inverting.

Fig 36 Fig 36 is a voltage controlled current source amplifier. Pages 56 to 57 derive the transfer function for this amplifier which is: -Io = #aGm1Gi Vi (1-#b)(n+1)+nB#aGi If 1-#b=0, then the transfer function reduces to: -Io = Gml Vi nB ie the output Io is independent of Gi and any errors in Gi or any signals coupled to Gi donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in Fig 36 comprising: an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first, second and third current inputs and first and second current outputs, an input means Gml whose voltage input is the voltage input of the said arrangment and whose output current is the input current of the first input of the said signal combining means G1, the output of the said feedback meanssswhose output current is the input current to the

input of the said signal combining means G1, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the second current output of the said output amplifier Gi forming the current output of the said arrangment.

In general -Io = #a(s)Gm1(s)Gi(s) Vi (1-#b(s))(n(s)+1) + B(s)n(s)#a(s)Gi(s) with s=jw -Io = #aGmlGi (jw) Vi (1-#b(jw)((n(jw)+1) + Bn#aGi(jw) If 1-#b(jw) = 0 ie |#b(jw)|= 1 ##b(jw) =#0 Then the above transfer function reduces to: -Io(jw) = Gml Vi(jw) nB(jw) ie with a loop gain of unity magnitude and zero phase around the signal loop formed by Ab(jw) the output current is independent of Gi(jw). For fig 36 to function correctly the signal path around the loop formed by B(jw) #a(jw).Gi(jw) .n(jw) must be inverting.

Fig 36 can also have an additional input transconductance amplifier (Gm2) which can be coupled to the input and to the input of Gi and provides a feedforward function. This feedforward current will reduce the signal current Ic to only the error components generated in Ci.

Fig 37 is a current controlled current source amplifier Pages 56 to 57 derive the transfer function for this amplifier which is -Io = #aGi Iin (1-#b)(1+n)+nB#a If 1 -Xb = 0 then the transfer function reduces to:- -lo = 1 Iin nB ie the output Io is independent of Gi and any errors in or coupled to to Gi donot appear at the output Io.

in accordance with the invention there is provide a current mode circuit arrangment comprising:an output current amplifier with first and second current outputs and a current input, a feedback means B whose input

current is the outputeof the first output of the said output amplifier Gi, a signal combining means G1 having first, second and third current inputs and first and second current outputs, the output of the said feedback means B whose output current is the input current of the third input of the said signal combining means G1, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Ci, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means Cl, the first input of the said signal combining means G1 forming the current input of the said arrangment, with the second current output of the said output amplifier forming the current output of the said arrangment.

In general -Io(s) = #a(s)Gi(s) Iin(s) (1-#b(s))(1+n(s))+n(s)B(s)#a(s)Gi(s) with s=jw -Io(jw) = #aGi(jw) Iin(jw) (1-#b(jw))(1+n(jw))+nB#aGi(jw) If 1 -#b(jw) = 0 ie |#b(jw)|= 1 ##b(jw) =#0 then the above transfer function reduces to: -Io(:jw) = 1 Iin(jw) n(jw)B(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by #b(jw), the output is independent of Gi(jw). For fig 37 to function correctly the signal path around the signal loop formed by B(jw).#d(jw).Gi(jw).n(jw) must be inverting.

Fig 38 Fig 38 is a voltage controlled voltage source amplifier. PagesCzto 63 derive the transfer fuction for this amplifier which is: -Vo =@meGr#a Vi 1-#b+BGdGr#a If 1-#b=0, then the transfer function reduces to: -Vo =,e Vi BGd ie the output Vo is independent of Gr and any error in GR or any signals coupled to Gr donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 38 comprising an output amplifier Gr having a current input and a voltage output, a feedback means B whose input is coupled to the output of the said output amplifier Gr, a signal combining means G1 have first and second current inputs and first and second current outputs, a signal combining means G2 haveing a voltage and current input and one current output, the said feedback means B whose output current is the input current of the current input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combing means G1 whose output current is the input current to the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the

input of the said signal the first input of the said signal combining means G2 forming the voltage input of the said arrangment, the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment.

In general -Vo(s) = Gem(s)Gr(s)#a(s) Vi(s) 1-#b(s)+B(s)Gid(s)Gr(s)#a(s) with s=jw -Vo(jw) = GmeGr#a(jw) Vi(jw) 1-#b(jw)+BGidGr#a(jw) If 1 - Bb(jw) = O ie |#b(jw)| = 1 ##b(jw) =#0 Then the above transfer function reduces to: -Vo(jw) = Gme(jw) Vi(jw) B(jw)Gid(jw) ie with a gain of unity magnitude and zero phase around the signal loop formed by #6(jw) the output voltage is independent of Gr(jw). For fig 38 to function correctly the signal path around the loop formed by B(jw).Gid(jw).#a(jw).Gr(jw) must be inverting.

Fig 39 is a current controlled voltage source amplifier. Pages 62 to 63 derive the transfer function for the amplifier which is: -Vo = GieXaGr Iin 1-#b+BGid#aGr If 1 -Bb=O then the transfer function reduces to: -Vo = Gie Iin BGid ie the output Vo is independent of Cr and errors in or coupled to Gr donot appear at the output Vo.

In accordance with the invention there is provided a cuurent mode circuit arrangment as in fig 39 comprising:- an output amplifier having a current input and a voltage output, a feedback means B whose input is coupled to the output of the said output amplifier Gr, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and one current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G2,the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means Cl, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the first input of the said signal combining means G2 forming the current input of the said arrangment, with the voltage output of the said output amplifie forming the voltage output of the said arrangment.

In general -Vo(s) = Gie(s)#a(s)Gr(s) Iin(s) 1-#b(s)+B(s)Gid(s)#a(s)Gr(s) with s=jw -Vo(jw) = Gie#aGr(jw) Iin(jw) 1-#b(jw)+BGid#aGr(jw) If 1 - ab(jw) = O ie |#b(jw)|= 1 ##b(jw) =#0 Then the above transfer function reduces to: -Vo(.jw) = Gie(jw) Iin(jw) BGid(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by #b(jw) the output voltage is independent of Gr(jw). For fig 39 to function correctly the signal path around the loop formed by B(jw).Gid(jw)#a(jw).

Gr(jw) must be inverting.

Fig 40 Fig 40 is a voltage controlled voltage source amplifier. Pages 68 to dq derive the transfer function for this amplifier which is: -Vo = GmeXaGr Vi 1-#b+BGmd#a Gr If 1-#b=0, then the transfer function reduces to: -Vo = Gme Vi BGmd ie the output Vo is independent of Gr and any errors in Gr or any signals coupled to Gr donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in Fig 40 comprising: an output amplifier hav ing a voltage output and a current input, a feedback means B whose input is coupled to the output of the said output amplifier Gr, a signal combining means G1 having first and second currents inputs and first and second current outputs, a signal combining means G2 hav ing first and second voltage inputs and a current output,the output of the said feedback means B whose output voltage is the input voltage of the second input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Cr, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means 62 whose output current is the input current of the first input of the said signal combining means G1, the first voltage input of the said signal combining means G2 forming the voltage input of the said arrangment, the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment.

In general -Vo(s) = Gme(s)#a(s)Gr(s) Vi(s) 1-Eb(s)+B(s)Gmd(s)\a(s)Gr(s) with s=jw -Vo(jw) = Gme#aGr(jw) Vi(jw) 1-#b(jw)+BGmd#aGr(jw) If 1- Xb(jw) = 0 ie |#b(jw)|= 1 ##b(jw) =#0 then the transfer function reduces to: -Vo = Gme(jw) Vi BGmd(jw) ie with a loop gain of magnitude unity and zero phase shift around the signal loop formed by #b(jw) the output Vo(jw) is independent of Gr(jw). For the circuit to function correctly the signal path formed by B(jw).Gmd(jw) #a(jw).Gr(jw) must be inverting.

Fig 41 Fig 41 is a current controlled voltage source amplifier. Pages 68 to 67 derive the transfer function for this amplifier which is: -Vo = Gie#aGr Iin 1-#b+BGmd#aGr If 1 - #b = 0 then the transfer function reduces to: -Vo = Gie Vi Bcmd le the output Vo is independent of Gr and any signals in to Gr or coupled to Gr donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in Fig 41 comprising an output amplifier Gr having a voltage output and a current input, a feedback means B whose input is coupled to the output of the said output amplifier Gr, a signal combining means G1 haveing first and second current inputs and first and second current outputs, a signal combining means G2 haveing a voltage input, a current input and a current output, the output of the said feedback means B whose output voltage is the input voltage of the voltage input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means Ç2 whose output current is the input current of the first input of the said signal combining means G1, the current input of the said signal combining means G2 forming the current input of the said arrangment, with the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment.

In general -Vo(s) = Gie(s)ats)Gris) Iin(s) 1-#b(s)+B(s)Gmd(s)#a(s)Gr(s) with s=jw -Vo(jw) = Gie#aGr(jw) Iin(jw) 1-#b(jw)+BGmd#aGr(jw) If 1 - Xb(jw) = 0 ie |#b(jw)| = 1 ##b(jw) =#0 Then the above transfer function reduces to: -Vo(jw) = Gie(jw) Iin(jw) BGmd(jw) ie with a gain magnitude of unity and zero phase shift around the signal loop formed by #b(jw) the output is independent of Gr(jw). For fig 41 to function correctly the signal path formed by B(jw).Gmd(jw).)a(jw).Gr(jw) must be inverting.

Fig 42 Fig 42 is a voltage controlled current source amplifier Pages 74 to 75 derive the transfer function for the amplifier which is: -Io = & eXaGi Vi (1-#b)(n+1)+BnGid#aGi If 1 - Ab = 0, then the above transfer function reduces to: -lo = Gme Vi BnGid ie the output is independent of Gi and any errors in or coupled to Gi donot appear at the output.

In accordance with the invention there is provided a current mode cicuit arrangment as in fig 42 comprising:an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the the output current of the first output of the said output amplifier Ci, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having a voltage input, a current input and a current output, the the output of the said feedback means B whose output current is the input current of the current input of the said signal combining means G2, the first output of the said signal combining means whose output current is the input of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the voltage input of the said signal combining means G2 forming the voltage input of the said arrangment, with the second current output of the said current amplifier Gi forming the current output of the said arrangment.

In general -Io(s) = Gme(s)#a(s)Gi(s) Vi(s) (1-#b(s))(n(s)+1)+B(s)n(s)Gid(s)#a(s)Gi(s) with s=jw -Io(jw) = Gme#aGi(jw) Vi(jw) (1-#b(jw))(n(jw)+1)+BnGid#aGi(jw) If 1 - #b(jw) = O ie|#b(jw)|= 1 ##b(jw) =#0 Then the above transfer function reduces to: -Io(jw) = Gme(jw) Vi(jw) B(jw)n(jw)Gid(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by Ab(jw) the output current is independent of Gi(jw). For fig 42 to function correctly the signal path around the loop formed by B(jw).

Gid(jw).#a(jw).Gi(jw).n(jw) must be inverting.

Fig 43 Fig 43 is a current controlled current source amplifier.

Pages 74 to 75 derive the transfer function for this amplifier which is: -Io = GieXaGi Iin (1-#b)(n+1)BnGid#aGi If 1 - #b = o, the the above transfer function reduces to: -Io = Gie Iin nBGid ie the output is independent of Gi and any errors in or coupled to Gi donot appear at the output.

In accordance with the invention there is provided a current mode cicuit arrangment as in fig 43 comprising: - an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the first input of the said signal combining means G2 forming the current input of the said arrangment, with the second current output of the said current amplifier Gi forming the current output of the said arrangment.

In general -Io(s) = Gie(s)#a(s)Gi(s) Iin(s) (1-#b(s))(n(s)+1)+B(s)n(s)Gid(s)#a(s)Gi(s) with s=jw -Io(jw) = Gie#aGi(jw) Iin(jw) (1-#b(jw))(n(jw)+1)+BnGid#aGi(jw) If 1 - Xb(jw) = O ie |#b(jw)|= 1 ##b(jw) =#0 Then the above transfer function reduces to: -Io(jw) = Gie(jw) Vi(jw) B(jw)n(jw)Gid(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by xb(jw) the output current is independent of Gi(jw). For fig 42 to function correctly the signal path around the loop formed by B(jw).

Gid(jw).\a(jw).Gi(jw).n(jw) must be inverting.

Fig 44 Fig 44 is a voltage controlled current source amplifier Pages 8ttoslderive the transfer function for the amplifier which is: -Io = Gme#aGi Vi (1-#b)(n+1)+BnGmd#aGi If 1 -Ab = 0, then the above transfer function reduces to: -Io = Gme Vi BnGmd ie the output is independent of Gi and any errors in or coupled to Gi donot appear at the output.

In accordance with the invention there is provided a current mode cicuit arrangment as in fig 44 comprising: - an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second voltage inputs and a current output, the output of the said feedback means B whose output voltage is the input voltage of the second input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the

input of the said signal combining means G2 forming the voltage input of the said arrangment, with the second current output of the said current amplifier Gi forming the current output of the said arrangment.

In general -Io(s) = Gme(s)#a(s)Gi(s) Vi(s) (1-#b(s))(n(s)+1)+B(s)n(s)Gmd(s)#a(s)Gi(s) with s=jw -Io(jw) = Gme#aGi(jw) Vi(jw) (1-#b(jw))(n(jw)+1)+BnGmd#aGmd#aGi(jw) If 1 - #b(jw) = 0 ie )b(jw)J= 1 ##b(jw) =#0 Then the above transfer function reduces to: -Io(jw) = Gme(jw) Vi(jw) B(jw)n(jw)Gmd(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by Xb(jw) the output current is independent of Gi(jw). For fig 42 to function correctly the signal path around the loop formed by B(jw).

Gid(jw).#a(jw).Gi(jw).n(jw) must be inverting.

Fig 45 Fig 45 is a current controlled current source amplifier.

Pages 80to81 derive the transfer function for this amplifier which is: -Io = Gie#aGi Iin (1-#b)(n+1)BnGmd#aGi If 1 - #b = O, the the above transfer function reduces to: -Io =give Iin nBGmd ie the output is independent of Gi and any errors in or coupled to Gi donot appear at the output.

In accordance with the invention there is provided a current mode cicuit arrangment as in fig 45 comprising: an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having a voltage input, a current input and a current output, the the output of the said feedback means B whose output voltage is the input voltage of the voltage input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means el whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the current input of the said signal combining means G2 forming the current input of the said arrangment, with the second current output of the said current amplifier Gi forming the current output of the said arrangment.

In general -Io(s) = Gie(s)#a(s)Gi(s) Iin(s) (1-#b(s))(n(s)+1)+B(s)n(s)Gmd(s)#a(s)Gi(s) with s=jw -Io(jw) = Gie#aGi(jw) Iin(jw) (1-#b(jw))(n(jw)+1)+BnGmd#aGi(jw) If 1 - #b(jw) = 0 ie |#b(jw)| = 1 ##b(jw) =#0 Then the above transfer function reduces to: -Io(jw) = Gie(jw) Vi(jw) B(jw)n(jw)Gmd(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by #b(jw) the output current is independent of Gi(jw). For fig 45 to function correctly the signal path around the loop formed by B(jw).

Gid(jw).#a(jw).Gi(jw).n(jw) must be inverting.

Fig 46 Fig 46 is a voltage controlled voltage source amplifier Pages g6 to 87 derive the transfer function for this amplifier which is: -Vo = Gm1#a#dGr Vi 1-#a#b+B#dGr If 1-\aXb=0, then the transfer function reduces to: -Vo = Gm1#a Vi B ie the output is independent of Gr and any errors in Gr or coupled to Gr donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 46 comprising:an output amplifier Gr having a current input and a voltage output, a feedback means B whose input voltage is the output voltage of the said output amplifier Gr, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, an input means Gml whose voltage input is the voltage input to the said arrangment and whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the voltage output of the output amplifier

n XrrVv^q Gr othe voltage output of the said arrangment.

In general -Vo(s) = Gm1(s)#a(s)#d(s)Gr(s) Vi(s) 1-La(s)AbAs)+B(s))d(s)Gr(s) with s=jw -Vo(jw) = Gm1#a#d Gr(jw) Vi(jw) 1-#a#b(jw)+B#dGr(jw) If 1-#a#b=0 ##a(jw)#b(jw)|= 1 ##a(jw)+#b(jw)=#0@ Then the above transfer function reduces to: -Vo = Gm1(jw)#a(jw) Vi B(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by #a(jw).#b(jw) the output voltage Vo is independent of Gr(jw). For fig 46 to function correctly the signal path around the loop formed by B(jw).#d(jw).Gr(jw) must be inverting. Fig 46 can have an additional input transconductance means Gm2, which can be used to drive G1.

Gml and Gm2 can be combined into one means and provide a differential drive to G1 and G2. Alternatively a second input can be used in Gr and if this input is coupled to the output of Gm2 and Gm2 is coupled to the input a feedforward arrangment results.

Fig 47 Fig 47 is a current controlled voltage source amplifier Pages 26 to g7 derive the transfer function for this amplifier which is: -Vo = #a#dGr Iin 1-#a#b+B#dGr If 1-)aub=0, then the transfer function reduces to: -Vo = Aa Iin B ie the output is independent of Gr and any errors in Gr or coupled to Gr donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 47 comprising:an output amplifier Gr having a current input and a voltage output, a feedback means B whose input voltage is the output voltage of the said output amplifier Gr, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the second input of the said signal combining means G2 forming the current input of the said arrangment, with the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment In general -Vo(s) =#a(s)#d(s)Gr(s) Iin(s) 1-#a(s)#b(s)+B(s)#d(s)Gr(s) with s=jw -Vo(jw) =#a#d Gr(jw) Iin(jw) 1-#a#b(jw)+B#dGr(jw) If 1-#a#b=0 |#a(jw)#b(jw)|= 1 ##a(jw)+#b(jw)=#0 Then the above transfer function reduces to:: -Vo =#a(jw) Iin B(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by Aa(jw).\b(jw) the output voltage Vo is independent of Gr(jw). For fig 47 to function correctly the signal path around the loop formed by B(jw).#d(jw).Gr(jw) must be inverting. Fig 47 can also be provided with a second input which drives G1. This will allow the circuit to accept a differential input current drive. Alternatively a second input to Gr can be provided. This feedfordward connection when driven by an identical current as input &num;1 will reduce the signal level of Ic.

Fig 48 Fig 48 is a voltage controlled current source amplifier Pages 4; to qq-derive the transfer function for this amplifier which is: -Io = Gm1#a#dGi Vi (1-#a#b)(n+1)+Bn#dGi If 1-#a#b=0, then the transfer function reduces to: -lo = GmlXa Vi Bn ie the output is independent of Gi and any errors in Gi or coupled to Gi donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 48 comprising:- an output amplifier Gi having a current input and first and second current outputs, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, an input means Gml whose voltage input is the voltage input to the said arrangment and whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, with the second output of the said output amplifier Gi forming the current output of the said arrangment.

In general -Io(s) = Gm1(s)#a(s)#d(s)Gi(s) Vi(s) (1-#a(s)#b(s))(n(s)+1)+B(s)n(s)#d(s)Gi(s) with s=jw -Io(iw) = GmlXad Gi(jw) Vi(jw) (1-#a#b(jw))(n(jw)+1)+Bn#dGi(jw) If 1-#a#b=0 |#a(jw)#b(jw)|= 1 ##a(jw)+#b(jw)=#0 Then the above transfer function reduces to: -Io(jw) = Gm1(jw)#a(jw) Vi(jw) B(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by Ra(jw).\b(jw) the output current lo is independent of Gi(jw). For fig 48 to function correctly the signal path around the loop formed by B(jw).#d(jw).Gi (jw).n(jw) must be inverting.Fig 48 can have an additional input transconductance means Gm2, which can be used to drive G1.

Gml and Gm2 can be combined into one means and provide a differential drive to G1 and G2. Alternatively a second input can be used in Gi and if this input is coupled to the output of Gm2 and Gm2 is coupled to the input a feedforward arrangment results.

Fig 49 Fig 49 is a current controlled current source amplifier Pages 92 to 9 4 derive the transfer function for this amplifier which is:- -Io =#a#dGi Iin (1-#a#b)(n+1)+Bn#dGi If 1-#a#b=0, then the transfer function reduces to: -Io = Xa Iin Bn ie the output is independent of Gi and any errors in Gi or coupled to Gi donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 49 comprising:- an output amplifier Gi having a current input and first and second current outputs, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, the first output of the said signal combining means Cl whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the said signal combining means G2 whose output current is the input current of the first input of of the said signal combining means G1, the second input of said signal combining means G2 forming the current input of the said arrangment, with the second output of the said output amplifier forming the current output of the said arrangment.

In general -Io(s) =#a(s)#d(s)Gi(s) Iin(s) (1-#a(s)#b(s))(n(s)+1)+B(s)n(s)#d(s)Gi(s) with s=jw -Io(jw) =#a#d Gi(jw) Iin(jw) (1-#a#b(jw))(n(jw)+1)Bn@dGi(jw) If 1-laXb=0 |#a(jw)#b(jw)| + 1 |#a(jw)+#b(jw)=#0 Then the above transfer function reduces to: -Io =#a(jw) Iin B(jw)n(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by Aa(jw).\b(jw) the output voltage Vo is independent of Gi (jw). For fig 49 to function correctly the signal path around the loop formed by B(jw).#d(jw). G@(jw). @(@@) must be inverting.Fig 49 can also be provided with a second input which drives G1. This will allow the circuit to accept a differential input current drive. Alternatively a second input to Gi can be provided. This feedfordward connection when driven by an identical current as input &num;1 will reduce the signal level of Ic.

Fig 50 Fig 50 is a voltage controlled voltage source amplifier Pages qq to lOOderive the transfer function for this amplifier which is: -Vo = GmlXeGr Vi 1-#a#b+B#a#eGr If 1- > aXb=0, then the transfer function reduces to: -Vo = Gml Vi BBa ie the output is independent of Gr and any errors in Gr or coupled to Gr donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 46 comprising:an output amplifier Gr having a current input and a voltage output, a feedback means B whose input voltage is the output voltage of the said output amplifier Gr, a signal combining means G2 having first and second current inputs and first and second current outputs, a signal combining means G1 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, an input means Gml whose voltage input is the voltage input to the said arrangment and whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G2 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the voltage output of the output amplifier

Cr the voltage output of the said arrangment.

In general -Vo(s) = Gml(s)#e(s)Gr(s) Vi(s) 1-#a(s)#b(s)+B(s)#a(s)#e(s)Gr(s) with s=jw -Vo(jw) = Gml#eGr(jw) Vi(jw) 1-#a#b(jw)+B#a#eGr(jw) If l-a > b=0 |#a(jw)#b(jw)| =1 |#a(jw)+#b(jw)=#0 Then the above transfer function reduces to: -Vo = Gml(jw) Vi B(jw)a(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by Xa(jw).\b(jw) the output voltage Vo is independent of Gr(jw). For fig 50 to function correctly the signal path around the loop formed by B(jw).#a(jw).#e(jw) Gr(jw) must be inverting. Fig 50 can have an additional input transconductance means Gm2, which can be used to drive G1.

Fig 51 Fig 51 is a current controlled voltage source amplifier Pages

derive the transfer function for this amplifier which is: -Vo = XeGr Iin $1-#a#b+B#a#eGr If l-ab=0, then the transfer function reduces to: -Vo = 1 Iin B)ia ie the output is independent of Gr and any errors in Cr or coupled to Gr donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 51 comprising:- an output amplifier Gr having a current input and a voltage output, a feedback means B whose input voltage is the output voltage of the said output amplifier Gr, a signal combining means G2 having first and second current inputs and first and second current outputs, a signal combining means G1 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, the first output of the said signal combining means C2 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the second input of the said signal combining means G2 forming the current input of the said arrangment, with the voltage output of the said output amplifier Cr forming the voltage output of the said arrangment.

In general -Vo(s) = #e(s)Gr(s) Iin(s) 1-#a(s)#b(s)+B(s)#a(s)#e(s)Gr(s) with s=jw -Vo(jw) = #eGr(jw) Iin(jw) 1-#a#b(jw)+B#a#eGr(jw) If 1-#a#b=0 j > a(jw)b(jw)= 1 |#a(jw)+#b(jw)=|0 Then the above transfer function reduces to: -Vo = 1 Iin B(jw)la(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by #a(jw).#b(jw) the output voltage Vo is independent of Gr(jw). For fig 51 to function correctly the signal path around the loop formed by B(jw).#a(jw).#e(jw) Gr(jw) must be inverting. Fig 51 can also be provided with a secc input which drives G1.This will allow the circuit to accept a differential input current drive. Alternatively a second input to Gr can be provided. This feedfordward connection when driven by an identical current as input &num;1 will reduce the signal level of Ic.

Fig 52 Fig 52 is a voltage controlled current source amplifier Pages 105 to 107 derive the transfer function for this amplifier which is: -Io = Gmi#eGi Vi (1-#a#b)(n+1)+Bn#a#eGi If 1- > ab=0, then the transfer function reduces to: -Lo = Gml Vi BnAa ie the output is independent of Gi and any errors in Gi or coupled to Ci donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 52 comprising:- an output amplifier Gi having a current input and first and second current outputs, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G2 having first and second current inputs and first and second current outputs, a signal combining means G1 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, an input means Gm1 whose voltage input is the voltage input to the said arrangment and whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G2 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the said signal combining means Cl whose output current is the input current of the first input of the said signal combining means G@, with the second output of the said output amplifier Gi forming the current output of the said arrangment.

In general -Io(s) = Gml(s)#e(s)Gi(s) Vi(s) (1-#a(s)#b(s))(n(s)+1)+B(s)n(s)#a(s)#e(s)Gi(s) with s=jw -Io(jw) = Gml#eGi(jw) Vi(jw) (1-#a#b(jw))(n(jw)+1)Bn#a#eGi (jw) If 1-#a#b=o |#a(jw)#b(jw)|=1 |#a(jw)+#b(jw)=|0 Then the above transfer function reduces to: -IobJw) = Uml(jw) Vi(jw) B(jw)n#a(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by #a(jw).#b(jw) the output current Io is independent of Gi(jw).For fig 52 to function correctly the signal path around the loop formed by B(jw).#a(jw).#e(jw).@(@) Gitjw) must be inverting. Fig 52 can have an additional input transconductance means Gm2, which can be used to drive G1.

Gml and Gm2 can be combined into one means and provide a differential drive to G1 and G2. Alternatively a second input can be used in Ci and if this input is coupled to the output of m2 and Gm2 is coupled to the input a feedforward arrangment results.

Fig 53 Fig 53 is a current controlled current source amplifier Pages 105 to /07derive the transfer function for this amplifier which is: -lo = AeGi Iin $(1-#a#b)(n+1)+Bn#a#eGi If 1-#e#b=0, then the transfer function reduces to: -Io = 1 Iin SnAa ie the output is independent of Gi and any errors in Gi or coupled to Ci donot appear at the output.

In accordance with the invention there is provided a current mode circuit arrangment as in fig 53 comprising:- an output amplifier Gi having a current input and first and second current outputs, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G2 having first and second current inputs and first and second current outputs, a signal combining means G1 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means eJ1, the first output of the said signal combining means G2 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means Gl, the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the second input of said signal combining means G2 forming the current input of the said arrangment, with the second output of the said output amplifier forming the current output of the said arrangment.

In general -Io(s) = #a(s)Gi(s) Iin(s) (1-#a(s)#b(s))(n(s)+1)+B(s)n(s)#a(s)#e(s)Gi(s) with s=jw -Io(iw) = AaGi(iw) Iin(jw) (1-#a#b(jw))(n(jw)+1)+Bn#a#eGi(jw) If 1-)ab=0 |#a(jw)#b(jw)| = 1 |#a(jw)+#b(jw)=|0 Then the above transfer function reduces to: -Io = 1 Iin B(jw)n(jw))a(jw) ie with a gain of unity magnitude and zero phase shift around the signal loop formed by #a(jw).#b(jw) the output current lo is independent of Gi(jw). For fig 53 to function correctly the signal path around the loop formed by B(jw). #a(jw).#e(jw).@(@) Gi(jw) must be inverting. Fig 49 can also be provided with a secor input which drives G1.This will allow the circuit to accept a differential input current drive. Alternatively a second input to Gi can be provided. This feedfordward connection when driven by an identical current as input &num;1 will reduce the signal level of Ic.

Operational and transconductance amplifiers figs 54 to 59 Fig 54 is a V.C.V.S multiple loop feedback amplifier based on the arrangment in fig 40, but with the signal combining means G1 replaced by a differential input, single ended output input stage. Fig 55 is the same as fig 54 but with the general feedback means B replaced by a resistive potential divider.

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derive the transfer functions which are Vp = Gme#aGr Vi 1-#b+Bgmd#eGr and Vo = Gme#aGr Vi 1-#b+R1 Gmd#aGr R1+R2 The arrangments provide a non-inverting voltage gain and with 1 -#b=0 ie #b= 1/0 then::- Vo = Gm Vi BGmd or Vo = Gme = R1+R2.Gme = 1+R2.Cme Vi R1 Gmd Ri Gmd Ri Gmd R1+R2 Both arrangments therefore comprise an input transconductance stage driving an input current into G1 which is a positive feedback amplifier with the output current of G1 driving the output stage, which comprises a transresistance amplifier. The arrangments can be modified by having the current amplifier G1 replaced by the current amplifier in fig 2. This will allow the input transconductance stage to have a differential output driving b and c in fig 2.

Also G1 can be replaced by a positive feedback current amplifier with error feedforward gain correction as in fig 23. Figs 54 and 55 are infact operational amplifier arrangments providing high non-inverting gain. The open loop gain is given by: AVOL = Gm. #a . Gr 1-#b A typical output transresistance stage can be based on fig 141. The current amplifier sees a low input impedence load which is required for its maximum bandwidth and Q3 and Q5 provide a class AB drive to the two output mirrors. In this application the two mirrors are replaced by standard 3 transistor wilson current mirrors and a resistor R,is added from the output to ground to define the transresistance.With a gain of say x5 in the mirrors and with R =750 ohms, the gain Gr is 5x750 = 3750. A typical open loop gain with Gm=0.005, Gi = x1000 and Gr = 3750 equals x18750 which is 85.5dB. With a standard voltage buffer at the output to isolate the load from R and with voltage gain of 0.9 the gain reduces to x16875 which is 84.5dB.

Fig 56 is a V.C.C.S multiple loop feedback amplifier based on the arrangment in fig 44 but with the signal combining means C2 replaced by a differential input, single ended output transconductance input stage. Fig 57 is the same as fig 56 but with B replaced by Ri.

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derive the transfer functions which are : Io = GmeXaGi Vi (1-#b)(n+1)+nBGmd#aGi and Io = GmeXaGi Vi (1-#b)(n+1)+nRlGmd#aGi both arrangments provide a non-inverting transconductance gain and with 1-#b=0 de #b = 1/0 : lo = Gme Vi nBGmd and Io = Gme Vi nRlGmd Both arrangments therefore comprise an input transconductance stage driving an input current into G1 which is a positive feedback amplifier with the output of G1 driving the output stage.The output stage consists a current amplifier and a current sampler which produces main and aux output currents.

The arrangment can be modified by replaceing G1 by the current amplifier in fig 2. This will allow the input transconductance stage to have a differential output driving b and c in fig 2. Also G1 can be replaced by a positive feedback amplifier using error feedforward gain correction as in fig 23.

The transconductance amplifiers in figs 56 and 57 are detailed more fully on page 144 and page 139 illustrates a number of end products.

Fig 58 is a V.C.V.S multiple loop feedback amplifier based on the arrangment in fig 40 but with G1 replaced by a differential input, single ended output transconductance stage and configuered to produce an inverting voltage gain Pages

d;2/nlC / to//qthe transfer function which is: -Vo = R2GmeXaGr Vi (1-#b)(R1+R2)+R1Gme#aGr and with 1 - #b = 0 ie #b = 1/0 Vo = -R2 Vi R1 The arrangment therefore comprises an input transconductance stage driving an input current into G1 which is a positive feedback amplifier with the output current of G1 driving the output stage, which comprises a transresistance amplifier.The arrangments can be modified by having the current amplifier G1 replaced by the current amplifier in fig 2. This will allow the input transconductance stage to have a differential output driving b and c in fig 2.

Also G1 can be replaced by a positive feedback current amplifier with error feedforward gain correction as in fig 23. Figs 54 and 55 are in fact operational amplifier arrangments providing high inverting gain. The open loop gain is given by: AVOL = Gm. Xa . Gr A typical output transresistance stage can be based on fig 141. The current amplifier sees a low input impedence load which is required for its maximum bandwidth and Q3 and Q5 provide a class AB drive to the two output mirrors. In this application the two mirrors are replaced by standard 3 transistor wilson current mirrors and a resistor R,is added from the output to ground to define the transresistance.With a gain of say x5 in the mirrors and with R =750 ohms, the gain Gr is 5x750 = 3750. A typical open loop gain with Gm=0.005, Gi = xlOOO and Gr = 3750 equals x18750 which is 85.5dB. With a standard voltage buffer at the output to isolate the load from R and with voltage gain of 0.9 the gain reduces to x.16875 which is 84.5dB.

Fig 59 is a V.C.C.S multiple loop feedback amplifier based on the arrangment in fig 44 but with G2 replaced by a differential input, single ended output transconductance stage and configured to produce an inverted gain.

The multiple loop feedback amplifiers of figs 34 to 53 can be either inverting or non-inverting as required, with the signal combining means G1 and G2 when shown as all current input means implemented as current mirrors . In the case of figs 34 to 45 G1 is implemented using two current mirrors and for figs 46 to 53 G1 is a current mirror and G2 is a current mirror. Each mirror is arranged to have one or more outputs as required by each circuit arrangment and in the case of figs 34 to 45 with two mirrors used to implement G1 the inputs can be coupled to the input of the first current mirror or to the input of the second current mirror.Also for figs 34 to 45 either mirror can drive the output amplifier Gi or Gr. In the case of the arrangments in figs 34, 35, 37, 47, 49, 51 and 53 the the input directly drives the G1 or G2 therefore either the drive source must have sufficiently high output impedence so as not to load the positive feedback loop around the to mirrors or G1 or G2 must contain a current buffer to isolate the positive feedback loop from the drive source.

Current samplers Fig 64 and 65 comprises two circuit arrangments in a semi-block diagram form which have secondary output currents which are some linear portion of there main output current. Fig 64 is an arrangment in which the secondary output is output &num;1 and provides a current output which is ditermined by the input current and the the ratio of R1 over R2 and assuming ideal circuit operation: Io&num;1 = 9 Pa Io&num;2 R1 The above equation is valid if two conditions are met which are: (1) The voltage difference between node 1 and node 2 is zero volts.

(2) The signal current into the emitter of Q1 is equal to the output current from the secondary output &num;1.

Block A comprises Ql, 2, CSl and CS2.

The ideal characteristics for block A to satisfy these above conditions must be a unity current gain from the emitter of Q1 to its secondary output &num;1, zero input impedence looking into the emitter of Q1 and infinite input impedence looking into the emitter of Q2.

For an input signal current of lOlmA into the input &num;1 for example, with Rl=l00Oohms and R2=10ohms and assuming block A is ideal the voltage drop across R1 equals the voltage drop across R2, as the voltage drop between nodes 1 and 2 is zero.

The current splits up with lmA flowing through R1 and lOOmA slowing through R2, giving an output current from o/p&num;1 of lmA and an output current from O/P&num;2 of lOOmA therefore Io&num;1 = R@ = 10 ohms = 1mA Io&num;2 Rt 100 Oohms lOOmA With Q1 and Q2 having matched Vbe for the same collector current, the circuit block A must maintain the collector currents of Q1 and Q2 at the same value.To do this block has additional circuitry ( not shown ) which maintains Ic(Q1)=IclQ2) and also gives the low (ideally zero ) input impedence into the emitter circuit of Q1 and high (ideally infinite ) input impedence into the emitter circuit of Q2.

Fig 60,61,62 and 63 are examples of circuitry suitable for implementing block A in a more detailed form. For fig 60, Q1 and Q2 represent Q1 and Q2 in fig 64 with the addition of Q3. For fig El Q1 and Q2 represent Q1 and Q2 in fig 64 with the addition of Q3 and Q4. For fig 62 Q1 and Q2 represent Q1 and Q2 in fig 64 with the addition of Q4. In fig 63 Ql and 42 represent Q1 and Q2 in fig 64 with the addition of Q3, Q4 and Q5.

The current sinks CSl and CS2 provide quiecent currents for Q3 and Q2 respectively and are chosen to provide substantially equal currents. Node 3 in figs 60, 61 62 and 63 is the secondary output &num;1 and node 4 is connected to a current source which provides quiescent

current^Q2 and/or Q2 and Q4, of a substantially equal value to the current provided by CS2.The arrangments in figs 60, 61, 62 and 63 have a finite dynamic input resistance which would typically be 25ohms, dependent on the emitter currents, so to obtain a required ratio of output current to secondary output current R1 or R2 would be trimmed ( Rin adds to the value of Ri In accordance with the invention there is provided a current mode circuit arrangment comprising a current sampling means with first and second transistors, the base of the first said transistor being coupled to the base of the second said transistor, first and second resistors, with the first end of first said resistor being coupled to the emitter of the first said transistor and the second end of the first said resistor forming the first input of the said arrangment, the second said resistor whose first end is coupled to the input of the said arrangment and whose second end is coupled to the emitter of the second said tansistor and whose second end forms the second output of the said arrangment, the first said transistor whose collector current is substantially equal to the output current of the first output of the said arrangment, the input impedence into the emitter of the first said transistor being low relative to the input impedence into the emitter of the second said transistor, the second said transistor whose collector current is substantially equal to the input current of the second input of the said arrangment, the output impedence of the first output of of the arrangment being high relative to the input impedence into the emitter of the first said transistor, first current supply means coupled to the emitter of the first said transistor, second current supply means coupled to the emitter of the second said transistor.

Fig 65 is the same as fig 64 but with the I/P &num;1 and the O/P&num;2 transposed, ie the I/P&num;1 is now the O/P&num;2 and the O/P&num;2 is now the input &num;1. All the previous analysis for the circuit arrangment in fig 64 can be applied to fig 65. Figs 60, 61, 62, 63, 64, and 65 can be implemented using PNP transistors and in this case the common connections to CSl and CS2 are connected either to a positive supply or ground, whereas the NPN versions are connected to a negative supply or ground. In practice the NPN and PNP transistors can be replaced with the appropriate conductivity type field-effect transistors in figs 60, 61, 63, 64 and 65 and the same circuit functions will be obtained.

A more detailed current sampler is shown in fig 66 which provides bipolar output currents. This is based on the basic circuit of fig 64. The basic sampler consists of Q1 to Q5 with Q1 and Q2 being the transistors of fig 64 and Q3 to Q5 added to ensure the quiescent current is the same in Q1 and a2. Q2 is diode connected so that the voltage drop across diode connected transistor Q3 and Q4 minus the base emitter voltage Q5 sets its collector current. CSl provides bias current for Q3 and Q4 and by the appropriate chose of CSi and the emitter areas of Q3 and Q4, IC(Q1) = IC(Q2), Q6 and Q7 provide level shifting so enableing the output sampled current from Ql to drive a grounded load.

The current sinks CS3 and CS4 are matched, with the current supplied by CSl being equal to the sum of CS2 and CS3. R1 and R2 set the ratio of sampled to output current and typically R1=lKohm and R2 10ohm, with an output swing of + or - lOOmA and I sample of + or - 1mA.

This circuit can also be implemented using PNP devices or MOSFETS of either conductivity type, with the appropriate supply rail polaritys. Figs 60 to 62 can also be used in fig 66 but with an additional current sink from the positive supply rail to input 4 to supply bias current and again can implemented using using PNP or MOSFET devices.

1st modifcation to the Current Sampler The circuit arrangment must have a zero voltage differnce betwwen the nodes 1 and 2 if the outputs 1 and 2 are ditermined solely by the ratio of R1 and R2 t assuming matched vbe for Q1 and Q2 ). To achieve this a 1st modification is prosposed for figs 64 an 65 whereby an additional circuit means is provided which senses the collector current of the first npn transistor Q1 and forces the collector current of the second npn transistor Q2 to equal to the collector current of the first npn transistor, so that as the collector current of Q1 increases or decreases due to the signal current the collector current of Q2 tracks it.

With Q1 and Q2 having sustantially equal vbe the voltage between nodes 1 and 2 is zero. Q2 collector current tracks Q1 collector current over the complete input current signal range and thus effectively cancels the finite dynamic input resistance looking into the emitter of Q1.

This modification therefore improves the gain accuracy as defined by R1 and R2 and also increases the linearity of the current sampler.

Fig 67 is a circuit diagram of a current sampler suitable for driving positive going currents into a load.

Q11 to Q14 form the first circuit means with Q1 to Q8 comprising the first modification. Q1 to Q4 maintain the the voltage difference between the emitters of Q5 and QE at zero volts therefore Q5 to Q8 act as a current mirror forceing the collector current of Q14 to be equal to that of w1: V1 provides a bias voltage to Q1 and Q2 and maintains a sufficient voltage difference between the collector of Qil and the collector Q8 to ensure the collector/base junction of Qll and Q8 are reversed biased. Q9 and Q10 with CS1, CS2 and V3 provide level shifting.Q15 and Q16 with V2 are added to isolate the sampler from the load which ensures greater sampler gain accuracy and linearity.

The relationship between the feedback current and the output current is given by: I(out) = R1 -1 I(f/b) R2 Therefore if R1 = lOlOohms and R2 = 10ohms I(out) = 1010 - 1 = 100 I(f/b) 10 Figs 68 to 72 are results of a typical PSPICE simulation of fig 67, with RL=250ohms, Vs=15V, R1=101Oohms, R2=lOohms and with a feedback load of 6000hms.

Fig 70 plots the deviation from the ideal transfer characteristics given by (R1/R2)-1 and indicates a value of 99.9998 . This simulation therefore shows a very high degree of sampler accuracy.

The linearity of this arrangment is also very high with a peak to peak deviation of O.85nA for an output current swing of 4mA to 20mA ie 16mA. Nonlinearity is specified to be a peak deviation from a "best fit" straight line, expressed as a percent of peak to peak full scale output.

Therefore with a 16mA output swing the feedback current is: If (Peak to Peak) = 16mA 99.9998 = 1.6000032x10-4 Therefore the nonlinearity of the feedback current is: = (0.85x10-9)/2 x 100 1.6000032x10-4 = 0.000026 7.

Fig 68 is a frequency responce plot of the sampler and shows a flat responce for both I(RL) and I(RF)/I(RL). I(RL) is to within O.ldB up to 10Mhz and I(RF)/I(RL) is -40dB and flat to within ldB up to 10Mhz. Fig 69 is a phase shift plot and indicates for I(RL) a phase shift of < 5 degrees up to 10Mhz and < 25 degrees up 10Mhz for ICRF). Fig 72 is the square wave responce at the load and indicates a fast, clean responce. Fig 71 is the square wave responce of the sampled current and again shows a clean responce with minumum overshoot.

Fig 73 is a second example of a current sampler with the first modification. Q11 to Q14 comprises the basic sampler ( see fig61 with Ql to Q8 being the additional circuit means, with V1. Q1 to Q4 maintain the voltage difference between the emitters of Q5 and Q6 at zero volts therefore Q5 to Q8 together act as a unity current gain mirror forceing the collector current of Q14 to equal that of Q13. The rest of the circuitry functions in an identical manner to the fir-st example.

Figs 74 to 78 are the results of a typical PSPICE simulation of fig 73 with RL=2500hms, Vs=15V, R1=lOloohms, R2=lOohms and with a feedback load of 6000ohms.

Fig 76 plots the deviation from the ideal transfer characteristics given by (R1/R2)-1 and indictes a a value of 100.0027 The linearity is very good with a peak to peak deviation of 1.7nA for a output current swing of 4mA to 20mA ie 16mA.

Therefore with a lEmA output swing the feedback current is: If @ peak to peak )=16mA =1.599956x10-4 100.0027 The nonlinearity of the feedback current is: =(1.7x10-9)/2 x100 1.599956x10-4 =0.00053 Fig 74 is a frequency responce plot and shows IeRL) flat to within û.ldB up to 10Mhz and I(RF)/I(RL) is -40dB and flat to whthin 1dB up to 10Mhz.

Fig 75 is a phase plot and indicates for I(RL) < 5 degress up to 10Mhz and < 15 degress for I(RF) up to 10Mhz.

Fig 78 is the square wave responce at the load and shows a clean responce Fig 77 is the square responce of the feedback current and again shows a clean responce with minumum overshoot.

2nd Modification to the Current Sampler As previous mentioned the current sampler must have zero voltage difference between nodes 1 and 2 if the outputs 1 and 2 are ditermined solely by the the ratio of R1 and R2 ( assuming matched vbe for Q1 and Q2 ). To achieve this a 2nd modification is proposed for figs 64 and 65 whereby an additional circuit means is provided which is responsive to the signal current to the arrangment and provides a feedforward current into the second input of block A of figs 64 and 65 This correction current is of 8. magnitude which tracks the collector current in Q1 so that as the collector current of Q1 increases or decreases due to signal current the feedforward current also increases or decrease.With Q1 and Q2 having equal vbe the voltage between nodes 1 and 2 is zero. The additional circuit means provides this correction current over the complete input signal range and thus effectively cancels the finite dynamic input resistance looking into emitter circuit of Q1.

This modification therefore improves the gain accuracy as defined by R1 and R2 and also increases the linearity of the arrangment. Fig 79 is a circuit diagram of the proposed modified arrangment. The additional circuit means comprises Block B, (Q3,Q4,CS3,CS4) current mirror M1, CSl and 53. L3ue to the identical circuits for blocks A and B the current from the first output of block B is sustantially equal to the current from the out of the first output of block A.

This current from the output of block B is mirrored by M1 and provides the feedforward current into the second input of block A. This feedforward current forces the collector current of Q2 to equal that of Q1, so that as the collector current of Q1 increases or decreases with input signal current Q2 collector currnet tracks it.

R1 = R3 for the feedfoward to work correctly, with the currents supplied by CS1, CS2, CS3, CS4 and CS5 being matched. The relationship between the output currents is given by: Io&num;2 = I(o/p) = R1 - 1 Io&num;1 I(f/b) $2 Therefore if R1=lOlOohms and R2=10ohms Io&num;2 = 1010 - 1 =100 Io&num;1 10 This sampling arrangment can also be implemented pnp transistors of mosfets of either conductivity type with the appropriate selection of supply voltages.

Fig 80 is a more detailed implementation of fig 79 using the circuit arrangments in fig 62 . The block A comprises Q9 to Q12, block B comprises Q5 to Q8 and mirror M1 comprises Q1 to Q4 and has a unity current gain.

Additional components CS6, CS7, Q13 O14, and Vb1 are included to provide the function of level shifting so the feedback current can drive a grounded load with negative or positive going currents.

Figs 81 to 85 are typical PSPICE simulations of fig 80 with R1=10ohm, R2=R3=1Kohm, CS1 to CS5 = 1.5mA, CS6=1mA, CS7=2.5mA, RL+100ohms, Rf=600ohms, +Vs=15V, -Vs=15V and transistor ft of 800Hhz.

Fig 85 plots the deviation from the ideal transfer characteristics given by (R1/R2)-1 and indicates a value of 98.94 which can be improved by trimming R1. The plot also indicates a peak to peak deviation of 560nA for the feedback current for an output current swing of + or - 50mA.

Therefore with a lOOmA output swing the feedback current is: If( peak to peak ) = lOOmA 98.94 = 1.0107mA The nonlinearity of the feedback current is:- =(560x10-93/2 1.0107x10-3 =0.028% Fig 83 is a frequency responce plot and shows a flat responce to within +4dB up to 100Mhz for I(RF)/ICRL) and +1.5dB to 100Mhz for I(RL).

Fig 84 is a phase plot and indicates for I(RL) < -15 degress phase shift up to 100Mhz and within + or - 12 degrees phase shift for I(RF) up to 100Mhz.

Fig 81 is the square wave responce for I(RL) and indicates a fast clean responce.

Fig 82 is the square wave responce for I(RF) and again indicates a fast clean responce.

Current Samplers with load isolated Bipolar Outputs Figs 86 to 90 are a number of current sampling circuit arrangments that provivde bipolar current outputs. These samplers have two current inputs &num;1 and &num;S, and two current outputs &num;1 and &num;2. Blocks A and B use the same circuit topology as in fig 64 and 65 , with a PNP or PMOS version of fig 64 being used in figs 86, 88 and 8g and a NPN or NMOS version of fig 65 being used in figs 86, 88 and 89. Figs 87 and 89 use a PNP or PMOS version of fig 65 with figs 87 and 89 using the NPN or NMOS version of fig 65.

The input currents into the inputs &num;1 or &num;2 are either from a class A or AB current output amplifier typically supplying 4mA to lOOmA ( class AS ). QI to Q4 isolate the sampling circuitry from the load impedence which results in greater sampling accuracy. With the input current increasing into the input &num;1, the f/b current increases and also the collector current of Q1 and Q2 increases. The output and f/b currents are therefore positive going. Like wise for for input &num;2, an increase in this current produces negative going f/b and output currents.

CSl and Ct2 are added to increase the quiescent currents of blocks A and B so that the dynamic input resistance is reduced into the emitters of Q ( Qi as in fig 587 ). Also the the total signal current swing is a smaller proportion of the emitter current of Q1 giving greater sampling linearity.

The advantages of these arrangments over the basic current sampler is that due to the transistors Q1 to Q4 capacitive loads for example will not effect the frequency/phase responce from the inputs &num;1 and &num;2 to the f/b output. Fig 90 is different from the preceding in that block A is based on NPN or NMOS versions of fig 64 and block B is based on a PNP or PMOS version of fig 64. Fig 90 has additional components comprising Q5 to Q7, CS3 and CS4 which provide the function of level shifting and so enabling the two sample currents from blocks A and B to sum into a grounded feedback load. The blocks A and B can utilise the the 1st and 2nd modifications and can also be modified by using a single pnp and npn in place of Q1 to Q4 or a single high current pmos or nmos device ( eg DMOS devices ).For blocks A and B without the 1st or 2nd modifications the transfer functions for the two inputs are:- IMoXp) = Rl(a) for the first input I(f/b) R2(a) I(o/p) = = Rl(b) for the second input I(fXh) R2Cb) For blocks A and B with the 1st or 2nd modification the transfer functions for the two inputs are: ICo/p) = Rl(a) -1 for the first input I(f/b) R2(a) I(o/p) = Rl(b) -1 for the second input I(f/d) R2(b) Figs 91 to 93 are three more detailed current samplers.

Fig 91 is based on the arrangment in fig 90. Blocks A and B use the circuit in fig 61 ie Q17 to Q20 and Q21 to Q21 form the basic sampler (see fig 64) with the first modification implemented csee fig 67).

Fig 92 is based on the arrangment in fig 86 and uses the second modification (see fig 80) Fig 93 is based on the arrangment in fig 86 but with blocks A and B forth connections grounded and using the arrangment in fig 63.

Figs 94 to 101 are typical PSPICE simulations of fig q3.

with R1=R3=lKohm, R2=R4=lOohms, I1=I2=1.5mA, I3=150uA, Q5, QE, Q7, Q9 with xO.1 the emitter area of Q2, Q4, Q8 and Q10, +Vs=15V, -Vs=-15V and RL=lOohms.

Fig 94 is a plot of load current verses feedback current and indicates a gain ratio of 100 for positive load currents.

Fig 95 is a plot of load current verses feedback current and indicates a gain ratio of 100 for negative load currents.

Fig 96 is the load square wave responce with a output swing of + or - 1mA and indicates a fast clean responce Fig 97 is the feedback square wave responce with the above output swing and indicates a fast, clean responce with minumum overshoot.

Fig 98 is the load squarewave responce with an output swing of + or - lOOmA and again indicates fast, clean responce with no sign of slewrate limitation.

Fig 9 is the feedback responce with the above output swing again with excellent clean, fast responce of + or - lama.

Fig 100 is a frequency plot for I(RL) and I(RF)/I(RL), with a -3dB point off over 100Mhz for IeRLv and 8oMhz for I(RF)/I(RL).

Fig 101 is a phase plot for I(RL) and I(RF), with both responce showing less than 18 degress phase shift up to 50Mhz.

Products using current samplers and/or M.L.F.As Fig 102 and fig 103 are transconductance amplifiers with current feedback .Fig 102 is a noninverting configuration and fig 103 inverting. Both circuits comprise a differential, high input impedence, transconductance amplifier with dual current outputs. The main current output provides drive current to the load and the secondary output provides a feedback current which is some linear proportion of the main output current. For example if the main output current is + or - 100mA the feedback current would typically be + or lama. This feedback current provides a feedback voltage by passing through R1 and therefore defines the overall transconductance with feedback.The feedback current is obtained by any of the previous current samplers and the internal transconductance gain stage can be based on a appropriate multiple loop feedback amplifier. The amplifiers can also be designed such that they operate from single positive or negative supplys and would be most likely implemented as monolithic integrated circuits in BIPOLAR, CMOS or BICMOS technologies.

Fig 110 and fig 111 are differential input, voltage/current output amplifiers .Fig 110 is a basic arrangment with an inverting input (Vl) and a noninverting (V2) and a. current output. This circuit is the same as in fig 102 but without the + input grounded. This basic arrangment provides a very high C.M.R.R due to the lack of resistor matching ( which is required in the classical operational amplifier 4 resistor differential amplifier) and is only limited by the inherent matching of the + or - input gains. C.M.R.R as high as 120dB or more

possible wilh the new circuit.

Fig 111 is based on fig 110 with the addition of Al and A2 which are standard operational amplifiers. These op amps provide equal input impedences and provide some differential voltage gain with unity common mode gain. The output can be taken directly from A3 (current output) or A4 (voltage output).

Figllb is a transconductance amplifier configured as a current transmitter .This circuit is configured to operate from a positive supply rail and provide positive currents but it can also be configured to run from a negative supply with the positive rail grounded and the negative rail connected to a negative supply, and therefore sinking current through a load.

Fig 114 is a transconductance amplifier configured as a instrumentation amplifier/differential input current transmitter The circuit configuration is the same as that in fig 111 but supplied from a positive supply and therefore only able to supply positive output currents, also CS1 is added which provides an output offset current when for example a current span of 4mA to 20mA is required.

Fig 116 and fig 117 are differential voltage/current input dual current output transconductance amplifiers, with fig 116 configured in a non-inverting mode and fig 117 in an inverting mode. Fig 116 and 117 can also be supplied from a single positive or negative supply rail. Both circuits consist of a non-inverting voltage ( high impedence ) input and an inverting ( low impedence) input. The main current output provides drive current to the load and the secondary output provides a feedback current current which is some linear proportion of the main output current.

For example if the main output swing is + or - lOOmA then the feedback current would typically be + or - lmA. This feedback current provides a feedback voltage by passing through R1 and therefore defines the overall transconductance. The feedback tries to force the the voltage between the inputs to zero, the very small voltage difference resulting in a input current into the inverting current input. It is this input current that is amplified by an internal high gain current amplifier to produce the output/feedback currents. The arrangment is based on a multiple loop feedback amplifier (see fig 42) and the internal current sampler can be any of the previously detailed arrangments. This circuit arrangment is best implemented as a monolithic integrated circuit in either BIPOLAR, CMOS or BI CMOS technologies.

Fig 129 and fig 130 are voltage input transconductance amplifiers configured to provide voltage gain, with fig 129 providing non-inverting gain and fig 130 inverting gain.

Under high load capacitance coditions Cc is added which cancels the load pole by a responce zero. Voltage gains up to at least x200 can be obtained by these circuits, with bandwidths to at least 100Mhz. Therefore the gainbandwidth products of these configurations can be as high as 20 Ghz or more, a figure totally unobtainable with present art voltage and current feedback operational amplifiers with the best voltage op amp capable of around 5Ghz and current feedback op amps capable of voltage gains of x50 at bandwidths ot 80Mhz ie a G.B.P of 4Ghz.

The voltage gain is ditermined by the value of RL for these amplifiers but with the addition of a open or closed loop buffer at the output this limitation is removed.

These circuit arrangments are relatively uneffected by load capacitance (output buffer not connected ) with regard to phase and gain margins due to the load isolation of the output sampler. The load time constant will reduce the bandwidth but with the addition of Cc this effect is cancelled and the overall bandwidth is ditermined by the bandwidth of the transconductance amplifier.

Fig 139 and fi9 140 are non-inverting transconductance amplifiers with errorfeedforward gain correction These arrangments are suitable for higher output current levels and/or when the high current output stage needs to be eliminated from the feedback loop so as to increase the overall bandwidth of the amplifier. The amplifier A3 can also be configured in an inverting mode therefore producing an inverting arrangment. The arrangment can be gated off if required by removing the bias voltages Vbl and Vb2 which are normally negative with respect to +Vs for Vbl and positive with respect to -Vs for Vb2, by forceing these voltages to +Vs and -Vs respectively.

Fig 144 and fig 145 are transconductance amplifiers with an additional input control labeled output enable These general circuit diagrams illustrate the general concept of controlling the output current by directing it to the load or to ground/supply rails.

Fig 146 are two transconductance amplifiers with output gateing, driing three current buses . Each input can be directed to one of three current buses which have resistive loads i not shown ) in the simplest case. If any i/p needs to drive more than one bus then the output gateing can be arranged such that if Q3 and Q6 only are switched on for example then two other switched complementary pairs are switched on which feed 2/3 of the output current to ground. If Q2 and Q5 are also switched on to drive bus &num;2 as well then only one of the additional complementary pairs are switched on driving 1/3 of the output current to ground.

If all outputs are switched on driving all three buses then non of the additional two pairs are switched on and each bus sees a 1/3 of the output current.

Fig 102 Fig 102 comprises a differential input, dual current output transconductance amplifier, connected to give a non-inverting, feedback transconductance amplifier.

The transconductance with feedback for this arrangment is derived on pages

/v6 to 148and is: Io= (Gml+Gm2) + (Gm1-Gm2) Vi 2K 2K Where K=1+n(1+R1Gm2) Cml is the transconductance of the non-inverting input Gm2 is the transconductance of the inverting input n is the ratio of the output current to the feedback current The term Gml+Gm2 is the differential gain 2K The term Gml-Gu2 is the common mode gain 2K Simplefing by assuming the commmon mode gain is zero gives Io=2Gm=Gm Vin 2K l+n(1R1Gm) Fig 102 has an internal topology which can be based on the Multiple loop feedback arrangment illustrated in fig 56 The Transfer function for fig 102 is derived on pages

and is: : Io= Gme#aGi Vi (1+n)(1-#b)+nss Gmd#aGi now Io= GmeXa Vi (1-#b)(1+n)+nss Gmd#a Gi and using typical values for the above parameters Gme=Gmd=0.01,#b=0.999, n=0.01, #a=1, Gi=50, and with Rf=6000hms and lOKohms Io=O.O1 Vi (1-O.999)(1+0.01)+0.Olx600xO.01 50 Io=0.01 Vi 2.02E-5+0.06 Io= 0.01 = 0.16661057 Vi 0.0600202 If Xb=l Then Io= 1 =0.166666 Vi 6 % error=0.034%=-0.0029dB If Rf=lOKohms Io=O.Ol =9.999798E-3 Vi 2.02x10-5+1 IfAb=1 then Io= 1 = 0.01 V1 100 %error=0.00202%=-0.000175dB From the above results it can therefore be seen that for typical closed loop gains of 0.166S and O.O1S the gains are very close to the ideal (the ideal being b=l).

Fig 103 Fig 103 comprises a differential input,dual current output transconductance amplifier, connected to give an inverting feedback transconductance amplifier. The transfer function for this circuit arrangment is derived on pages

and is: -Io = Gm Vin 1+n(1+RlGm) where Gm is the transconductance for the inverting input n is the ratio of the feedback current divided by the output current.

Fig 103 can have an internal circuit topolgy based on the multiple loop feedback arrangment as described on page 111 and illustrated in fig 59. The transfer function for fig 59 is: -Io=GmeXaGi Vin (1-#b)(1+n)(nGmeR1#aGi -Io=GmeXaGi Vin l-b 1+n(1+R1Gme#aGi) 1-#b where GmeXaGi=Gm 1-#b Typical values for the circuit elements would be Gme=0.01, #b=0.999 ie a loop gain accuracy from unity of 0.17., n=O.Ol #a=1 and Gi=50 now -Io=Gme#aGi Vin (1-#b)(1+n)+nGmeR1#aGi Using typical a value for R1 of 6000hms:: -Io= u.Olx50 Vin (1-0.999)(1+0.01)+0.01x0.01x600x50 -Io= O. 5 = 0.166610574 Vin 1.01 E -3 +3 If #b =1, then -Io = 1 Vin nR1 -Io = 1 = 0.166666666 Vin 0.01x600 error = 0.0347. = - 0.00292dB If R1 equals lOKohms -lo = 0.5 = 9.998798E-3 Vin l.OlE-3 + 50 If #b = I, then -Io = 1 = 0.01 Vin O.OlxlOE+3 % error = 0.00202% = -0.00175dB From the above results it can therefore be seen that for typical closed loop gains ot 0.1665 and 0.015. the gains are very close to the ideal (the ideal being #b=1).

Fig 104 and fig 105 are typical internal circuit arrangments for the transconductance amplifiers of figs 102 and 103. Fig 104 consists of Q5 and Q6 which provide the differential input stage with CS1. The drive circuits are coupled to the positive feedback amplifier comprising Q8 to Q18 by the common base amplifiers Q7 and 48. A single ended output is taken from M1 t QS to Q 13 ) via Q12 and drives an output current into the emitters Q4 and Q19.These two transistors provide a class AB drive current from there collectors when driven by the class A collector current of Q12. The collector current of Q4 is coupled to the output current amplifier comprising Q1,Q2,Q3,R1,R2 and R10 which a positive output current as the collector current of Q4 increases. Likewise the collector of Q19 is coupled also to an output current amplifier comprising Q21,Q22,Q17,R11,R12 and R7 which provides a negative output current as the collector current of Q19 increase. CS3 provides a minumum input current to these two output mirrors so that the main output devices Q3 and 417 are always conducting and therefore operate in true class AB.

The outputs &num;1 and &num;2 provide the output currents for the load via the output current sampler and would typically provide 4mA to lOOmA for a collector current swing of 2mA for Q12 Fig 105 is the current sampler and is the same circuit as in fig 93. The outputs &num;1 and &num;2 are coupled to the inputs &num;1 and A2 respectivEly and drive the sampler such that an current is obtained from the output. Fig 105 is described on page 138 and can be referred to. The feedback current is taken from the collectors of Q1 and Qil and is typically +or - imA for a output current swing of + or Fis 106 to 110 are PSPICE simulations of a typical circuit.

Fig 106 is the closed loop transfer characteristics with figs 104 and 105 configured as in fig 102 ie non-inverting.

The feedback resistor is 600ohms, resulting in a gain of 0.1665. The circuit easily provides over + or - lOOmA into lOohms, with very high linearity due to the high open loop transconductance 2 Gm x n ) of over 255. Fig 107 is a bode frequency plot of output current verses input voltage and indicates a bandwidth of 10Mhz. Fig 108 is the same amplifier when driven by a square wave, giving an output of + or 20mA and showing a good responce with a settling time under 400nS to 0.1% . Fig 109 is the same amplifier with an ouput swing of + or - lOOmA and indicates a very high slew rate of 4A/uS.

Figs 174 and 175 are additional plots which show the frequency and time responces of the amplifier with the addition of a small lOpF ) capacitor across Ri. This capacitor provides a zero in the responce and increases the bandwidth to over 20Mhz.

Figs 177 to 180 are results of the same non-inverting amplifier with R1=lOOohms ( figs 177 and 178 ) and R1=lKohm ( figs 179 and 180 ). For R1=100ohms fig 177 shows a bandwidth of 20Mhz and fig 178 shows a fast settling square wave responce of 400nS to .1, with a transconductance of 15. For R1=lKohm fig 179 shows a bandwidth of around 22Mhz and fig 180 shows a settling time of 400ns to 0.1%, with a transconductance of 0.15.

Frequency compensation is obtained by placeing a series CR network across the + and - inputs, with Rl=lOOohms R=25ohms, with R1=6O0 R=2Oohms and with R=lKohm R=l5ohms. In all cases C= 700nF. This simulation uses transistor FT,s of typically 800Mhz. +Vs=15V, -Vs=-15V, RL=100ohms (for +or -100mA outputs RL=lOohms ), RS=S0ohms and with a quiescent supply current of 8mA. This circuit would ideally be implemented as a integated circuit with the option of Q3 and Q17 being external to the package, enabling much high output current levels to be obtained.

The positive feedback current loop (Ml and M2) would be trimmed by adjustment of one of the mirror emitter resistors,ie laser trimming one of the thin film resistors R3 to R8. In production R3 or R6 would be lower in value to R4, R5 and R8 giving a loop gain considerable less than unity and therefore zero yield to parametric specifcations. Laser trimming of R3 or R5 would be undertaken increasing R3 or R6 until the loop gain was in specification ie a minumum loop gain of 0.999 . An alternative to laser trimming is to replace the basic mirror loop with a feedforward gain correction circuit ( see fig 23 ) which would not only eliminate gain trimming in general but would also be more cost effective in dual or quad packages.Figs 104 and 105 can also be implemented using all CMOS devices or a mix off CMOS and BIPOLAR devices which would enable the choice of device most appropriate for any given part of the circuit.

For example the postive feedback current amplifier can be implemented using a CMOS feedforward gain correction arrangment and the high current output stage can use BIPOLAR devices in a BICMOS integrated circuit.

Fig 110 Fig 110 is a differential input, dual current output transconductance amplifier configured as a differential amplifier. The transfer function for this arrangment is derived on pages

and is: Io=Gm1+Gm2(V2-V1)+Gm1-Gm2(V1+V2) 2K K 2 where K=1+n(1+R1Gm2) Cml is the transconductance of the noninverting input Gm2 is the transconductance of the inverting input n is the ratio of the feedback current to the output current lo the first term is the differential gain the second term is the common mode gain An important characteristic of any differential amplifier is its common mode gain which is ideally zero.Looking at the common mode gain term it can be seen that for zero common mode gain only the variables Gml and Gm2 must be be equal ie equal transconductance gains for the inverting and non-inverting inputs. Therefore this configuration relies on the inherent common mode rejection of the transconductance amplifier, not on any resistor matching as in the case of the standard 4 resistor differential amplifier based on a operational amplifier.

Fig 112 is a suitable circuit arrangment for the input stage and fig 80 is a suitable current sampler. Fig 112 comprises Q5 and Q6, the input differential amplifier, which has a low common mode gain. Q9 to Q18 , the positive feedback current amplifier.

which has a common mode gain of typically v.s and a differential gain of 500 ie a C. M. R.R of 66dB and the output stage which also has a low common mode gain. Typical common mode rejection ratios of 120dB or more are possible with this circuit. The positive feedback current amplifier in fig 112 can be replaced with a feedforward gain correction arrangment ( see fig 23 ) which would eliminate gain trimming requirements.

Fig 111 Fig 111 is a differential amplifier based on fig 110 but with Al and A2 added which provide input buffering and differential gain and with A4 which buffers the output of A3 and provides a voltage output. The transfer functions for this arrangment are derived on pagesi6ito!3and are: Vo = [Gm1+Gm2(V2-V1)(1+2R2)+Gm1-Gm2(V1+V2)RL 2K R3 K 2 and Io = Gm1+Gm2(V2-V1)(1+2R2)+Gm1-Gm2(V1+V2) 2K R3 K 2 where K = l+ntl+RlGm) These two arrangments will provide high impedence inputs, voltage or current outputs, high C.M.R.R dependent to a large degree only on the C.M.R.R of A3 and operation from dual or single supplys. For both arrangments it can be seen that the input stage provides voltage gain for differential input signals (1+2R2/R30 but only unity gain for common mode signals.As for fig110 ,fig 111 can use for example the circuit arrangments in figs 112 and 80 for the amplifier A3, and A3 itself can have an internal errorfeedfoward amplifier to provide its high current gain.

Fig 176 Fig 176 is based on the arrangment in fig 111 but with a modified front end. This configuration can be used to sense a current in a current loop without introducing a voltage drop in the loop, ie V1,2 = OV. The output current can be taken from o/p&num;l or a voltage can be taken from o/p&num;2.

In eqiulibrum the voltage between V1,2 is very nearly zero and with R5=R4=R, the voltage between the two outputs of the op amps is Vd=iR where i is the current through R5 and R4.

The output current from o/p&num;l is: Vd=iR , Io&num;l= Vd nR1 therefore Io&num;l= R i nRl Gain can be taken on the input side by scaleing the values R4 and R5. The instrumentation amplifier is ideal for this application due to its high common mode rejection which eliminates the floating voltage at the input from appearing as an output signal.

Fig 113 Fig 113 is a differential transconductance amplifier configured as a current transmitter. This circuit arrangment will accept input voltage ranges of O to +lOV, O to +5V etc and output current spans of O to +20mA, +4mA to t20mA and +5mA to+25mA etc.

For the circuit to function correctly the voltage on the inputs must be at some positive value above ground/OV to ensure that the input stage is operating within its common mode input voltage range and also to ensure that the output current sampler has a minumum voltage at its output for correct operation. Pages

derive the transfer function for this transmitter and also give three examples for a range of input voltage and output current spans. Fig 115 is a suitable circuit arrangment for the transconductance amplifier and a suitable current sampler is shown in figs 67 and 73. Fig 115 is based on the arrangment of figll2but with the variable current sink replaced by CS4, which provides bias for Q2 and Q3. The current transmitter has a wide bandwidth of typically 1OMhz and with a very high linearity I due to linearity of current sampler ) and thus has a performance exceeding existing integrated circuit current transmitters. The transmitter is best implemented as a monolithic integrated circuit, with Q3 ideally being an external transistor so that most of the power dissipated in the circuit is external to the package.

Fig 114 Fig 114 is a single supply, differential voltage input single ended current output instrumentation amplifier. The arrangment is based on the the dual supply voltage type instrumentation amplifier in fig 111 but with a current sink CS1 added. With CS1 added an output offset current can be produced, for example when an output current of +4mA to +20mA. Pages

derive the transfer function which is: Io = Gml+Gm2(V2-V1)(1+2R) + Gml-Gm2(V2+V1) 2K R3 K 2 +ICS1 R1 Gm2 K Where the first term gives the differential mode gain, the second term gives the common mode gain and the third term gives the output offset current.For this arrangment to function correctly the inputs V1 and V2 must be at some positive potential with respect to ground to ensure that the inverting and non-inverting inputs are operating within there common mode input voltage range, a typical value being +5V. Also the input voltage V2 must be greater than V1 over the input differential voltage range, ie: V2 > ,V1 so that the output current increases in a positive direction as V2 increases.

Now Io(offset) ICS1 R1 Gm2 1+n(1+R1Gm2) With 1+n/Gm2 < < nR1 Io(offset) = ISC1 n Therefore if an output range of +4mA minumum is required and n = 0.01 , then ICS1 = 40uA. The differential mode gain is given by: Io = Gm1+Gm2 (V2-V1)(1+2R) 2(1+n(1+R1Gm2)) R3 with Gml=Gm2=Gm Io = 1 CV2-V1)(1+2R) I+n+nR1 R3 Gm with 1+n/Gm nR1 R3 = 2R nRlIo - 1 V2-V1 Example &num;1: With R1 = R = 10Kohms, V2-V1 = 10mV and Io = 16mA R3 = 2x10E3 0.01x10E3x0.016 - 1 0.01 R3 = 20E3 159 R3 = 125.786ohms Therefore a value of 125.786ohms would be used for R3 and with an offset of 4mA, CS1 = 40uA.

Example &num;2: With R1 = R= lOKohms, V2-V1 = 1V, Io = 50mA and zero output offset current: R3 = 2x10E3 0.01x10E3x.05 - 1 R3 = 20E3 4 R3 = SKohms Therefore a value of 5kohms would be used for R3.

Figs 116, 118 and 119 Fig 116 comprises a differential input, dual current output transconductance amplifier connected in a non-inverting mode.

The amplifier has a high input impedence at its non-inverting voltage input and a low input impedence at its inverting current input. Fig 118 is a multiple loop feedback amplifier V.C.C.S ) which can he used as the internal circuit arrangment of the transconductance amplifier in fig 116 and is in fact the same multiple loop feedback amplifier as in fig 42. Fig 119 is based on fig 118 whereby the input amplifier G2 is replaced by a voltage buffer whose +Vin input represents input e of G2 and whose -Iin input represents input d of G2 The buffer comprises a high ( ideally infinite ) input impedence at its + voltage input with a voltage gain assumed to be unity and has a finite input resistance (Rs) into its invention current input.The current through Rs is the same as the input current Ia into G1, ie Ia = - IRs The overall transconductance for fig 119 is derived on pages to 186 and is: Io = #aGi Vin (I-#b)(Rs+R1)(n+1)+#aR1nGi Typical values for the circuit elements are: #a=1, Gi=50, Rs=250hms, n=0.01 and #b-0.999 ie a 0.17. accuracy from unity.With R1=600ohms Io = ~ 50 Vin (1-0.999)(25+600)(0.01+1)+600x0.01x50 50 = 50 = 0.166316 Vin 300.63125 with #b =1 Io = 1 = 1 =0.166666 Vin Rln 600x0.01 % error = 0.21% = -0.018dB With R1 = lOKohms Io = 50 Vin (1-0.999)(25+10E3)(0.01+1)+10E3x0.01x50 Io = 50 = 0.00997979 Vin 5010.1252 with #b = 1 lo = 1 = 1 = 0.01 Vin Rin ltE3xt.01 % error = 0.202% = 0.0175dB The above results show that the gain error remains constant even with R1 changing in value.This is due to the gain setting resistor R1 not effecting the value of loop gain as R1 is much greater in value than Rs, so R1 can be eliminated from the denominator of the amplifier transfer function.

Figs 117 and 120 Fig 117 comprises a differential input dual current output transconductance amplifier connected in an inverting mode.

The amplifier has a high input impedence at its non-inverting voltage input and a low input impedence at its inverting current input. Fig 120 is the same circuit arrangment as in the non-inverting configuration of fig 119 but with the voltage input grounded and the resistor R1 forming the inverting input. The overall transconductance for fig 117 is derived on pages

and is: -Io =#a 61 Vin (1-#b)(Rs+R1)(n+1)+nR#aGi typical values for the circuit elements are #asl, Gi=50, Rs=25ohms, n=0.01, and #b=0.99 is 0.1% accuracy from unity.With R1 = 600ohms - lo = 50 Vin (1-0.999)(25+600)(0.01+1)+600x0.01x50 - Io = 50 = 0.166316 Vin 300.63125 with #b = 1 - lo = 1 = 1 = 0.166666 Vin Rln 600x0.01 % error = 0.21% = -0.018dB With Rl = 10Kohms - lo = 50 Vin (1-0.999)(25+10E3)(0.01+1)+10e3x0.01x50 - Io = 50 = 0.00997979 Vin 5010.1252 with #b= 1 - lo = 1 = 1 = 0.01 Vin Rln 10E3x0.01 % error = 0.0202% = -0.0175dB The above results show that the gain error remains constant even with R1 changing in value. This is due to the gain setting resistor R1 not effecting the valueof loop gain as R1 is much greater in value than Rs, so R1 can be eliminated from the denominator of the transfer function.

Figs 121 and 122 Fig 121 is a typical circuit arrangment for the transconductance amplfiers of figs 116 and 117. Q5, Q6, Q23 and Q24 form the voltage and current inputs. The collector current of Q6 drives the positive feedback current amplifier which comprises Q9 to Q18 via the common base transistor Q8. The output is taken by Q12 which drives the emitters of Q4 and Q19. These two devices provide a class AB drive to the output current amplifiers comprising Q1 to Q3 for positive output currents and Q17, Q21 and Q22 for negative output currents when driven by the class A collector current of Q12. CS5 provides a minumum collector current in Q3 and Q17 therefore ensuring these devices are always operated in class AB as the collector currents of Q4 and Q19 drop.Fig 122 is a suitable current sampler which is the same as that in fig 105 and provides a bipolar output current when driven by the class AB outputs &num;1 aand &num;2 from fig 121.

Figs 123 to 126 are typical PSPICE simulations of figs 121 and 122 connected in a non-inverting feedback mode as shown in fig 116. Fig 123 is the frequency responce for R1 = SKohm and indicates a bandwidth of around 14Mhz. Fig 124 is with R1 = 500ohms and indicates a bandwidth of around 8Mhz. The bandwidth has dropped by 57% for a gain change of 20dB , which is due to the fininte dynamic input impedence into the inverting current input, whereas a conventional operational amplifier displays a 1000% bandwidth reduction for a 20dB change of gain.Fig 125 is the square wave responce and indicates a + or - 20mA output swing with minumum overshoot and a settling time of under 400mS to 0.17 with R1 = 5000hms. Fig 126 is again the square wave responce with R1 = SKohms and again shows a fast responce with minumum overshoot and a settling time of under 400r to 0.1% .

Fig 127 and 128 Figs 127 and 128 are alternative circuit arrangments which can be used to implement the transconductance amplifiers of figs 116 and 117. Fig 127 comprises Q1 and Q2, with the emitter of Q2 providir the non-inverting voltage input and the emitter of Q1 the inverti current input. The collector current of Q1 drives the postive feedback current amplifier comprising Q5 to Q14 via the common ba amplitier Q3.The outputs &num;1 and &num;2 are provided by Q10 and Q12 which give identical bipolar output currents, with a typical output swing of + or - 4mA. Fig 128 is the current sampler which provdes a bipolar feedback and output current when driven by the class A input drives. The sampler is symetrical about the C)V axis and therefore the positive output circuitry will only be described. Input &num;1 is coupled to output &num;1 of fig 127.

Q4 to Q7 provide a class AB drive current to the high current positive output amplifier which comprises Q1 to Q3, R1, R2 and R5. As the output current &num;1 reduces by I, the emitter current of Q7 increases by I and inturn increase the current in R1 by I.

With suitable choice of values for R1 and R2 the output mirror amplifier with provide a current gain ( typically x 50 ) and this output currnet passes to the current sampler circuitry which comprises R3, R4 and Q8 to Q13. With R6, R7 and Q14 to Q19 the current sampler is the same as the sampler in fig 93 and can be revered to for circuit operation. The collector current of Q10 forms the positive feedback current and the collector current of Q8 forms the positive output current. Typical current gains from the from the inverting current input to output are x50,000, with a quiecent current of AmA and an output of + or - l50rnA.

Fig 165 Fig 165 is yet another input transconductance amplifing stage.

This arrangment provides a differential current drive to the positive feedback current amplifier and provides a voltage and current input. Q5 to Q14 comprises the current feedback amplifier driven by Q3 and Q4 which are connected as a differential pair and provide a differential drive. The current stage consists of Q1 and Ql5 with the voltage input stage consisting of Q2 and Q16. This arrangment can be used to drive fig 128 or by using o/p&num;;1 as a feedback current it can be configured as an inverting or non-inverting transconductance amplifier with typical output current swings of + or - 5mA and bandwidths exceeding 150Mhz, with NO FREQUENCY COMPENSATION REQUIRED.

Figs 129 and 130 Figs 129 and 130 illustrates the use of a differential voltage input dual current output transconductance amplifier as a voltage amplifier. The top circuit being a noninverting configuration and the lower circuit an inverting configuration. The transfer function for the non-inverting circuit is derived on pages 196 to ssq7 and is: Vo(s) = R191+sccRf) Vi(s) = nR1(1+sC1R1) the transfer function contains a pole due to the addition of load capacitance Cl and a zero due to addition of a compensation capacitor across the feedback resistor R#.

Under the conditions of high load capacitance which will tend to reduce the overall bandwidth of the amplifier Ct is added. With the appropriate value of CC the zero cancels the pole and therefore maximum bandwidth is obtained (as ditermined by the bandwidth of the transconductance amplifier) even with high load capacitance.

For pole-zero cancellation to occur the feedback network timeconstant is made equal to the load timeconstant ie Ct Rf = Cl Rl For example with Rl=lOOohms, Rf=6OOohms, C1=500pF and n=0.01 CC = 500xE-12.100 = 83.3pF 600 The voltage gain is: Vo = Rl = 100 = 16.66 = 26.6dB V1 nR1 0.01x600 example &num;2 : R1=5Kohm,C1=20pF, Rf=10Kohms and n=0.01 Cc=20E-12 . 5E3 10E3 Cc=lOpF The voltage gain is:: Vo = Rl =5Eb Vi nRf 0.01 . lOE3 Vo = 50 = 34dB vi In practice the transconductance amplifier will have a finite output capacitance and the feedback node will have some stray capacitance both of which will have to be taken into account for in calculating Cc Therefore with Cstray and Cout (Cc+Cs )Rf=(Cl+Co )Rl Cc=(C1+Co)RL-CsRF Rf The advantages of using a trnsconductance amplifier as a voltage amplifier as compared to a conventional op amp are as follows:- (1) A conventional op amp is sensitive to load capacitance which reduces its gain and phases margins which in turn increase transient overshoot and ringing and eventially result in the op amp oscillating if CL is high enough.A transconductance amplifier due to the feedback being derived in an active circuit isolated from the load (see current samplers in figs 86 to 90 is not effected by the load capacitance with regard to gain or phase margins, any load capacitance will only act with the load resistance to form a low pass filter,reducing the overall bandwidth of the amplifier. With the addition of a feedback zero this load time constant can be cancelled, a technique not possible with operational amplifiers.

(2) A conventional operational amplifier has a constant gain-bandwidth product which limits both high gain and bandwidth. For an op amp with a bandwidth at unity gain of 10Mhz, has its bandwidth reduced to 1Mhz at a gain of x10 and at a gain of x100 reduced to 100Khz. A transconductance amplifier however is not restricted to a constant gain-bandwidth and can have relativity constant bandwidths dispite changes in RL which changes the voltage gain and can have the same bandwidth at unity gain to gains of x100 or greater. A transconductance with the same bandwidth of 10Mhz at a gain of 100 is equivalent to a op amp with a G.B.P of 1Ghz, the transconductance therefore has 8. clear advantage in high gain, wideband applications.

Figs 131 to 136, figsl72 to 173 and figs 181 to 184 are typical PSPICE simulations of the circuits in figs 104 and 105 configured as non-inverting voltage amplifiers. Figs 131 to 136 are with RL=600ohms, R1=600ohms and n=0.01 giving a voltage gain of x100 = 40dB. Fig 131 is a frequency plot of the amplifier with Cc=CL=OpF resulting in a bandwidth of 10Mhz. Fig 132 is the square wave responce and shows a fast, clean responce. Fig 133 is the same amplifier with CL-50pF and shows the bandwidth reduced to 4Mhz. FIg 134 is the square wave responce wih CL=50pF and clearly indicates the increased settling time.Fig 135 is a frequency plot with Cc=CL=5OpF and clearly illustrates the increses in bandwidth back to the case where CL=OpF, of 1(jMh. Fig 136 is the square responce. Adding Cc then clearly improves the responce under high load capacitance conditions.

Figs 172 and 173 are the same circuit with R1=RL=600 and CL =OpF, with Cc=lOpF, illustrating that the addition of a small amount of feedback capacitance can be used to tweak the circuit to get the highest bandwidth.

Figs 181 to 184 are with R1=100ohms and RL=6000hms resulting in a gain of x60O = 55.6dB. Fig 181 is with Cc=CL=OpF and indicates a bandwidth of 20Mhz. Fig 182 is the square wave responce. Fig 183 is with CL=500pF and Cc=100pF and again shows the effect of Cc by giving a bandwidth of 12Mhz.

With no Cc added the load timeconstant results in a bandwidth of 530Khz. Fig 184 is the square wave responce showing fast settling tines of 500nS to 0.1%.

The conclusion is that even with very large load capacitance (SOOpF) the resultant bandwidth is 12Mhz which at a gain of x600 is a G.B.P of 7.2Ghz !!! , with Cc=C1=OpF the G.B.P is 12Ghz !!!. Both results show that these circuit arrangments give bandwiidths at high gains much greater than existing op amps. In practice bandwidths in excess of 100Mhz will be obtainable which configured for gains of x600 for example will give G.B.P in excess of 60Ghz !!!.

Fig 137 illustrates the use of a differential voltage/ current input, dual current output amplifier as an

inverting voltage amplifier. The transfer function for this arrangment is derived on pages

and is: Vo(s) = RL(1+sCcRL) Vin(s) nR1(l+sCLRL) The transfer function contains a pole due to the load capacitance CL and a zero due to the addition of a compensation capacitor c. With high load capacitance Cc is added to cancel the output pole due to CL.For pole-zero cancellation to occur the feedback timeconstant and load timeconstants must be equal ie CcR1 = CLRL For example if RL=5000hms, R1=5000hms, CL=20pF Cc = 20E-12x500 = 20pF 500 The voltage gain is Vo = RL = 500 = x100 = 40dB Vin nR1 0.01x500 Figs 166 to 171 are typical PSPICE simulations of a voltage/ current transconductance amplifier configured in a noninverting mode (see figs 121 and 122 ), with RL=5000hms and R1 =500ohms therefore giving a voltage gain of x100.

Fig 166 is a frequency plot showing the responce of the amplifier with Cc=CL=OpF. The bandwidth is 8Mhz and indicates a voltage gain of 4OdB.Fig 167 is the square responce indicating a clean, fast responce with a settling time of 400nS to 0.1%. Fig 168 is a frequency plot this time vdth CL=5úpF and shows a reduction in bandwidth to around 5iAhz, with fig l69 being the square wave responce.

Fig 170 is a frequency plot with Cc=CL=50pF and clearly illustrates the increase in bandwidth due to Cc to a value in fact greater than Cc=CL=OpF of 9Mhz. Fig 171 is the square wave responce with Cc=CL=5upF and shows the fast clean responce. Therefore even with a high load capacitance the overall bandwidth can still be defined by the transconductance amplifier with Cc added. This NON-OPTIMISED simulation exhibits a bandwidth of 8Mhz and is set for a gain of x100. This results in a C.B.P of 800Mhz which is near to the top end of op amp performance. This circuit can be expected to give much greater bandwidths of 50Mhz or more and with gains of say x200 will result in a G.B.P of 10GHz Output slew rate is also very high with fig 171 showing a slew rate of 160V/uS.

Figs 129 and 130 can be modified by adding a unity voltage gain, closed or openloop buffer at the output, with RL now connected to to the buffer output and a resistor R2 connected from the buffers input to ground. This has two advantages; (1) Cc is much lower in value as it only has to compensate for the input capacitance of the buffer.

(2) The load is isolated from the gain equation , the gain now being R2/nR1 or -R2/nR1.

Errorfeedforward current output amplifers Figs 139 and 140 Figs 139 and 140 are semi-block diagrams of non-inverting transconductance amplifiers with errorfeedforward gain correction. The circuit consists of A3 which converts the input drive voltage into two identical drive currents which drive A4 and A5.A4 provides the output load current and is a open loop circuit arrangment. A5 has a. single current input and a dual current output and is configured as an inverting current amplifier with a current gain of -1/n . A5 compares the input reference current from Q1 and Q4 with the sampled output current I n4 ) and provides a error feedforward current which corrects for gain errors, distortion etc in A4 by cancelling these errors at the output node.

The transfer function for fig 140 is derived on pages

and is:

A4 is therefore eliminated from the transfer function and its error components donot appear at the output. A typical circuit arrangment for A3 is shown in fig 142. The input differential pair drive the the positive current feedback amplifier which comprises M1 and M2. M1 has two outputs which are coupled to to the translinear circuits TLN1 and TLN2. The outputs of TLNl and TLN2 drive the output transistors Q4 to a7 which provide the identical output drive currents, with the entire amplifier operating in class A.Fig 141 @a s. suitable circuit arrangment which can be used to implement the class AS amplifier A4 in figs 139 and 140. Q3 and Q4 convert the the class A input current into class AB output currents which drive the positive output current mirror( which comprises Q, Q2, Q4 and R1 to R3) via the collector of Q3 and drives the negative output mirror (which compises Q6 to QS and R4 to R6) via the collector of Q5. Both output mirrors can be designed such that they give output currents into the ampere range. CSl is added to ensure that the output devices are always conducting and therefore are operating in true class AB.Figs 139 and 140 have an advantage over the previous current amplifiers in that the output stage is not inside a feedback loop, but its gain errors etc are corrected by error feedforwarded. This results in a greater overall bandwidth as the phase shift of the output stage does nut have to be frequency compensated for.

Fig 143 is an extention of figs 139 and 140 in that additional input op amps Al and A2 are added. The resultant circuit provides a differential input with high C.M.R.R and with high output current capability and with wide bandwidth.

Figs 144 and 145 Figs 144 and 145 are transconductance amplifiers configured in non-inverting and inverting modes which have been modified to provide an output enable/gate function. By applying an appropiate input control voltage/current to the o/p enable/gate, gates off the output sampler and therefore eliminates the input signal from the output and therefore results in zero gain. This is a useful function and would typically be used as a high speed signal multiplexor. Fig 147 details a practical circuit.

Fig 146 is a circuit arrangment which allows a signal voltage to be converted into a signal current to drive one of three current buses. Fig 146 comprises two voltage/ current input transcoductance amplifiers with gated output current samplers based on the gated sampler in fig 147 but with the addition of a third complementary pair. Each output pair are connected to the output buses 1, 2 and 3, therefore looking at the top circuit, the input A turns on Q1 and Q4, input B turns on Q2 and Q5 and input C turns on Q3 and Q6. With the identical bottom circuit this arrangment allows the two input signals to drive any bus, with both inputs able to be summed in to any bus. The arrangment in general can drive more buses by the inclusion of more output pairs and more inputs can be catered for by having more input amplifiers.

Fig 147 Fig 147 is a current sampler with the addition of a gateing facility. Fig 147 is based on the current sampler arrangment as shown in fig 93 but with the addition of Q13 and Q14. The signal current through R2 can be gated by turning cn Q3 or ç to the first or second outputs respectively and the current through R4 can be gated by turning on Q14 or Q13 to the first or second outputs respectively. The sampler therefore provides the facility to drive a load at &num;1 or a load at output&num;2 at a high switching rate if required. With the output &num;2 grounded for example the sampler can can be used to elirninate from the output &num;1 the input signal current ie provide a gateing function.

Figs 148 and 149 are circuit diagrams of voltage/current input transcoductance amplifiers configured to to drive signal cables. G1 to G3 are the said amplifiers whose outputs sum into R4. R4 matches the characteristic impedence of the cable and is typically 50 to 75 ohms.

These configurations due to current summing of the outputs allow the input signals to be summed or gated off by the application of a suitable control signal to the appriopriate enable inputs of the transconductance amplifiers. R5 acts as a matching load for the cable. Fig 149 uses a forth transconductance amplifier to buffer the cable and provides a output current. G1 to G4 with R4 can be implemented as a single integrated circuit and with R1 to R4 external gain setting resistors, the input amps can be inverting. Typical circuit arrangments for the input amps are shown in fig 104 and fig 147.

Fig 150 Fig 150 comprises a transconductance amplifier configured as a variable/gated gain voltage amplifier. This circuit configuration provides a non-inverting variable gain fusion which can also be gated off (using force 07 input) or gated to full gain as set by R1 and R3 (using force 1007. input).With both force inputs not activated the voltage is set by R1, R3 and a variable current gain means which comprises part of the output current sampler.The transconductance of the input amplifier is given by:- Gm = -K;R1 The transresistance of the output stage is given by: Gr = -R3 therefore Vo = R3K Vin R1 The circuit means (2) produces a control voltage or current which controls the current gain of the variable current gain meansKvia (1) and is acted upon by a differential input voltage and the force inputs. By varying the differential input voltage the gain can be varied and by applying a suitable control signal to the 0% force input the differential control voltage is overiden and the gain drops to zero.

Applying a control signal to the 100% force input overides the gain control and forces the gain to be given by R3/R1.

Therefore gain is varied from 0 to R3/R1. Suitable practical circuitry for this arrangment is shown in figs 152, 153 and 156.

Fig 151 Fig 151 comprises two tansconductance amplifiers configured as a signal mu iplexor/signal fader, each amplifier comprises a variable gain amplifier ( see fig 152, 153 and 156 ) which allow gain control and output gateing. The circuit block Gain/enable control has a number of inputs which in turn via the circuit block control the gain. Gain A is a differential input which controls the gain of the top amplifier and B like wise for the bottom amplifier. When cross coupled together the resultant differential input allows the arrangment to act as a signal fader. Enable A when activated enables the gain control circuitry in the top amplifier and when not activated the top amplifier gain is given by -1/R1, with enable B acting in the same manner.Force A overides both Enable A and Gain A inputs and when activated gates off the top amplifier, with Force B acting in the same manner for the bottom amplifier.

Fig 155 , Fig 153 and Fig 156 Figs 152 and 153 are transconductance amplifiers suitable for variable gain applications. Fig 152 is an all npn signal path design with ZD1 providing the level shifting whereas fig 153 uses a pnp device Q3 for level shifting. For both circuits Q1 provides the current input and Q2 the voltage input, with the signal current from Q2 passing through either ZD1 or Q3 to the positive feedback current amplifier, which comprises Q5 to Q14. Q10 and Q12 provide output current drive, with the collector current Q10 forming the feedback current and the collector current of Q12 formng the output current, with a typical swing of + or - SmA.These circuits can be configured in non-inverting or inverting modes as in figs 116 and 117 to define the input transconductance. Figs 155 and 156 are typical PSPICE simulations of fig 153 with the amplifier in a non-inverting mode, RL=l0Oohms, +Vs=15V, -Vs=-1SV, R1=6000hms, Rs=SOohms and transistor FT=800Mhz.

Fig 155 is the square wave responce, with an output swing of + or - lmA. This plot shows the the fast clean responce with a lZ settling time of 20nS. Fig 15Q is frequency plot and indicates the widebandwidth of over 150Mhz.

Fig 156 is a current controlled variable gain current amplifier arrangment whose input current is the output current of figs 152 or 153. Q9 to Q12 comprises the basic variable transconductance gain core with Q9 to Q12 acting as linearising elements and with the output taken from the collector of Qil. The circuit also comprises mirror M1 (R1, R2, Q1, Q2 and Q5), mirror M2 (Q19, Q23, Q24, R5 and R6), mirror M3 (Q20, Q25, Q26, R7 and R8), translinear circuit TLN1 (Q7, Q8, Q17 and Q18), translinear circuit TLN2 ( Q13 to Q16) and common base transistors Q21 and Q22with associated bias source CS1. Increasing the input control current by I increases the output current by I of TLN1.

This also increases the emitter current of Q21 by I which in turn reduces the collector current of Q22 by I and therefore reduces by I the output current of TLN2. Mirrors Ml, M2 and M3 are set at gains of x10 to reduce the control current input swing therefore M1 output current will increase by lOxI M2 will increase by lOxI and M3 will reduce by lOxI. With identical geometry in Q9 to Q12 the collector current of Q10 will reduce by lOxI and the collector current of Q11 will increase by lOxI. The gain will therefore increases, with the collector of Qll matching the output current of M2, ie the output offset current will remain at zero volts.

Figs 163 and 164 are PSPICE simulations of fig 156 with RL= 250hms, R1=RS=R8=SKohms, R2=RE=R7=5000hms, CS1=400uA, +Vs=15v, -Vs=-1SV and transistor FT=800Mhz. In fig 163 the input control current is set to give a current gain of OdB (xl) therefore Q10 is just about off and Qll is conducting the full signal current, resulting in a bandwidth of around 45Mhz. In fig 164 the control current is set to give a gain of -14dB, resulting in a bandwidth of around 100Mhz.

Fig 157 Fig 157 is a circuit arrangment that can typically be implemented as a single monolithic integrated circuit. This combination of circuit elements can be used to implement a wide range of circuit functions, with Gm being a transconductance amplifier with a typical output swing of + or - 50mA, Al a standard operational amplifier and the voltage reference being a zener or bandgap type. The transistors Ql and Q2 are included to increase the versatility of the IC. Al has internal frequency compensation for unity gain and Gm has an external frequency compensation network connected to pin 5.

Figs 158 to 160 are a brief range of possible applications for this IC, with the IC typically implemented in a 14pin DIL package in BIPOLAR, CMOS or BICMOS technologies.

Fig 158 Fig 158 is a current transmitter based on the the general purpose circuit in fig 157. Gm provides the current output drive to the load with a gain ditermined by R2,R1,R4,Vref, Al, with Q1 providing an offset current to the feedback loop, and thus provides an output current under the conditions of zero input voltage.

For example if an output current of 4mA to 20mA is required for an input voltage range of OV to 10V then for 4mA output and with n=0.01 the feedback current is 40uA. The collector current of Q1 is then set at 40uA so that when Vin=OV the voltage drop across R2 is also OV, with 40uA feedback current Iout=4mA.

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derive the transfer function for this arrangment which is: Io = Vin + IcQ1 nR2 n where ICQ1 = Vref/RS For example with an input voltage range of OV to +10V and R2=62k5 and R4=250K. If the value of R2 needs to be reduced for stability requirements in Gm, then an input attenuator can be used at the input of Gm but will of course reduce the input resistance. In general this circuit can be configured to give any range of input voltages and output currents within the capability of Gm.

Fig 160 Fig 160 is an absolute value circuit based on the general purpose IC in fig 157. Al is the transconductance amplifier and A2 is the standard op amp.

For positive going input voltages the diode AL conducts giving a positive voltage output and for negative going voltages D1 conducts which in turn also gives a positive output voltage due to the inversion of A2 ie Vo=|Io|R With Io=Vin Cm l+n(l+RlGm) Vo= Vin GmR 1+n(1+RlGm)

or Vo= Vin R E 1+n/Gm < < nR1] nR1 This arrangment can typically be used to drive an AtoD converter which can only accept positive input voltages.

Fig 159 Fig 159 is a non-inverting integrator using the general purpose IC of fig 157. Gm is configured in a non-inverting mode and drives the integrating capacitor C1. The op amp A2 buffers the load, isolating C1. the SET switch precharges C1 to a value given by VrefR3/R2+R3 or without R2 SET discharges C1 to zero volts. When RUN is on and HOLD is off integration takes place and when HOLD is on and RUN is off C1 holds its charge and therefore gives a constant output voltage. The switches are typically CMOS and a quad package would be ideal. This circuit can be modified to give an inverting integrator by connecting Gm in an inverting mode.

Claims

1 A current mode circuit arrangment comprising an output amplifier Gr having a voltage output and a current input, a feedback means B whose input is coupled to the output of said output amplifier Gr, a signal combining means Cl having first, second and third current inputs and first and second current outputs,an input means Gml whose voltage input forms the input of the said arrangment and whose output current is the input current of the first input of the said signal combining means C1,the output current of the said feedback means B whose output current is the input current of the third input of the said signal combining means G1, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr,the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combinings means G1, the said output amplifier Gr whose voltage output forms the voltage output of the said arrangment.

2 A current mode circuit arrangment comprising an output amplifier Gr having a voltage output and a current input, a feedback means B whose input is coupled to the output of the said output amplifier Gr,a signal combining means G1 having first, second and third current inputs and first and second current outputs,the output of the said feedback means B whose output current is the input current of the third input of the said combining means G1, the first output of the said combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the first input of the said signal combining means Cl forming the current input of the said arrangment, the said output amplifier Cr whose voltage output forms the voltage output of the said arrangment.

3 A current mode circuit arrangment comprising an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first, second and third current inputs and first and second current outputs, an input means Gml whose voltage input is the voltage input of the said arrangment and whose output current is the input current of the first input of the said signal combining means Cl, the output of the said feedback means B whose output current is the input current of the third input of the said signal combining means Cl, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the second current output of the said output amplifier Gi forming the current output of the said arrangment.

4 A current mode circuit arrangment comprising an output current amplifier with first and second current outputs and a current input, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first, second and third current inputs and first and second current outputs, the output of the said feedback; means B whose output current is the input current of the third input of the said signal combining means G1, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the first input of the said signal combining means G1 forming the current input of the said arrangment, with the second current output of the said output amplifier forming the current output of the said arrangment.

5 A current mode circuit arrangment comprising an output amplifier Gr having a current input and a voltage output, a feedback means B whose input is coupled to the output of the said output amplifier Gr, a signal combining means G1 have first and second current inputs and first and second current outputs, a signal combining means G2 haveing a voltage and current input and one current output, the said feedback means B whose output current is the input current of the current input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combing means G1 whose output current is the input current to the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the voltage input of the said signal combining means G2 forming the voltage input of the said arrangment, the voltage output of the said output amplifier Cr forming the voltage output of the said arrangment.

6 A current mode circuit arrangment comprising an output amplifier having a current input and a voltage output, a feedback means B whose input is coupled to the output of the said output amplifier Gr, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and one current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means C2,the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means el, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the first input of the said signal combining means G2 forming the current input of the said arrangment, with the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment.

7 A current mode circuit arrangment comprising an output amplifier having a voltage output and a current input, a feedback means B whose input is coupled to the output of the said output amplifier Gr, a signal combining means G1 having first and second currents inputs and first and second current outputs, a signal combining means G2 having first and second voltage inputs and a current output, the output of the said feedback means B whose output voltage is the input voltage of the second input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means Cl, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the first voltage input of the said signal combining means G2 forming the voltage input of the said arrangment, the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment.

8 A current mode circuit arrangment comprising an output amplifier Gr having a voltage output and a current input, a feedback means B whose input is coupled to the output of the said output amplifier Gr, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having a voltage input, a current input and a current output, the output of the said feedback means E whose output voltage is the input voltage of the voltage input of the said signal combining means G2) the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the current input of the said signal combining means G2 forming the current input of the said arrangment, with the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment.

9 A current mode circuit arrangment compising an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having a voltage input, a current input and a current output, the the output of the said feedback means B whose output current is the input current of the current input of the said signal combining means C2, the first output of the said signal combining means G1 whose output current is the input of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the voltage input of the said signal combining means G2 forming the voltage input of the said arrangment, with the second current output of the said current amplifier Gi forming the current output of the said arrangment.

10 A current mode circuit arrangment comprising an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means Cl, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the first input of the said signal combining means G2 forming the current input of the said arrangment, with the second current output of the said current amplifier Ci forming the current output of the said arrangment.

11 A current mode circuit arrangment comprising an output amplifier Gi having first and second current outputs and a current input, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second voltage inputs and a current output, the output of the said feedback means B whose output voltage is the input voltage of the second input of the said signal combining means G2 the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means G1, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the first input of the said signal combining means G2 forming the voltage input of the said arrangment, with the second current output of the said current amplifier Gi forming the current output of the said arrangment.

12 A current mode circuit arrangment comprising an output amplifier Ci having first and second current outputs and a current input, a feedback means B whose input current is the the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having a voltage input, a current input and a current output, the the output of the said feedback means B whose output voltage is the input voltage of the voltage input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the second input of the said signal combining means Cl, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the current input of the said signal combining means G2 forming the current input of the said arrangment, with the second current output of the said current amplifier Gi forming the current output of the said arrangment.

13 A current mode circuit arrangment comprising an output amplifier Gr having a current input and a voltage output, a feedback means B whose input voltage is the output voltage of the said output amplifier Gr, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, an input means Cml whose voltage input is the voltage input to the said arrangment and whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Cr, the second output of the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the voltage output of the output amplifier Gr forming the voltage output of said arrangment arrangment.

14 A current mode circuit arrangment comprising an output amplifier Gr having a current input and a voltage output, a feedback means B whose input voltage is the output voltage of the said output amplifier Gr, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means U the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the second input of the said signal combining means G2 forming the current input of the said arrangment, with the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment.

15 A current mode circuit arrangment comprising an output amplifier Gi having a current input and first and second current outputs, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, an input means Gml whose voltage input is the voltage input to the said arrangment and whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means Cl whose output current is the input current of the said output amplifier Ci, the second output of the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means Cl, with the second output of the said output amplifier Gi forming the current output of the said arrangment.

16 A current mode circuit arrangment comprising an output amplifier Gi having a current input and first and second current outputs, a feedback means B whose input current is the output current of the first output of the said output amplifier Ci, a signal combining means G1 having first and second current inputs and first and second current outputs, a signal combining means G2 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means Cl, the first output of the said signal combining means G1 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means 52, the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the second input of said signal combining means G2 forming the current input of the said arrangment, with the second output of the said output amplifier forming the current output of the said arrangment.

A- A current mode circuit arranment comprising an output amplifier Gr having a current input and a voltage output, a feedback means B whose input voltage is the output voltage of the said output amplifier Cr, a signal combining means G2 having first and second current inputs and first and second current outputs, a signal combining means G1 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means Ci, an input means Gml whose voltage input is the voltage input to the said arrangment and whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G2 whose output current is the input current of the said output amplifier Gr, the second output of the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the voltage output of the output amplifier Cr forming the voltage output of the said arrangment.

18 A current mode circuit arrangment comprising an output amplifier Gr having a current input and a voltage output, a feedback means B whose input voltage is the output voltage of the said output amplifier Gr, a signal combining means G2 having first and second current inputs and first and second current outputs, a signal combining means G1 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, the first output of the said signal combining means G2 whose output current is the input current of the said output amplifier Cr, the second output of the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the second input of the said signal combining means G2 forming the current input of the said arrangment, with the voltage output of the said output amplifier Gr forming the voltage output of the said arrangment.

19 A current mode circuit arrangment comprising an output amplifier Gi having a current input and first and second current outputs, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G2 having first and second current inputs and first and second current outputs, a signal combining means el having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, an input means Gml whose voltage input is the voltage input to the said arrangment and whose output current is the input current of the second input of the said signal combining means G2, the first output of the said signal combining means G2 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, with the second output of the said output amplifier Gi forming the current output of the said arrangment.

20 A current mode circuit arrangment comprising an output amplifier Gi having a current input and first and second current outputs, a feedback means B whose input current is the output current of the first output of the said output amplifier Gi, a signal combining means G2 having first and second current inputs and first and second current outputs, a signal combining means G1 having first and second current inputs and a current output, the output of the said feedback means B whose output current is the input current of the second input of the said signal combining means G1, the first output of the said signal combining means G2 whose output current is the input current of the said output amplifier Gi, the second output of the said signal combining means G2 whose output current is the input current of the first input of the said signal combining means G1, the said signal combining means G1 whose output current is the input current of the first input of the said signal combining means G2, the second input of said signal combining means G2 forming the current input of the said arrangment, with the second output of the said output amplifier forming the current output of the said arrangment.

21 A current mode circuit arrangment as in claims 1 and 2 whereby the signal path of the said signal combining means el from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G1 from its third input through to its first output via the said output amplifier Cr and the said feedback means B to the third input of the said signal combining G1 means being inverting, with the said arrangment being a voltage output amplifier.

22 A current mode circuit arrangment as in claims 3 and 4 whereby the signal path of the said signal combining means G1 from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G1 from its third input through to its first output via the said output amplifier Gi and the said feedback means B to the third input of the said signal combining Cl means being inverting, with the said arrangment being a current output amplifier.

23 current mode circuit arrangment as in claim 5 whereby the signal path of the said signal combining means G1 from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G2 from its current input through to its output via the said signal combining means G1 via the said output amplifier Gr and via the said feedback means B to the current input of the said signal combining means G2 being inverting, with the said arrangment being a V.C.V.S amplifier.

24 A current mode circuit arrangment as in claim 6 whereby the signal path of the said signal combining means G1 from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G2 from its second current input through to its output via the said signal combining means G1 via the said output amplifier Gr and via the said feedback means B to the second current input of the said signal combining means G2 being inverting, with the said arrangment being a C.C.V.S amplifier.

25 A current mode circuit arrangment as in claim 7 whereby the signal path of the said signal combining means G1 from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G2 from its second voltage input through to its output via the said signal combining means G1 via the said output amplifier Gr and via the said feedback means B to the second voltage input of the said signal combining means being inverting, with the said arrangment being a V.C.V.S amplifier.

26 A current mode circuit arrangment as in claim 8 whereby the signal path of the said signal combining means G1 from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means 2 from its voltage input through to its output via the said signal combining means G1 via the said output amplifier Gr and via the said feedback means B to the voltage input of the said signal combining means G2 being inverting, with the said arrangment being a C.C.V.S amplifier.

27 A current mode circuit arrangment as in claim 9 whereby the signal path of the said signal combining means Ci from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G2 from its current input through to its output via the said signal combining means G1 via the said output amplifier Gi and via the said feedback means B to the current input of the said signal combining G2 means being inverting, with the said arrangment being a V.C.C.S amplifier.

28 A current mode circuit arrangment as in claim 10 whereby the signal path of the said signal combining means G1 from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G2 from its second current input through to its output via the said signal combining means G1 via the said output amplifier Gi and via the said feedback means B to the second current input of the said signal combining G2 means being invertingwith the said arrangment being a C.C.C.S amplifier.

29 A current mode circuit arrangment as in claim 11 whereby the signal path of the said signal combining means G1 from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G2 from its second voltage input through to its current output via the said signal combining means G1 via the said output amplifier Gi and via the said feedback means B to the second voltage input of the said signal combining G2 means being inverting, with the said arrangment being a V.C.C.S amplifier.

30 A current mode circuit arrangment as in claim 12 whereby the signal path of the said signal combining means G1 from its second input through to its second output is non-inverting with the said signal path having a current gain substantially equal to unity ,with the signal path of the said signal combining means G2 from its voltage input through to its output via the said signal combining means G1 via the said output amplifier Gi and via the said feedback means B to the voltage input of the said signal combining G2 means being inverting, with the said arrangment being a C.C.C.S amplifier.

31 A current mode circuit arrangment as in claims 13 and 14 whereby the signal path of the said signal combining means G1 from its first input through to its second output via the first current input of the said signal combining means G2 through to its output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G1 from its second input through to its first output via the said output amplifier Gr and the said feedback means B to the second input of the said signal combining means G1 being inverting, with the said arrangment being a voltage output amplifier.

32 A current mode circuit arrangment as in claims 15 and 16 whereby the signal path of the said signal combining means G1 from its first input through to its second output via the first input of the said signal combining means G2 through to its output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G1 from its second input through to its first output via the said output amplifier Gi and the said feedback means B to the second input of the said signal combining means G1 being inverting, with the said arrangment being a voltage source amplifier.

33 A current mode circuit arrangment as in claims 17 and 18 whereby the signal path of the said signal combining means G2 from its first input through to its second output via the first input of the said signal combining means G1 through to its output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G2 from its first input through to its first output via the said output amplifier Gr via the said feedback means B and via the second input of the said signal combining means G1 through to the output of the said signal combining means G1 being inverting, with the arrangment being a voltage output amplifier.

34 A current mode circuit arrangment as in claims 19 and 20 whereby the signal path of the said signal combining means G2 from its first input through to its second output via the first input of the said signal combining means G1 through to its output is non-inverting with the said signal path having a current gain substantially equal to unity, with the signal path of the said signal combining means G2 from its first input through to its first output via the said output amplifier Gi via the said feedback means B and via the second input of the said signal combining means G1 through to the output of the said signal combining means G1 being inverting, with the said arrangment being a current output amplifier.

35 A current mode circuit arrangment as in claims 21, 23, 245 25 and 26 whereby the said signal combining means G1 has differential current outputs, the said output amplifier Gr having differential current inputs, with the differential current outputs of the said signal combining means G1 being coupled to the differential current inputs of the said output amplifier Gr.

36 A current mode circuit arrangment as in claims 22, 27, 28, 29 and 30 whereby the said signal combining means G1 has differential current outputs, the said output amplifier Gi having differential current inputs, with the differential current outputs of the said signal combining means G1 being coupled to the differential current inputs of the said output amplifier Gi.

37 a current mode circuit arrangment as in claim 31 whereby the said output amplifier Gr has an additional current input with both inputs forming a differential current input, the said current combining means G2 having an additional current output, with the additional current output of the said signal combining means G2 being coupled to the additional current input of the said output amplifier Gr.

38 a current mode circuit arrangment as in claim 32 whereby the said output amplifier Gi has an additional current input with both inputs forming a differential current input, the said current combining means G2 having an additional current output, with the additional current output of the said signal combining means G2 being coupled to the additional current input of the said output amplifier Gi.

39 a current mode circuit arrangment as in claim 33 whereby the said output amplifier Gr has an additional current input with both inputs forming a differential current input, the said current combining means G1 having an additional current output, with the additional current output of the said signal combining means G1 being coupled to the additional current input of the said output amplifier Gr.

40 a current mode circuit arrangment as in claims 34 whereby the said output amplifier Gi has an additional current input with both inputs forming a differential current input, the said current combining means G1 having an additional current output, with the additional current output of the said signal combining means G1 being coupled to the additional current input of the said output amplifier Gi.

41 A current mode circuit arrangment as in claims 22, 27, 28, 29 and 30 whereby the said output amplifier Gi consists of a current amplifying means and a current sampling means, with the said current sampling means being responsive to the output current of the said current amplifying means for generating a. feedback current which is some proportion of the output current of the said current amplifying means.

42 A current mode circuit arrangment as in claim 41 whereby the said current sampling means comprises first and second transistors, the base of the first said transistor being coupled to the base of the second said transistor, first and second resistors, with the first end of first said resistor being coupled to the emitter of the first said transistor and the second end of the first said resistor forming the first input of the said current sampling means, the second said resistor whose first end is coupled to the first input of the said current sampling means and whose second end is coupled to the emitter of the second said transistor and whose second end forms the second output of the said current sampling means, the first said transistor whose collector current is substantially equal to the output current of the first output of the said current sampling means, the input impedence into the emitter of the first said transistor being low relative to the input impedence into the emitter of the second said transistor, the second said transistor whose collector current is substantially equal to the input current of the second input of the said current sampling means, the output impedence of the first output of the said current sampling means being high relative to the input impedence into the emitter of the first said transistor, first current supply means coupled to the emitter of the first said transistor, second current supply means coupled to the emitter of the second transistor.

43 A current mode circuit arrangment as in claims 32 and 34 whereby the said output amplifier Gi consists of a current amplifying means and a current sampling means, with the said current sampling means being responsive to the output current of the said current amplifying means for generating a feedback current which is some proportion of the output current of the said current amplifying means.

44 A current mode circuit arrangment as in claim 43 whereby the said current sampling means comprises first and second transistors, the base of the first said transistor being coupled to the base of the second said transistor, first and second resistors, with the first end of first said resistor being coupled to the emitter of the first said transistor and the second end of the first said resistor forming the first input of the said current sampling means, the second said resistor whose first end is coupled to the first input of the said current sampling means and whose second end is coupled to the emitter of the second said transistor and whose second end forms the second output of the said current sampling means, the first said transistor whose collector current is substantially equal to the output current of the first output of the said current sampling means, the input impedence into the emitter of the first said transistor being low relative to the input impedence into the emitter of the second said transistor, the second said transistor whose collector current is substantially equal to the input current of the second input of the said current sampling means, the output impedence of the first output of the said current sampling means being high relative to the input impedence into the emitter of the first said transistor, first current supply means coupled to the emitter of the first said transistor, second current supply means coupled to the emitter of the second said transistor.

45 A current mode circuit arrangment comprising a current sampling means with first and second transistors, the base of the first said transistor being coupled to the base of the second said transistor, first and second resistors, with the first end of first said resistor being coupled to the emitter of the first said transistor and the second end of the first said resistor forming the first input of the said arrangment, the second said resistor whose first end is coupled to the input of the said arrangment and whose second end is coupled to the emitter of the second said transistor and whose second end forms the second output of the said arrangment, the first said transistor whose collector current is substantially equal to the output current of the rirst output of the said arrangment, the input impedence into te emitter of the first said transistor being low relative to the input impedence into the emitter of the second said transistor, the second said transistor whose collector current is substantially equal to the input current of the second input of the said arrangment, the output impedence of the first output of the said arrangment being high relative to the input impedence into the emitter of the first said transistor, first current supply means coupled to the emitter of the first said transistor, second current supply means coupled to the emitter of the second said transistor.

46 A current mode circuit arrangment as in claims 42 and 45 whereby the said first input of the said current sampling means now forms the second output of the said current sampling means, with the said second output of the said current sampling means now forming the first input of the said current sampling means.

47 A current mode circuit arrangment as in claims 42 45 and 46 whereby the voltage between the first end of the first said resistor and the second end of the second said resistor is substantially zero.

48 A current mode circuit arrangment as in claim 47 whereby the signal current in the first said resistor is substantially equal to the signal current from the first output of the said current sampling means.

49 A current mode circuit arrangment as in claims 42, 45, 46, 47 and 48 whereby a buffer circuit means is provided for which comprises first and second and third and forth connections, the first said connection being coupled to the collector of the firt said transistor, the second said connection being coupled to the collector of the second said transistor, the third said connection forming the first output of the said current sampling means, the forth connection forming the second input of the said current sampling means, s. coupling between the collector and base of the first said transistor or a coupling between the collector and base of the second said transistor, with the said buffer means comprising one or more transistors.

50 A current mode circuit arrangment as in claims 42, 45, 46, 47, 48 and 49 whereby a first circuit means is provided for which is responsive to the collector current of the first said transistor for generating a output current which forces the collector current of the second said transistor to be substantially equal to the collector current of the first said transistor.

51 A current mode circuit arrangment as in claim 50 whereby the said output current is substantially equal to the collector current of the first said transistor.

52 A current mode circuit arrangment as in claim 51 whereby the said first circuit means forces the collectur current of the first and second said transistors to be substantially equal as the current in R1 varies due to signal current.

53 A current mode circuit arrangment as in claim 52 whereby the said first said circuit means is current mirror.

54 A current mode circuit arrangment as in claim 42, 44 ,45, 46, 47, 48 and 49 whereby the relationship betwwen Io&num;l and Io&num;2 is substantially given by IoS1 = R2 Io&num;2 R1 55 A current mode circuit arrangment as in claims 42, 45, 46, 47, 48 and 49 whereby a first circuit means is provided for which is responsive to the input current of the said first input for generating a feedforward current which forces the collector current of the second said transistor to be substantially equal to the collector current of the first said transistor.

56 A current mode circuit arrangment as in claim 55 whereby the first circuit means comprises third and forth transistors with there bases connected together, first current mirror whose input current is substantially equal to the collector current of the third said transistor and whose output is coupled to the second input of the said arrangment, a third resistor whose first end is coupled to the first input of the said arrangment and whose second end is coupled to the emitter of the third said transistor, with the emitter of the forth said transistor coupled to the second output of the said arrangment, with a third current supply means coupled to the emitter of the third said transistor.

57 A current mode circuit arrangment as in claim 56 and 53 whereby the relationship between the first said output and the second said output is substantially given by: Io&num;2 = R1 -1 Io&num;1 R2 58 A current mode circuit arrangment as in claims 42, 45, 46, 47, 4b, 49. 54 and 57 whereby the said transistors are npn types 59 A current mode circuit arrangment as in claims 42, 45, 46, 47, 48, 49, 54 and 57 whereby the said transistors are pnp types.

60 A current mode circuit arrangment as in claim 58 whereby the base, collector and emitter of the said transistors can be replaced by the gate, drain and source of corresponding NMOS transistors.

61 A current mode circuit arrangment as in claim 59 whereby the base, collector and emitter of the said transistors can be replaced by the gate, drain and source of corresponding PMOS transistors.

62 A current mode circuit arrangment as in claims 21,23to26 42, 45 to 49,54, 57 to 61 whereby the said signal combining means G1 is comprised of first and second current mirrors, with the first output of the said current mirror is coupled to the input of the second said current mirror and the first output of the second said current mirror is coupled to the input of the first said current mirror, the input of the first said current mirror and/or the input of the second said current mirror forming the current inputs of the said signal combining means G1, with the first said current mirror or the second said current mirror providing the output current of the said signal combining means G1.

63 A current mode circuit arrangment as in claims 21, 23 to 26,42,45 to 49,54, 57 to 61 whereby the said signal combining means G1 is comprised of first and second current mirrors, each comprising an input connection, with an output connection and a common output connection, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror, the input of the first said current mirror and/ or the input of the second said current mirror forming the current inputs of the said signal combining means, with the common output of the first said current mirror or the common output of the second said current mirror forming the current output of the said signal combining means G1.

64 A current mode circuit arrangment as in claims 21, 23 to 26, 42, 45 to 49 ,54, 57 to 61 whereby the said signal combining means G1 comprises first and second current mirrors, with the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror whose output is coupled to the input of the first said current mirror, third and forth current mirrors, with the input of the third said current mirror being coupled to the common of the first said current mirror, with the input of the forth said current mirror being coupled to the common of the second said current mirror, the third said current mirror or the forth said current mirror providing the current output of the said current combining means G1, the input of the first said current mirror and/or the input of the second said current mirror providing a plurality of current input to the said signal combining means G1.

65 A current mode circuit arrangment as in claims 21, 23 to 26, 42, 45 to 9, 54, 5 to 61 whereby the said signal combining means G1 comprises first and second current mirrors with each said current mirrors comprising two or more bipolar transistors, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror,a first additional circuit means responsive to the common output current of the first said current mirror for generating a feedforward current substantially equal to that portion of the input current of the first said current mirror attributable to the base currents of the said bipolar transistors which comprise the first said current mirror, with the feedforward current of the first additional circuit means being coupled to the output of the first said current mirror,a second additional circuit means responsive to the common output of the second said current mirror for generating a feedforward current substantially equal to that portion of the input current of the second said current mirror attributable to the base currents of the said bipolar transistors which comprise the second said current mirror, with the feedforward current of the second said additional circuit means being coupled to the output of the second said current mirror, the input of the first said current mirror and/or the input of the second said current mirror providing a plurality of current inputs to the said signal combining means G1, with one or more additional circuit means responsive to the first said current mirror circuit current or responsive to the second said current mirror circuit current for generating the current output of the said current combining means G1.

66 A current mode circuit arrangment as in claims 21, 23 to 26, 42,45 to 49, 54, 57 to 61 whereby the the said signal combining means G1 comprises a current amplifying means with one current input and first and second current outputs, the input to the said current amplifying means whose input impedence is low relative to the first and second current outputs of the said current amplifying means, the first output of the said current amplifying means being coupled to the input of the said current amplifying means, an additional circuit means responsive to the input current of the input of the said current amplifying means and responsive to the output current of the first output of the said current amplifying means for generating a feedforward current proportional to the difference between the input current of the input of the said current amplifing means and the output current of the first current output of the said current amplifying means, the feedforward current of the said additional circuit means being coupled to the input of the said current amplifying means, the second output of the said current amplifying means forming the current output of the said signal combining means G1, with the input of the said current amplifying means forming the input of the said signal combining means G1.

67 A current mode circuit arrangment comprising first and second transistors, the base of the first said transistor being coupled to the base of the second said transistor, first and second resistors, with the first end of first said resistor being coupled to the emitter of the first said transistor and the second end of the first said resistor forming the first input of the said arrangment, the second said resistor whose first end is coupled to the input or the said arrangment and whose second end is coupled to the emitter of the second said transistor and whose second end forms the second output of the said arrangment, the first said transistor whose collector current is substantially equal o the output current of the first output of the said arrangment, the input impedence into the emitter of the first said transistor being low relative to the input impedence into the emitter of the second said transistor, the second said transistor whose collector current is substantially equal to the input current of the second input of the said arrangment the output impedence of the first output of the said arrangment being high relative to the input impedence into the emitter of the first said transistor, first current supply means coupled to the emitter of the first said transistor, second current supply means coupled to the emitter of the second said transistor.

68 A current mode circuit arrangment as in claims 67 44 whereby the said first input of the said current sampling means now forms the the second output of the said current sampling means, with the said second output of the said current sampling means now forming the first input of the said current sampling means.

69 A current mode circuit arrangment as in claims 44, 67 and 68 whereby the voltage between first end of the first said resistor and the second end of the second said resistor is substantially equal to zero.

70 A current mode circuit arrangment as in claims 69 whereby the signal current in the first said resistor is substantially equal to the signal current from the said first output.

71 A current mode circuit arrangment as in claims 44,67, 68, 69 and 70 whereby a buffer circuit means is provided for which comprises first and second and third and forth connections, the first said connection being coupled to the collector of the first said transistor, the second said connection being coupled to the collector of the second said transistor, the third said connection forming the first output of the said current sampling means, the forth connection forming the second input of the said current sampling means, a coupling between the collector and base of the first said transistor or a coupling between the collector and base of the second said transistor, with the said buffer means comprising one or more transistors.

72 A current mode circuit arrangment as in claims 44, 67, 68, 9, 70 and 71 whereby a first circuit means is provided for which is responsive to the collector current of the first said transistor for generating a output current which forces the collector current of the second said transistor to be substantially equal to the collector current of the first said transistor.

73 A current mode circuit arrangment as in claim 72 whereby the said output current is substantially equal to the collector current of the first said transistor.

74 A current mode circuit arrangment as in claim 73 whereby the said first circuit means forces the collectur current of the first and second said transistors to be substantially equal as the current in R1 varies due to signal current.

75 A current mode circuit arrangment as in claim 74 whereby the said first said circuit means is current mirror.

76 A current mode circuit arrangment as in claims 44, 67, 68, 69, 70 and 71 whereby the relationship betwwen Io&num;1 and Io&num;2 is substantially given by Io&num;1 = R2 Io&num;2 R1 77 A current mode circuit arrangment as in claims 44, 67, 68, 69, 70 and 71 whereby a first circuit means is provided for which is responsive to the input current of the said first input for generating a feedforward current which forces the collector current of the second said transistor to be substantially equal to the collector current of the first said transistor.

78 A current mode circuit arrangment as in claim 77 whereby the first circuit means comprises third and forth transistors with there bases connected together, first current mirror whose input current is substantially equal to the collector current of the third said transistor and whose output is coupled to the second input of the said arrangment, a third resistor whose first end is coupled to the first input of the said arrangment and whose second end is coupled to the emitter of the third said transistor, with the emitter of the forth said transistor coupled to the second output of the said arrangment, with a third current supply means coupled to the emitter of the third said transistor.

79 A current mode circuit arrangment as in claim 78 and 75 whereby the relationship between the first said output and the second said output is substantially given by Io&num;2 = R1.-1 Iot1 H2 80 A current mode circuit arrangment as in claims 44, 67, 68, 69, 70, 71, 76 and 79 whereby the said transistors are npn types 81 A current mode circuit arrangment as in claims 44, 67, 68, 69, 70, 71, 76 and 79 whereby the said transistors are pnp types.

82 A current mode circuit arrangment as in claim 80 whereby the base, collector and emitter of the said transistors can be replaced by the gate, drain and source of corresponding NMOS transistors.

83 A current mode circuit arrangment as in claim 81 whereby the base, collector and emitter of the said transistors can be replaced by the gate, drain and source of corresponding PMOS transistors.

84 A current mode circuit arrangment as in claims 31, 33, 44, 67 to 71, 76, 79 to 83 whereby the said signal combining means G1 comprises a first current mirror and the said signal combining means G2 comprises a second mirror, with the first output of the first said current mirror being coupled to the input of the second said current mirror, the first output of the second said current mirror being coupled to the input of the first said current mirror, the input of the first said current mirror and the input of the second said current mirror forming the current inputs of the said signal combining means G1 and G2 respectively, with the first said current mirror or the second said current mirror providing the current output of the said signal combining means G1 or G2 respectively.

85 A current mode circuit arrangment as in claims 31, 33, 44, 67 to 71, 76, 79 to 83 whereby the said signal combining means Cl comprises a first current mirror and the said signal conbining means C2 comprises second current mirror with each said current mirror having an input connection also an output connection and a common output connection, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror, the input of the first said current mirror and the input of the second said current mirror forming the current inputs of the said signal combining means G1 and G2 respectively, with the common output of the first said current mirror or the common output of the second said current mirror forming the current output of the said signal combining means 51or52 respectively.

86 A current mode circuit arrangment as in claims 31, 33, 44, 67 to 71, 76, 79 to 83 whereby the said signal combining means G1 comprises a first current mirror and the second said signal combining means ? comprises a second current mirror, with the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror whose output is coupled to the input of the first said current mirror, third and forth current mirrors, with the input of the third said current mirror being coupled to the common of the first said current mirror, with the input of the forth said current mirror being coupled to the common of the second said current mirror, the third said current mirror or the forth said current mirror providing the current output of the said current combining means G1 or G2 respectively, the input of the first said current mirror and the input of the second said current mirror providing the current inputs to the said signal combining means G1 and G- respectively.

87 A current mode circuit arrangment as in claims 31, 33, 44, 67 to 71, 76, 79 to 83 whereby the said signal combining means G1 comprises a first current mirror and the said signal combining means G2 comprises a second current mirror, with said current mirrors comprising two or more bipolar transistors, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror,a first additional circuit means responsive to the common output current of the first said current mirror for generating a feedforward current substantially equal to that portion of the input current of the first said current mirror attributable to the base currents of the said bipolar transistors which comprise the first said current mirror, with the feedforward current of the first additional circuit means being coupled to the output of the first said current mirror,a second additional circuit means responsive to the common output of the second said current mirror for generating a feedforward current sustantially equal to that portion of the input current of the second said current mirror attributable to the base currents of the said bipolar transistors which comprise the second said current mirror, with the feedforward current of the second said additional circuit means being coupled to the output of the second said current mirror, the input of the first said current mirror and the input of the second said current mirror providing the current inputs to the said signal combining means G1 and G? respectively, with one or more additional circuit means responsive to the first said current mirror circuit current or responsive to the second said current mirror circuit current for generating the output current of the said signal combining means G1 or G2 respectively.

88 A current mode circuit arrangment comprising a current amplifying means with one current input and first and second current outputs, the input of the said current amplitying means whose input impedence is low relative to the output impedence of the first and second outputs of the said current amplifying means, with the second output of the said current amplifying means being coupled to the input of the said current amplifying means, with the signal path from the input of the said current amplifying means through the said current amplifying means to the second output of the said current amplifying means being non-inverting, the current input of the said current amplifying means forming the current input of the sal arrangment, with the first output of the said current amplifyingr means forming the current output of the said arrangment, with the said non-inverting signal path current gain being of a value such that the resultent current gain from the input of the said arrangment to output of the said arrangment is substantially greater than unity.

89 A current mode circuit arrangment as in claim 88 whereby the current gain of the said current amplifying means from its input to its second output is substantially equal to unity.

90 A current mode circuit arrangment as in claim 89 and 88 whereby the said current amplifying means has one or more additional current inputs and/or one or more additional current outputs.

Yl A current mode circuit arrangment comprising first and second current mirrors whereby the first output of the first aid current. mirror is connected to the input of the second said current mirror and the first output of the second sait current mirror is connected to the input of the first said current mirror.

Second output of the first said current mirror which forms tfle first current output of the said arrangment.

9 current mode circuit arrangment as in claim 91 whereby the current gain of the first said current mirror from its input to its first output multiplied by the current gain of the second said current mirror from its input to it first output is substantially equal to unity.

93 current mode circuit arrangment as in claim 92 whereby only one current input and/or one current output of the said arrangment is provided for.

94 A current mode circuit arrangment as in claim 92 whereby a plurality of current inputs and/or a plurality of current outputs are provided for.

95 A current mode circuit arrangment comprising first and second current mirrors, each comprising an input connection, an output connection and a commun output connection, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror, the input of the first said current mirror forming the first current input of the said arrangment,the input of the second said current mirror forming the second current input of the said arrangment,the common output of the first said current mirror forming the first current output of the said arrangment, with the common output of the second said current mirror forming the second current output of the said arrangment.

96 A current mode circuit arrangment as in claim 95 whereby only one current input and/or one current output of the said arrangment is provided for.

97 A current mode circuit arrangment as in claim 95 whereby a plurality of current inputs and/or a plurality of current outputs are provided for.

98 A current mode circuit arrangment comprising first and second current mirrors, with the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror whose output is coupled to the input of the first said current mirror, third and forth current mirrors, with the input of the third said current mirror being coupled to the common of the first said current mirror, with the input of the forth said current mirror being coupled to the common of the second said current mirror, the output of the third said current mirror forming the first current output of the said arrangment, the output of the forth said current mirror forming the second current output of the said arrangment, the input of the first said current mirror forming the first current input of the said arrangment, with the input of the second said current mirror forming the second current input of the said arrangment.

99 A current mode circuit arrangment as in claim 98 whereby only one current input and/or one current output of the said arrangment is provided for.

100 A current mode circuit arrangment as in claim 98 whereby a plurality of current inputs and/or a plurality of current outputs are provided for.

101 A current mode circuit arrangment comprising first and second current mirrors with said current mirrors comprising two or more bipolar transistors, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror first additional circuit means responsive to the common output current of the first said current mirror for generating a feedforward current substantially equal to that portion of the input current of the first said current mirror attributable to the base currents of the said bipolar transistors which comprise the first said current mirror, with the feedforward current of the first additional circuit means being coupled to the output of the first said current mirror, a. second additional circuit means responsive to the common output of the second said current mirror for generating a feedforward current substantially equal to that portion of the input current of the second said current mirror attributable to the base currents of the said bipolar transistors which comprise the second said current mirror, with the feedforward current of the second said additional circuit means being coupled to the output of the second said current mirror, a connection to the input of the first said current mirror forming the first current input of the said arrangment , a connection to the input of the second said current mirror forming the second current input of the said arrangment, a third additional circuit means responsive to the currents of the first said current mirror for generating a first current output, a forth additional circuit means reponsive to the currents of the second said current mirror for generating a second current output.

102 A current mode circuit arrangment as in claim 101 whereby only one current input and/or one current output of the said arrangment is provided for.

103 A current mode circuit arrangment as in claim 101 whereby a plurality of current inputs and/or a plurality of current outputs are provided for.

104 A current mode circuit arrangment comprising a a current amplifying means with one current input and first and second current outputs, the input to the said amplifying means whose input impedence is low relative to output impedences of the first and second outputs of the said ampl If i .ing means. the first output of the said current amplifiying means being coupled to the input of the said current amplif lying means, an additional circuit means responsive to the input current of the said current amplifying means and responsive to the output current of the first output of the said current amplifying means for generating a feedforward current proportional to the difference between the input current of the said current amplifying means and the output current of the first output of the said current amplifying means, the feedforward current of the said additional circuit means being coupled to the input of the said current amplifying means, the second output of the said current amplifying means forming the output of the said arrangment, the input of the said current amplifying means forming the input of the said arrangment.

10 A current mode circuit arrangment as in claims 66,104 whereby the signal path from the input of the said current amplifying means through the said current amplifying means to the first output of the said current amplifying means is non-inverting.

106 A current mode circuit arrangment as in claim 105 whereby the said additional circuit means comprises first and second current sampling means, with the first said current sampling means responsive to the input current of the said current amplifying means, the second said current sa.mpl inS means responsive to the output current of the first output of the said current amplifying means, an output current from the said f irst current sampling means substantially equal to the input current of the said current amplifying means, an output current from the second said current sampling means substantially equal to the output current of the first output of the said current amplifying means, the output current of the first said current sampling means coupled to input of the said current summing means,the output current of the second said current sampling means coupled to the input of the said current summing means,the said feedforward current of the said additional circuit means being the output current of the said current summing means.

107 A current mode circuit arrangment as in claim 10 whereby the current gain from the input to the output of the said current summing means is substantially equal to unity.

108 A current mode circuit arrangment as in claim 107 whereby the transfer function of the said current amplifying means is:- Io = Aa lin l-b-SlA+AbS2A With each term being the transfer function of the following: 51 is the first sampling means is is the second sampling means A is the current summing means Aa is the current amplifying means transfer function from its input to its first output.

> b is the current amplifying means transfer function from its input to its second output.

109 h current mode circuit arrangment as in claim 108 whereby the said current amplifying means is comprised of first and second current mirrors each with an input, an input common, an output and a output common, with the input current of the first and second said current mirrors being substantially equal to the output current of the input commons of the first and second said current mirrors respectively, the output current of the first and second said current mirrors being substantially equal to the output current of the output commons of the first and second said current mirrors respectively, the output of the first said current mirror being coupled to the input of the second said current mirror, the output of the second said current mirror being coupled to the input of the first said current mirror, the input of the first said current mirror forming the current input of the said current amplifying means, the output of the second said current mirror forming the first output of the said current amplifying means, the said current summing means comprising a common base bipolar transistor whose emitter input forms the input of the said current summing means and whose collector forms the output of the said current summing means, the first said current sampling means comprising a coupling from the input common of the first said current mirror to the input of the said current summing means, the second said current sampling means comprising a coupling from the output common of the second said current mirror to the input of the said current summing means, the output of the said current summing means being coupled to the input of the first said current mirror, with the first or second said current mirrors having one or more additional current outputs and providing the current outputs of the said current amplifying means or the output common of the first said current mirror providing the output current for the said current amplifying means or the input common of the second said current mirror providing the output current of the said amplifying means.

11 A current mode circuit arrangment as in claims 109 whereby the said current summing means is a current mirror.

111 A current mode circuit arrangment as in claim 109 whereby the said current summing means comprises a second bipolar transistor whose collector is coupled to the collector of the first said bipolar transistor ,the base of the second said bipolar transistor being coupled to the base of the first said bipolar transistor,and whose emitter forms a second input to the said current summing means, with the input common of the first said current mirror being coupled to the second input of the said current summing means and forming the first said current sampling means.

112 A current. mode circuit arrangment as in claim 62 whereby the current gain of the first said current mirror from its input to its first output multiplied by the current gain of the second current mirror from its input to its first output is substantially equal to unity.

113 A current mode circuit arrangment as in claim d4 whereby the current gain of the firs said current mirror from its input to its first output multiplied by the current gain of the second current mirror from its input to its first output is substantially equal to unity.

114 A current mode circuit arrangment as in claims 63 to 5 and 112 whereby the first said current mirror provides the first current output of the said signal combining means 1 and the second said current mirror provides a second current output ot the said signal combining means Cl, the said output amplifier having an additional current input with both inputs forming a differential input, the first said current output and the second said current output forming a differential current output, with the said differential current output being coupled to the said differential current input.

115 A current mode circuit arrangment as in claims 85 to 87 and 113 whereby the first said current mirror provides a first current output of the said current combining means Cl and the second said current mirror provides a first current output of the said signal combining means C2, the said output amplifier having an additional current input with both inputs forming a differential current input, the first said current output and the second said current output forming a differential current output, with the said differential current output being coupled to the said differential current input.

-li6 A current mode circuit arrangment as in claims 62to65,84to87,95to103,109to115, whereby the current gain of the first said current mirror and/or the current gain ot the second said current mirror are adjusted by trimming gain setting resistors which set the current gains of the said current mirrors.

117 A current mode circuit arrangment as in claims

116 whereby the said gain setting resistors are thin film types and the trimming is undertaken by a laser.

118 A current mode circuit arrangment as in claim 62to65,84to87,95to103,109to117 whereby the said current mirrors comprise bipolar or field effect transistors of either conductivity type.

119 A current mode circuit arrangment as in claims.

62to65,84to87,95to103,109to118 whereby the first said current mirror contains transistors of the opposite conductivity type to the second said current mirror.

120 A current mode circuit arrangment substantially as described herein with reference to figs 1 to 3, 6, 7, 11, 18, 19, 20, 23 to 28, 31, 34 to 67, 73, 79, 80, 86 to 93, 102 to 105, 110 to 122, 127 to 130, 137 to 153, 156 to 162, 165, 176 of the accompanyiny drawings.