GB2278211A

GB2278211A - Memory management system

Info

Publication number: GB2278211A
Application number: GB9309169A
Authority: GB
Inventors: Ilan Pardo; Eitan Doron; Yoav Talgam
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1993-05-04
Filing date: 1993-05-04
Publication date: 1994-11-23
Also published as: GB9309169D0

Abstract

A memory management system 4 comprises a memory address translator 8 which matches a received virtual address to a virtual address of a memory address entry which also comprises a physical address and a valid bit. The received virtual address is mapped onto the matched physical address depending on the value of the valid bit. The memory address translator 8 allows for the memory address entries to be validated or invalidated in parallel by using bits of a control word held in a control register 16 to write to the valid bits of the memory address entries. The validation/invalidation is determined by the control bits which are programmable, and so memory address entries can be allocated in a generalised manner. <IMAGE>

Description

Memory Management System Field of the Invention This invention relates to memory management systems.

Background of the Invention Memory management systems which utilise virtual or logical address mapping are well known. In such systems, virtual addresses address entries in a table which map onto physical addresses. The mapping entries and hence the physical addresses to which the virtual addresses translate can be changed or made invalid as necessary. Applications, such as multi-tasked real time embedded applications require efficient run-time address mapping so that the mapping entries can be rapidly changed when the tasks are switched. Efficient run-time address mapping is best achieved by Address Translation Cache (ATC) type structures.

The specific mapping scheme used is highly application dependent. General purpose memory management systems usually change the ATC mapping entries by way of hardware.

It is becoming increasingly popular, however, particularly in embedded control applications, to be able to set specific mappings per task in the ATC and thus, to change ATC mapping entries by way of software. Typically, this achieved by first invalidating all the mapping entries of the exiting task, for example by performing an 'invalidate-all-type' of operation, and then sequentially validating (or loading) all of the mapping entries of the new tasks.

There may also be global mappings, like the mapping of the code and data of the operating system task switch routine, that preclude an 'invalidate-all-type' operation for supervisor mappings of the exiting task. The mapping entries may overlap between tasks in which case, mappings can be changed individually. Each task may use several mapping entries of different types: for example, interrupt routine code (supervisor code), interrupt data (supervisor data), main code (user code) and main data (user data). Some known memory management systems allow invalidation of ATC mapping entries by type: that is, supervisor code or supervisor data or user code or user data.

A disadvantage of using software to change the mapping entries when performing task changes is that it requires a software overhead which can exceed 20 clocks. This can be significantly long in applications having tight real time constraints.

There is therefore a need to design a memory management system which provides fast mapping switching between tasks and which is also relatively cheap to implement since many of the relevant applications which require task changes and mapping switches are cost sensitive.

Summary of the Invention In accordance with the present invention there is provided a memory management system for receiving a virtual address and for controlling the addressing of memory in response thereto, the memory management system comprising: memory address translator means for holding M memory address entries, each entry comprising a virtual address and an associated physical address of the memory and a valid bit, the valid bit being switchable between a first logic value which indicates a valid memory address entry and a second logic value which indicates an invalid memory address entry, the memory translator means for matching a received virtual address to a virtual address of one of the memory address entries and for determining the logic value of the valid bit of the one of the memory address entries and for providing the associated physical address when the valid bit has the first logic value; control register means for receiving and holding a M-bit control word, a bit of the M-bit control word corresponding to a valid bit of the M memory address entries and being programmable so as to have a first logic value or a second logic value; and means for writing the M-bit control word to the valid bits of the M memory address entries whereby the logic value of each of the valid bits is determined by the logic value of the corresponding bit of the M-bit control word.

The memory management system in accordance with the present invention allows for the memory address entries to be validated or invalidated in parallel. Furthermore, the validation/invalidation is determined by the control bits which are programmable, and so memory address entries can be allocated in a totally generalised manner (e.g. with or without map overlaps).

Thus, the present invention provides a fast and flexible system by which memory address entries can be validated/invalidated on task switching.

Brief Description of the Drawings A memory management system in accordance with the present invention will now be described, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a block schematic diagram of a processor incorporating a memory management system in accordance with the present invention; Fig. 2 is a block schematic diagram of an Address Translation Cache (ATC) of the memory management system of Fig. 1; Fig. 3 is a simplified representation of an entry of the ATC of Fig. 2; and Fig. 4 is a representation of the control registers of the memory management system in accordance with the present invention.

Detailed Description of the Drawings Referring firstly to Fig. 1, in order to access memory 6, a CPU 2 sends a memory access request to the memory management system 4. The request includes a virtual address which is translated by an address translator 8 in the memory management system 4 to a physical address of the memory 6.

In a preferred embodiment, the memory address translator 8 is implemented in an ATC 8 as shown in Fig. 2 which has 40 entries.

Each entry (one of which is shown in Fig. 3) comprises a logical address (virtual block 10), a corresponding physical address (physical block 12), a valid bit V[i], and a type bit which designates the type of the entry, that is user or supervisor or data or code. If a virtual address received from the CPU 2 matches a virtual address of one of the 40 entries, and the valid bit V[i] is set, the logical address is mapped to the corresponding physical address which is used by the memory management system 4 to address the memory 6. If there is no match, a miss signal is sent back to the CPU.

The valid bit V[i] of each entry is written to or read with each entry. If the valid bit V[i] is set, the matched logical address is mapped to the physical address. If the valid bit VM is not set, there is no mapping irrespective of whether there is a match of logical addresses.

The memory management system in accordance with the present invention further comprises control registers 16 for holding control words which control the setting and resetting of the valid bits of the ATC entries: one bit of a control word is associated with one valid bit. All the bits of the control words can be set or reset individually and in parallel. Preferably, there are at least two registers: one register VSET for controlling the setting of the valid bits and one register V~CLR for controlling the resetting of the valid bits.

In the preferred embodiment, the valid bits appear as a bit vector grouped into 32 bit words and since there are 40 ATC entries, the two registers are arranged so that each register is divided into two 32 bit registers: one pair of registers to set and one pair to reset the valid bits of the ATC entries.

Fig. 4 is a representation of the two pairs of registers V,SET1, and VSET2, and V CLR1 and V~CLR2 of the memory management system in accordance with the present invention. Writing a one in a particular bit location of a V~SET control word causes the corresponding valid bit of an ATC entry to be set, without affecting any other ATC entry valid bit. Writing a zero maintains the previous value of the corresponding valid bit. Similarly, writing a one in a particular bit location of a V~CLR control word causes the corresponding valid bit of an ATC entry to be cleared, without affecting any other ATC entry valid bit. Writing a zero maintains the previous value of the corresponding ATC entry valid bit.

With reference to Fig. 4, writing one to the i bit in the SET register VSET will set the valid bit of ATC[i]. Writing one to the i bit of the CLR register V~CLR will invalidate the valid bit of ATC[i].

For i > 40, all write attempts to V,CLR[i] or V~SET[i] bits will be ignored. This is represented by the shaded areas of the V~SET2 and V~CLR2 registers. Load control register commands from the registers will return the appropriate valid bits from the ATC entries.

This enables the CPU 2 to read the ATC valid bits in parallel from the registers 16.

In a write operation, the bit locations of the control registers V~SET and VCLR are selectively written to individually or in parallel by the CPU. The selective writing to the control registers is dependent on the new task to which the memory management system is to switch, and may be, for example, by pre-assigned type.

In response to a write control register command generated by the CPU, the control word bits of the registers are read out in parallel to set or reset the appropriate valid bits in the ATC entries. Thus, either one or all of the ATC entries can be validated or invalidated in parallel in as little as one or two clocks.

Since the ATC entries can be selectively validated or invalidated according to the control words in response to one command, the memory management system provides a very fast and simple system of manipulating the ATC entries. This therefore improves the task switching time. Fusrthermore, the selective validation or invalidation of the ATC entries by the corresponding bits of the control words, which can be simply and quickly varied as necessary, provides for a flexible memory management system. A further advantage of the invention is that the ATC can be loaded for various tasks, but only those ATC entries required for a particular task are validated in response to one command.

It will be appreciated that although the invention has been described with respect to an ATC type structure, the invention can be implemented in any associative memory arrangement.

Claims

1. A memory management system for receiving a virtual address and for controlling the addressing of memory in response thereto, the memory management system comprising: memory address translator means for holding M memory address entries, each entry comprising a virtual address and an associated physical address of the memory and a valid bit, the valid bit being switchable between a first logic value which indicates a valid memory address entry and a second logic value which indicates an invalid memory address entry, the memory translator means for matching a received virtual address to a virtual address of one of the memory address entries and for determining the logic value of the valid bit of the one of the memory address entries and for providing the associated physical address when the valid bit has the first logic value; control register means for receiving and holding a M-bit control word, a bit of the M-bit control word corresponding to a valid bit of the M memory address entries and being programmable so as to have a first logic value or a second logic value; and means for writing the M-bit control word to the valid bits of the M memory address entries whereby the logic value of each of the valid bits is determined by the logic value of the corresponding bit of the M-bit control word.

2. A memory management system according to claim 1 wherein the means for writing writes the bits of the M-bit control word to the valid bits in parallel.

3. A memory management system according to claim 1 or 2 further comprising means for reading the bits of the M-bit control word from the control register means so as to determine the logic value of the valid bits.

4. A memory management system according to claim 3 wherein the means for reading reads the bits of the M-bit control word in parallel.

5. A memory management system according to any preceding claim wherein the bits of the M-bit control word are programmed in parallel.

6. A memory management system according to any preceding claim wherein the control register means receives and holds a set control word and a clear control word, a bit of the set control word setting a valid bit to the first logic value when the set control bit has the first logic value and not changing the logic value of a valid bit when the set control bit has the second logic value and a bit of the clear control word clearing a valid bit to the second logic value when the clear control bit has the first logic value and not changing the logic value of a valid bit when the clear control bit has the second logic value.

7. A memory management system according to claim 6 wherein the control register means comprises a set register for receiving and holding the set control word and a clear register for receiving and holding the clear control word.

8. A memory management system according to any preceding claim wherein the memory address translator means is implemented in an ATC.

9. A processing system comprising: a processor; memory; and a memory management system according to any preceding claim, the processor accessing the memory by sending a memory access request comprising a virtual address to the memory management system to provide an associated physical address of the memory.

10. A memory management system substantially as hereinbefore described with reference to the accompanying drawings.