GB2277822A

GB2277822A - A memory system with selectable row power down

Info

Publication number: GB2277822A
Application number: GB9309167A
Authority: GB
Inventors: Daniel Shterman; Eitan Doron
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1993-05-04
Filing date: 1993-05-04
Publication date: 1994-11-09
Also published as: GB9309167D0

Abstract

A memory system (2), having low power consumption in a standby mode, comprises a memory array (4) having a plurality of memory cells (10) arranged in columns and rows, and power control means (6, 8) for receiving a control word and for selectively controlling the power supplied to the rows of the memory array in dependence on bits of the control word whereby the power control means is switchable between a first state in which no power is supplied to the cells of at least one row and a second state in which power is supplied to at least one row. Each row is connected to the power supply via a transistor 30. Each transistor is controlled via a shut-down register 6 which receives data from a data bus. <IMAGE>

Description

Memory System Field of the Invention This invention relates to a memory system. More particularly, the invention relates to a memory system comprising a memory array with power control circuitry.

Background of the Invention Modern processors increasingly require integration of high density memories in order to save space, thereby giving more data on chip at lower cost. Four transistor cell Random Access Memory (RAM) arrays, a typical cell of which is shown in Fig. 1, are often implemented in such processors, since the design of the four transistor array allows for higher density memories. However, the four transistor RAM arrays are generally composed of non-CMOS structures and so have significantly high power consumption. A typical 8K byte array consumes as much as 30mW in standby mode: that is, a 'sleeping' mode when the memory array is not accessed for a long period which is generally when its CPU is not active. This magnitude of power consumption is too high for systems that require low power standby memory, such as battery operated equipment, lap top computers, embedded microcomputers, and general purpose microprocessors in power sensitive applications.

A known solution to the problem of high power consumption is the use of a six transistor cell RAM array, a typical cell of which is shown in Fig. 2. The six transistor RAM array has negligible power dissipation in standby mode. However, the structure of the six transistor array requires twice the area per bit which increases the cost of the device or lowers the operational performance.

Summary of the Invention In accordance with the present invention there is provided a memory system comprising: a memory array having a plurality of memory cells arranged in columns and rows; power control means for receiving a control word and for selectively controlling the power supplied to the rows of the memory array in dependence on bits of the control word whereby the power control means is switchable between a first state in which no power is supplied to the cells of at least one row and a second state in which power is supplied to at least one row.

Brief Description of the Drawings A memory system in accordance with the present invention will now be described, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a circuit diagram of a cell of a four transistor RAM array; Fig. 2 is a circuit diagram of a cell of a six transistor RAM array; Fig. 3 is a simplified block diagram of a memory system in accordance with the present invention; and Fig. 4 is a circuit diagram of a cell of the memory system of Fig. 3.

Detailed Description tof the Drawings Referring to Figs. 3 and 4, a memory system 2 in accordance with a preferred embodiment of the invention comprises a memory array 4 formed of a plurality of RAM cells 10 arranged in columns and rows, and power control circuitry 6, 8 for controlling the data retention versus power of the memory array 4 in the standby mode.

Each RAM cell 10 comprises four FET transistors 12-18. A first transistor 12 has a gate electrode coupled to a row line 20 of the memory array 4, a first current electrode coupled to a NOT bit line 22 and a second current electrode coupled to a first node A.

Node A receives a switched supply voltage SVDD from a first supply line 21. A second transistor 14 has a first current electrode coupled to the first node A, a second current electrode coupled to a second supply line, at for example ground, and a gate electrode coupled to a second node B. Node B is also coupled to the first supply line 21 to receive the switched supply voltage SVDD. A third transistor 16 has a gate electrode coupled to the first node A, a first current electrode coupled to the second node B and a third current electrode coupled to the second supply line. A fourth transistor 18 has a gate electrode coupled to the row line 20, a first current electrode coupled to a bit line 24 and a second current electrode coupled to the second node B.

The RAM cell 10 has a similar structure to the known four transistor cell (of Fig. 1) except that the nodes A and B are coupled to receive a switched supply voltage SVDD rather than VDD. The operation of RAM cell 10 is therefore similar to the known four transistor cells. For example, when the row line is at logic state '0', the transistors 18 and 12 are 'off' and the cell is electrically isolated from its surroundings. The cell is accessed by putting the row line at logic state '1' whereby the logic levels at the bit and NOT bit lines 24 and 22 correspond to the logic state of the cell. Alternatively, the logic state of the cell can be set by the logic levels presented externally to the bit and NOT bit lines 24 and 22.

The memory system 2 in accordance with the present invention supports a standby mode wherein the RAM array 4 can be selectively shut down so as to reduce or even stop its power consumption. This power control function is performed by the power control circuitry 6 and 8, which in the preferred embodiment comprises a control register 6 and switch means 8 coupled to the register 6 and the rows of the memory array 4.

The control register 6 has reset and write inputs, a port for coupling to a data bus and control outputs coupled to the switch means 8. The control register 6 receives a m-bit data word from a CPU (not shown) via the data bus. Each of the m bits corresponds to a control output of the control register 6.

The switch means 8 preferably comprises a plurality of pchannel MOS transistors 30. Each MOS transistor 30 has a gate electrode coupled to a control output of the control register 6, a first current electrode coupled to a third supply line VDD and a second current electrode coupled to at least one of the first supply lines 21 of the array 4 so as to supply the switched supply voltage SVDD.

The number of MOS transistors 30, of which the switch means 8 is comprised, is a trade off between space and how much control is desired over the rows in the array 4. At the extreme, the number of MOS transistors 30 is equal to the number of rows in the RAM memory array 4. In the preferred embodiment, four MOS transistors were implemented for a memory array 4 comprising thirty-two rows.

The operation of the memory system 2 will now be described.

When the control register 6 receives a reset signal, all the bits of the register are set to logic '1' whereby all the control outputs are at logic '1' and all the corresponding MOS transistors 30 are 'off. No power is supplied to any of the cells 10 of the memory array 4. The RAM memory array 4 is in a power shut down state. When the memory array 4 is required for use, the CPU sends a data word to the control register to clear the register bits. Only the register bits which correspond to the rows of the memory array 4 which are to be written to or read from at that time need be cleared. Thus, the data word comprises '0's for those rows to be cleared and 'l's otherwise. With a logic '0' at a control output, the corresponding MOS transistor 30 is 'on', whereby a voltage SVDD is supplied to the appropriate cells 10. All or part of the array, depending on the data word, is in a power wake up state. In order to write to (read) any uninitialised cells in the memory array 4, the user should wait a predetermined time period to allow time for the array to resolve the meta-state existing during the 'waking-up' of the memory array.

In order to switch one of the rows of the memory array 4 into the shut down state, the appropriate bit of the control register is set via the data bus. As a result, the switched row of the memory array 4 loses its content and stops consuming power. Thus, part or all of the RAM memory array 4 may be switched to the shut down state during the standby mode by setting the appropriate control register bits.

In summary, the present invention provides a memory system comprising a four transistor cell array and integrated power control circuitry which allows fine power control over data retention versus power in the standby mode. Thus, the present invention allows for the higher density advantages of the four transistor cell, which increases the amount of RAM that may be integrated into a processor, but has controllable power dissipation and so can be used in low power applications.

It will be appreciated that although the switch means has been implemented as a plurality of p-channel MOS transistors, the switch means may instead be implemented as a plurality of nchannel MOS transistors.

Claims

1. A memory system comprising: a memory array having a plurality of memory cells arranged in columns and rows; power control means for receiving a control word and for selectively controlling the power supplied to the rows of the memory array in dependence on bits of the control word whereby the power control means is switchable between a first state in which no power is supplied to the cells of at least one row and a second state in which power is supplied to at least one row.

2. A memory system according to claim 1 wherein the power control means comprises: a control register coupled to receive the control word and having a plurality of outputs; and switch means having a plurality of inputs coupled to the plurality of outputs of the control register, a supply input for receiving a first reference signal and a plurality of outputs coupled to the rows of the memory array, the switch means in dependence on the bits of the received control word being switchable between the first state in which no power is supplied to a row and the second state in which power dependent on the first reference signal is supplied to a row via an output of the switch means.

3. A memory system according to claim 2 wherein the switch means comprises a plurality of MOS transistors, each of the MOS transistors having a control electrode coupled to an output of the control register, a first current electrode coupled to receive the first reference signal and a second current electrode coupled to an output of the switch means.

4 A memory system according to claim 2 or 3 wherein m bits of the control word control the switching of the switch means, the control register has m outputs corresponding to the m bits, and the switch means comprises m outputs.

5. A memory system according to claim 4 wherein one output of the plurality of outputs of the switch means is coupled to a predetermined number of rows of the memory array.

6. A memory system substantially as hereinbefore described with reference to Figs. 3 or 4 of the drawings.