GB2276033A - Integrated circuit package - Google Patents

Integrated circuit package Download PDF

Info

Publication number
GB2276033A
GB2276033A GB9404559A GB9404559A GB2276033A GB 2276033 A GB2276033 A GB 2276033A GB 9404559 A GB9404559 A GB 9404559A GB 9404559 A GB9404559 A GB 9404559A GB 2276033 A GB2276033 A GB 2276033A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
circuit package
substrate
package
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9404559A
Other versions
GB2276033B (en
GB9404559D0 (en
Inventor
Peter Jones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems PLC
Original Assignee
British Aerospace PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Aerospace PLC filed Critical British Aerospace PLC
Publication of GB9404559D0 publication Critical patent/GB9404559D0/en
Publication of GB2276033A publication Critical patent/GB2276033A/en
Application granted granted Critical
Publication of GB2276033B publication Critical patent/GB2276033B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/16315—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

An integrated circuit package comprises a ceramic sub-package (1) a substrate (5) mounted on shoulders (4) therein, a lid (9) and connecting pins (10). The sub-package (1) and substrate carry a multiplicity of naked semi-conductor dies (2A, 2B, 2C, 6A, 6B, 6C) which are connected to one another and the subpackage (1) via wire bonds (3, 7, 8). If desired, further die-carrying substrates may be stacked within the sub-package (1) thus achieving a high packing density of semi-conductor dies in a single package. <IMAGE>

Description

INTEGRATED CIRCUITS This invention relates to integrated circuits and particularly to packaging for semi-conductor devices.
An integrated circuit package may be fabricated by arranging a multiplicity of bare semi-conductor dies on a series of flat substrates which are stacked one on top of the other. European Patent Application EP-A-478,426 (Figure 13) discloses a package incorporating stacked substrates, each substrate being populated, on one of it s faces by semiconductor dies. The stack is supported by a lower unpopulated substrate.
This known configuration has the disadvantages of poor mechanical rigidity and the need for tortuous electrical interconnections between dies.
This invention aims to provide an integrated circuit package which combines a high packing density of a standard die product with ease of reworking and reliability.
Accordingly, the invention consists of an integrated circuit package including a lower surface substrate which is provided with a shoulder on which is supported an upper substrate and in which each substrate supports at least one bare semi-conductor die.
In this way, the lowermost substrate forms a sub-package which can be provided with a lid and external connecting pins to produce an integrated circuit for connection to a printed circuit board while the shoulder provides mechanical support for the upper substrate.
In order to maximise packing density, bare dies and other electronic devices can be provided on both sides of the upper substrate.
Optionally, further sets of shoulders could be incorporated to support further substrates.
Each substrate may be constructed from either low temperature (ie. approximately 86Oc) or high temperature (ie.
approximately 1600'c) multilayer, co-fired material. Bare dies can be mounted on each substrate using epoxy adhesive or solder and the necessary electrical connections made by wire-bonding. Electrical interconnections between substrates are achieved by virtue of the multilayer structure and wire bonding from the package to each substrate.
To facilitate pressure balancing and the back-filling of an inert atmosphere, each subsequent substrate is preferably provided with small holes.
Some embodiments of the invention will now be described, by way of example only, with reference to the drawings of which: Fig. 1 is a cross-sectional view of an integrated circuit package in accordance with the invention; and Fig. 2 is a cross-sectional view of an alternative embodiment.
In Figure 1, a sub-package 1 which is roughly U-shaped in cross-section is formed from multi-layer, co-fired material.
This material is essentially ceramic incorporating metal conducting tracks, pads and vias. Methods of forming this type of material are well-known and will not be described herein. Naked, semi-conductor dies 2A, 2B and 2C are mounted on the floor of the subpackage (which forms a lower substrate 1A) using epoxy adhesive and are connected to conducting pads incorporated within the sub-package 1 by thin wires 3.
The sub-package 1 incorporates a shoulder 4 on which is located a flat ceramic (upper) substrate 5. Further support can be given to the substrate 5 by providing support walls (not shown) extending between the subpackage floor and the lower surface of the substrate 5. The substrate 5 is fixed in place with epoxy adhesive having first been populated with naked semi-conductor dies 6A, 6B, 6C. Wire bonds 7 and 8 form the electrical interconnections between the dies 6A, 6B, 6C and the substrate 5 and the substrate 5 and sub-package 1 respectively. Interconnections between the substrate 5 and the floor of the sub-package 1 is achieved by virtue of the multilayer structure of the sub-package.
The above assembly is provided with a lid 9 and external connecting pins 10.
The package of Fig. 1 can be connected to printed circuit boards by through-hole or surface mount interconnection techniques. It can be filled with an inert gas and hermetically sealed using conventional methods.
It will be appreciated that during assembly of the integrated circuit package of Fig 1, the lower substrate 1A and upper substrate 5 can be tested independently and reworked if necessary.
The materials and assembly techniques used to fabricate the package are well proven and capable of producing packages with very high reliability over a temperature range -55 to 125 c.
It will also be appreciated that a high packing density is attainable and consequently, the package is particularly suitable for use with dies which comprise memory modules. In general, the invention can be applied equally well to analogue or digital circuits and is adaptable for use with dies supplied by most manufacturers.
A second embodiment which has all of the above advantages yet achieves a greater packing density is shown in Fig 2.
In Fig 2 two packages 11 and 12 of the type described with reference to Fig 1 are fixed to one another in a "back to back" configuration. They share common external connecting pins 13 with external wired connections 14 provided between the upper package 11 and said pins 13.
Further embodiments can be configured by populating both sides of the upper substrate 5 (of Figs 1 and 2) with semi-conductor dies, and other electronic devices.

Claims (10)

1. An integrated circuit package including a lower substrate which is provided with a shoulder on which is supported an upper substrate and in which each substrate supports at least one bare semi-conductor die..
2. An integrated circuit package as claimed in claim 1 in which the upper substrate is provided with small holes.
3. An integrated circuit package as claimed in any preceding claim in which each substrate is constructed from multi-layer, co-fired material.
4. An integrated circuit package as claimed in any preceding claim in which the upper subsequent substrate is provided with bare semi-conductor dies on both of its sides.
5. A integrated circuit package as described in any preceding claim including support walls extending between the lower and upper substrates.
6. An integrated circuit package as claimed in any preceding claim in which the bare semi-conductor dies are electrically connected to a substrate by means of wires.
7. An integrated circuit package as claimed in any preceding claim which is provided with a lid and external connecting pins.
8. An integrated circuit package as claimed in any preceding claim incorporating one or more further shoulders for supporting one or more further substrates.
9. An integrated circuit package incorporating two packages as claimed in any preceding claim which are fixed to one another in a back to back configuration, each of said two packages sharing common external connecting pins.
10. An integrated circuit package substantially as hereinbefore described with reference to the drawings.
GB9404559A 1993-03-11 1994-03-09 Integrated circuits Expired - Fee Related GB2276033B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB939304956A GB9304956D0 (en) 1993-03-11 1993-03-11 Integrated circuits

Publications (3)

Publication Number Publication Date
GB9404559D0 GB9404559D0 (en) 1994-04-20
GB2276033A true GB2276033A (en) 1994-09-14
GB2276033B GB2276033B (en) 1996-08-07

Family

ID=10731843

Family Applications (2)

Application Number Title Priority Date Filing Date
GB939304956A Pending GB9304956D0 (en) 1993-03-11 1993-03-11 Integrated circuits
GB9404559A Expired - Fee Related GB2276033B (en) 1993-03-11 1994-03-09 Integrated circuits

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB939304956A Pending GB9304956D0 (en) 1993-03-11 1993-03-11 Integrated circuits

Country Status (1)

Country Link
GB (2) GB9304956D0 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6364542B1 (en) * 2000-05-09 2002-04-02 National Semiconductor Corporation Device and method for providing a true semiconductor die to external fiber optic cable connection
WO2003021678A1 (en) * 2001-08-29 2003-03-13 Motorola Inc Package for electronic components and method for forming a package for electronic components
US6655854B1 (en) 2001-08-03 2003-12-02 National Semiconductor Corporation Optoelectronic package with dam structure to provide fiber standoff
EP1556895A2 (en) * 2002-10-08 2005-07-27 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US7001083B1 (en) 2001-09-21 2006-02-21 National Semiconductor Corporation Technique for protecting photonic devices in optoelectronic packages with clear overmolding
EP1665374A2 (en) * 2003-08-19 2006-06-07 Delaware Capital Formation, Inc. Multiple cavity/compartment package

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6364542B1 (en) * 2000-05-09 2002-04-02 National Semiconductor Corporation Device and method for providing a true semiconductor die to external fiber optic cable connection
US6655854B1 (en) 2001-08-03 2003-12-02 National Semiconductor Corporation Optoelectronic package with dam structure to provide fiber standoff
WO2003021678A1 (en) * 2001-08-29 2003-03-13 Motorola Inc Package for electronic components and method for forming a package for electronic components
US7001083B1 (en) 2001-09-21 2006-02-21 National Semiconductor Corporation Technique for protecting photonic devices in optoelectronic packages with clear overmolding
US7195955B2 (en) 2001-09-21 2007-03-27 National Semiconductor Corporation Technique for protecting photonic devices in optoelectronic packages with clear overmolding
EP1556895A2 (en) * 2002-10-08 2005-07-27 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
EP1556895A4 (en) * 2002-10-08 2009-12-30 Chippac Inc Semiconductor stacked multi-package module having inverted second package
EP1665374A2 (en) * 2003-08-19 2006-06-07 Delaware Capital Formation, Inc. Multiple cavity/compartment package
EP1665374A4 (en) * 2003-08-19 2010-03-03 Capital Formation Inc Multiple cavity/compartment package

Also Published As

Publication number Publication date
GB2276033B (en) 1996-08-07
GB9404559D0 (en) 1994-04-20
GB9304956D0 (en) 1993-04-28

Similar Documents

Publication Publication Date Title
US6195268B1 (en) Stacking layers containing enclosed IC chips
US4730232A (en) High density microelectronic packaging module for high speed chips
JP3239909B2 (en) Stackable 3D multi-chip semiconductor device and its manufacturing method
US6890798B2 (en) Stacked chip packaging
EP0638931B1 (en) Multi-chip module
US4975765A (en) Highly integrated circuit and method for the production thereof
US5620928A (en) Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
EP1097467B1 (en) Ic stack utilizing secondary leadframes
US5386341A (en) Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US6670702B2 (en) Stackable ball grid array package
US6638792B2 (en) Method for fabricating BOC semiconductor package
US6479321B2 (en) One-step semiconductor stack packaging method
US5909058A (en) Semiconductor package and semiconductor mounting part
US6628527B2 (en) Mounting structure for electronic parts and manufacturing method thereof
US20080157327A1 (en) Package on package structure for semiconductor devices and method of the same
US7161251B2 (en) Partially populated ball grid design to accommodate landing pads close to the die
US5849608A (en) Semiconductor chip package
WO1987004316A1 (en) Ultra high density pad array chip carrier
WO1997025742A1 (en) Multi-chip integrated circuit package
JPS6290953A (en) Resin-sealed semiconductor device
JPH0357257A (en) Prearranged on surface of outer heat sink high density semiconductor memory module and forming method of the same
GB2276033A (en) Integrated circuit package
WO2000002246A1 (en) Double-sided electronic device
US5051869A (en) Advanced co-fired multichip/hybrid package
US5706172A (en) Stacked semiconductor package having supporting bars and a socket therefor

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee