GB2275839A - Non-saturating logic circuit - Google Patents

Abstract

A non-saturating logic circuit similar to I<2>L has a PNP injector 5 feeding a current mirror output stage 2, 3, 4, and includes a voltage clamp 7 which prevents the output transistors of stages connected to input node 1 from saturating. Vcc may be as low as 0.9 V. <IMAGE>

Description

Logic Circuits The present invention relates to logic circuits, and in particular although not exclusively to non-saturating transistor logic circuits.

Integrated circuits powered from batteries require devices with very low current consumption, to ensure good battery life, and if the integrated circuits incorporate logic circuits these should be low power circuits, particularly if they are to operate at low speeds. In addition the devices used in the logic circuits ideally should be standard devices that are well characterised and modelled, requiring no extra process steps or special process control, and should use up as small an area of silicon as possible.

For certain applications, such as pagers, it is also desirable to have circuits which can be powered from a single cell, providing a voltage which can be as low as 1.0 or 1.1 volts.

The merged device structure of I 2L logic circuits has been used to minimise the area of silicon required, but in presently used processes 12L can often require special process steps or control, making it unattractive. Also the devices in I2L tend to operate into saturation regions, where device modelling is often unsatisfactory. It is possible to make I2L type circuits from normal devices, i.e. without using a merged structure, but such devices still operate in their saturation regions.

Emitter-coupled logic circuits use devices out of their saturation regions, and can be used at low currents. However, due to the need to keep a constant logic voltage swing across the load resistors used in emitter-coupled circuits, the resistors required for low current operation can be very large and require a considerable area of silicon.

According to the present invention a transistor logic circuit comprises a current mirror circuit in which a first transistor has its control and output electrodes connected together, connected to an input terminal of the circuit and connected to the control electrode of at least one output transistor, and there are provided means to supply a current of a controlled value to said interconnected control and butput electrodes and means substantially to prevent the potential at said input terminal in operation from falling below a predetermined value.

Preferably the means to supply a current of a controlled value comprises a second current mirror circuit. The means to prevent the potential at said input terminal from falling below a predetermined value may comprise a further transistor having its control electrode connected to a point of reference potential.

A logic circuit in accordance with the present invention will now be described by way of example with reference to the accompanying drawing, which shows the circuit diagrammatically.

Referring to the drawing the circuit is functionally equivalent to an I2L logic circuit, in that it has a single input and one or more outputs, a two-output circuit being shown in the drawing. The input is connected to an input node 1, which is also connected to the interconnected base and collector electrodes of an npn transistor 2 and to the base electrodes of two npn output transistors 3 and 4, the collector electrodes of these output transistors being connected to the outputs of the circuit.

A current of an accurately controlled value is supplied to the input node 1 by way of a pnp transistor 5, which may for example be the output device of a current mirror type of circuit the remainder of which is represented schematically within the box 6.

The input node 1 is also connected to the emitter electrode of an npn transistor 7 to the base electrode of which is applied a reference voltage of, for example, 1.3VBE to 1.5VBE above the local earth potential VEE, derived from a VBE multiplier circuit 8.

The emitter electrodes of the transistors 2, 3 and 4 are connected to local earth potential VEE, while the emitter electrode of the transistor 5 and the collector electrode of the transistor 7 are connected to a positive supply line Vcc which may, for example, be as little as 0.9 volt positive with respect to VEE.

In operation, when the input is at a logic high voltage, that is, when substantially no current is drawn from the node 1 to VEE by way of any external circuits connected to the input, the current supplied by the transistor 5 flows into the interconnected base and collector electrodes of the transistor 2, whereby the input logic high voltage is clamped to a value equal to the VBE voltage of transistor 2 above VEE. Under these conditions the transistor 7 is substantially non-conducting. Since the transistor 2 is conducting the output transistors 3 and 4 of the current mirror circuit formed by the transistors 2, 3 and 4 are also conducting.These transistors 3 and 4 have larger emitter areas than transistor 2, for example they may be twice as large, and are therefore each fully capable of drawing more current from the input of a following logic circuit than that provided by the current source in that following logic circuit.

When current is drawn to VEE from the input node 1 by, for example an output transistor of a preceding logic circuit, the voltage at the node 1 falls and the transistor 2 becomes non-conducting, switching off the output transistors 3 and 4. The fall in voltage is limited, by conduction of the transistor 7, to VBE of the transistor 7 below the reference voltage from the circuit 8, which prevents the output transistor of the preceding logic circuit from going into saturation. The voltage at the input node 1 therefore ranges from a logic high value of VBE (of transistor 2) above VEE down to a logic low value of 0.5 to 0.25 VBE above VEE, say, from 0.7 volts down to 0.2 volts above VBE.

While the output transistors 3 and 4 are off their collector electrodes will be set either to a logic high value by the input of the following logic circuit, if all other connections to that input from other logic circuits are drawing no current, or to a logic low value if any of the other logic circuits are drawing current.

The minimum operating voltage for the logic circuit described above is determined by the VBE voltage of transistor 2 plus the minimum VCE voltage of transistor 5, such that transistor 5 is not in hard saturation. As mentioned above this can be as low as 0.7 + 0.2 = 0.9 volts.

The logic circuit described above therefore has the advantages that a) it can operate from a single cell supply voltage, b) it operates all transistors in their non-saturated regions, c) it can be made very low power if required, d) it can use standard process devices if required, e) it enables the use of logic function design procedures established for I2L logic, and f) the speed of the circuit can be programmed by changing the value of current provided by transistor 5, without any other design changes such as the change of resistor values required in emitter-coupled logic circuits.

Claims (4)

1. A transistor logic circuit comprising a current mirror circuit in which a first transistor has its control and output electrodes connected together, connected to an input terminal of the circuit and connected to the control electrode of at least one output transistor, and there are provided means to supply a current of a controlled value to said interconnected control and output electrodes and means substantially to prevent the voltage drop across said first transistor in operation from falling below a predetermined value.

2. A transistor logic circuit in accordance with Claim 1 wherein the means to supply a current of a controlled value comprises a second current mirror circuit.

3. A transistor logic circuit in accordance with Claim 1 or Claim 2 wherein the means to prevent the voltage drop across said first transistor from falling below a predetermined value comprises a further transistor having its control electrode connected to a point of reference potential.

4. A transistor logic circuit substantially as hereinbefore described with reference to the accompanying drawing.