GB2273804A - Dynamic visual representation of simulated circuit information - Google Patents

Abstract

An improved technique for processing large amounts of information and displaying that information graphically. The graphic display focuses attention to suspect areas employing colours and shading techniques to quickly focus the users attention to problem areas. The display shows selected net states across respective raster lines e.g. N21, N20 etc for a selected period of a VLSI circuit simulation. As the net states changes between logic 1, logic zero or an undefined state, the colour of the raster line changes. The large number of nets which can thus be displayed and the time sequence of changing states can enable rapid evaluation of the VLSI circuit performance and the existence of errors or faults in the design. <IMAGE>

Description

MULTI-DIMENSION VISUAL ANALYSIS Field of the Invention This invention generally relates to improvements in design analysis of logic and circuit simulators and more particularly to a technique that employs visualization techniques to analyse and display large volumes of data more effectively. This application is divided out of application number 9015322.2 filed 12 July 1990.

Description of the Invention High speed logic and circuit simulators are used throughout the computer industry to aid in the design of complex systems. High performance simulators generate enormous amounts of data mappking storage of the information impractical. In order to pinpoint problems effectively, the information must be displayed to the designer as it is generated. However, current technology only allows the information to be presented in the form of waveforms, tables or compared to known values to detect problems. A prior art technique for analyzing information on a computer channel is disclosed in US Patent 4,773,003. This patent detects a pre-selected signal line event and displays the information on a two-dimensional display for further manual analysis.

VLSI designers have difficulty trying to debug designs when a large amount of information is displayed without trend or summary information. For#example, it is very difficult for a designer to analyze the effect of power reset on all macros. The source of a problem is often very difficult to trace to its cause. A typical network predecessor tree for the problem just described can be very large and quite deep.

The tree also grows quickly to obscure the source of the problem further.

State of the art waveform displays help the designer in the analysis of networks. However, they only focus on one aspect of the problem at a time and have no capability for correlating multiple functions to decipher the common source of the problem.

Waveform programs are offered by many of the Engineering Design Association (EDA) vendors such as the LSIM simulator, ZYCAD, IKOS and Mentor. A standard approach plots the information on two-dimensional waveforms for each net as a function of time. The plots are displayed on a graphics device for further manual interrogation. As many as fifty nets are plotted in the vertical direction while time is plotted from an origin of zero at the extreme left-hand side. Figure 1 shows an example of a prior art net display.

To debug many networks and visualize the simulation information globally, a new approach is necessary.

According to the invention, a method for dynamically representing simulated circuit network information visually on a raster scan display screen comprises the steps of: selecting from the network a group of nets the states of which are to be represented; allocating one or more consecutive scan lines across the display to represent the states of each selected net of said group in a predetermined order of nets, with scan line length representing in time the predetermined number of clock cycles in a simulation sequence to be run; selecting unique display attributes to indicate and represent on the screen transitions from one net state to another during running of said simulation sequence; running said simulation sequence through said predetermined number of simulation clock cycles and detecting net state changes during each cycle; and raster scanning the display screen in synchronism with the simulation sequence, changing display attributes in accordance with net state change; whereby the resulting screen display provides a visual representation of propagation of states through the selected group of nets as a function of time.

The invention employs a computer and graphics display for processing large amounts of information and displaying that information graphically. Software processing of the information and graphic display of the processed information focuses attention to suspect areas employing colours and shading techniques to quickly call the user's attention to problem areas.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, aspects and advantages of the invention will be better understood from the following detailed description of the preferred embodiment of the invention with reference to the accompanying drawings, in which: Figure 1 shows a prior art example of a waveform display of nets; Figure 2a is an illustration of a many net display in accordance with the invention; Figure 2b is a blowup of a waveform display of one network of a many net display in accordance with the invention; and Figure 3 is a flowchart showing the logic for implementing a many net display in accordance with the present invention; and Figure 4 is a block diagram of the hardware in accordance with the subject invention.

Starting with the simple two-dimensional multiple net display as shown in Figure 1, a simple initial step entails the compression of the vertical plots until all plots are compressed. Thus, the transition from the lowest state to the highest state would be shown as a line color change not a vertical deflection of a polygon waveform. As more and more net states are plotted on one screen, the limiting factor is the number of scan lines on the display. The limit is reached when the logic states are represented by a single pel or line of pels and encoded using color as a differentiating factor.

The waveform of the clock net in Figure 1, input net 10, required one-hundred pixels (or pels) to show the logic state transition. Employing the technique just described, the rise and fall transition of output network 20 (one of two output nets) in Figure 1 is represented in Figure 2 as output net 01 by colour differences on one horizontal scan line. Two red pixels are indicative of the undefined state, then one green pixel for the logical down state and two blue pixels for the logical up state. The green pixels are represented in Figure 2 by white square areas, while the red pixels are represented by cross-hatching downwards from left to right, and the blue pixels are represented by cross-hatching upwards from left to right. Similarly, the other output net shown in Figure 1 is represented in Figure 2 as output net 02.

In Figure 2 time is plotted on the X-axis while each line of the Y-axis is a separate net. So, for example, in net 20 at 30 a transition from logical high to undefined is indicated by the area of cross-hatching running from left to right changing to an area of cross-hatching falling from left to right. In Figure 2, each net occupies a single scan line.

Thus, a group of undefined nets would be visible as a red area 40 on the display.

The resulting display has patches of color that change from left to right as the simulation proceeds in time. By allowing the user to select the vertical order of the net display, for example net predecessor, net successor, or distance from input or output port, various images are created to enhance the visualization process.

Referring to Figure 2, the output net 02 is undefined at time zero 25, but become defined by time four 27. The net represents a typical power reset problem of a microcomputer or a fetch to an invalid address. A user notes that the net becomes undefined at time five, but the cause is not apparent based on the display in Figure 1. Using techniques of the prior art, such as the waveforms illustrated in Figure 1, the user would have to select the specific output net, and then begin his trace backwards through multiple windows and networks. In Figure 2, the capacity to visualize many more networks enables a comprehensive view of a plurality of networks and the ability to pinpoint the source of an error quickly and accurately.

Many line drawing routines are presently available for implementing the line drawing calls of the invention.

Packages such as the Graphics Programmer's Hierarchical Interactive Graphic System (GraPhigs) or the IBM 3277 Graphics Attachment PRQ described in IBM publication SH20-2137 provide the type of graphics support necessary to implement the invention. The graphic packages are designed to execute on a variety of standard processors and displays such as IBM's PC/RT with corresponding high resolution graphic's display or the IBM 5085 controller attached to a System/370 Host to drive an IBM 5080 display as shown in Figure 4.

The logic for implementing the invention is displayed in Figure 3. In function block 100, the mapping of-the network is determined. Information pertaining to the colour or intensity of each electrical state and the maximum number of nets to display in the raster image is predefined by the user in conjunction with function block 110. Then, the net locations are allocated by logical or physical nearest neighbors in function block 120. The user must-then select the subset of nets that can be displayed on the display in function block 130.

The time window of interest is selected next in function block 140. Then the number of time steps is calculated in function block 150, and the delta movement in the horizontal direction for each step is calculated in function block 160.

A loop is used to process each net data simulation as time elapses commencing at function block 170 where the display is reset for the particular horizontal (x) coordinate.

Function block 180 resets the subnet data pointer to the start of the left side of the display and function block 190 increments the display to the next vertical (y) location for displaying the next net's state. The net is incremented in function block 200 to get the next net simulation information.

Then an inner loop is entered at function block 210 for processing the net transition information. Function block 210 increments through the transition information until the net is completed as tested in decision block 250. A test for a transition in the net data is performed at decision block 220 and the information is plotted at 240 if a transition is detected in decision block 230.

Following the plot step at function block 240, or a detection of no transition at decision block 230, control returns to decision block 250 to determine if the net processing is complete. If it is not, then control returns to the inner loop at function block 210 to continue to process net information. If it is complete, then control returns to function block 170 to increment to the next net.

Processing continues until the information is halted or the process is interrupted.

The many nets display allows a designer to look at large chip macros that get a summary of its behaviour by looking at one graphic image.

Claims (4)

1. A method for dynamically representing simulated circuit network information visually on a raster-scan display screen comprising the steps of: selecting from the network a group of nets the states of which are to be represented; allocating one or more consecutive scan lines across the display to represent the states of each selected net of said group in a predetermined order of nets, with scan line length representing in time the predetermined number of clock cycles in a simulation sequence to be run; selecting unique display attributes to indicate and represent on the screen transitions from one net state to another during running of said simulation sequence; running said simulation sequence through said predetermined number of simulation clock cycles and detecting net state changes during each cycle; and raster scanning the display screen in synchronism with the simulation sequence, changing display attributes in accordance with net state change; whereby the resulting screen display provides a visual representation of propagation of states through the selected group of nets as a function of time.

2. A method as claimed in claim 1, in which selection of nets to form a group is determined having regard to a known relationship between the nets.

3. A method as claimed in claim 1 or claim 2, in which the order in which nets are mapped to the screen is determined having regard to a known relationship between nets in the group.

4. A method as claimed in claim 1, claim 2 or claim 3, in which each net state is represented by a unique colour and a change from one net state to another is represented on the screen by a change from the colour representing the one state to that representing the other state.