GB2270220A - Linearised floating MOS resistance - Google Patents

Abstract

MOS transistor M1 acts as a floating resistor, e.g. for use in active filters, the resistance of which can be adjusted by current sources 16, 18, 20. The average of the source and drain voltages is generated by circuit 10 (transistors M2 - M5) at node 13, and this voltage is scaled and offset by the diode-connected transistor M6 to provide a gate drive for M1 which reduces nonlinearity due to body effect. <IMAGE>

Description

A CMOS INTEGRATED CIRCUIT This invention relates to a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit, and in particular to an improved technique for making an integrated circuit CMOS transistor function as a linear floating two-terminal resistor.

In CMOS integrated circuit technology, resistors take up a relatively large area, particularly in the case of high valued components, and are subject to high tolerances. For these and related reasons, there has been a considerable volume of research devoted to finding ways of making a CMOS transistor function as a resistor. The problems that arise are due to the fact that whereas a resistor has only two terminals, a CMOS transistor has four, all of which can influence the current flowing between the pair that are designated as the source and drain. Furthermore, in an ideal resistor, the current is directly proportional to the difference in the potential across its terminals, i.e. it is a linear device.In the CMOS transistor, even when it is operating in the so-called linear region, the current flowing between the drain and source is a non-linear function of the potential difference between the source and drain and has a large second order (quadratic) distortion term. In addition, the drain current varies in a nonlinear way when the potential between the source and substrate varies; this latter phenomenon being referred to as the body effect. In fact, the only linear relationship is that between the drain current and the gate-source potential and this has been exploited in the design of twoport trans conductors.

Other than using fully balanced circuits as a means of suppressing even order distortion, as proposed by Y.

Tsividis, M. Banu & J. Khoury in "Continuous-time MOSFET-C filters in VLSI" IEEE Trans Circuits & Sys, Vol. CAS-33, Feb. 1986 pp. 125-140, it is well known that linearity can be improved in several ways, most of which rely on the fact that the principal non-linear components in pairs of transistors can be made to cancel by connecting devices in series or parallel and by applying appropriate signals to the gate and bulk terminals (see M. Banu & Y. Tsividis in "Fully integrated active RC filters", Proc. IEEE Int. Symp.

circuits & Sys., 1983 pp. 602-605 and P.M. Van-Peteghem & BR< G.L. Rice in "New CMOS resistor implementation for linear IC applications", Electronics Letters, Vol. 24, No. 5, March 1988 pp. 288-290) or by using cross-coupled transistors as described, for example, by Z. Czarnul in "Novel MOS resistive circuit for synthesis of fully integrated continuous-time filters", IEEE Trans. Circ. & BR< Sys., Vol. CAS-33, No. 7 1986. Schemes that rely on cancellation are subject to a significant disadvantage in that integrated components cannot be perfectly matched and the imperfect cancellation arising from mismatches can result in unacceptable distortion levels.It may also be noted that compensating for the so-called body effect component of non-linearity by injecting a signal into the substrate can only be achieved by putting the transistors into separate "isolated" wells on the substrate; that is, giving each transistor its own "substrate". However, separate wells are generally undesirable in that they occupy a larger area than the same number of devices in a common well, but also because of increased risk of "latch up" which at best would cause maloperation and at worst could result in the chip being destroyed by uncontrolled conduction.

It is an object of this invention to create a substantially linear resistance using CMOS transistor circuitry which avoids the mismatching disadvantage referred to above.

According to this invention we provide a CMOS integrated circuit including a circuit arrangement which comprises a transistor having drain, source, gate and bulk terminals, a common-mode voltage generator for generating the average of the drain and source voltages, and means for modifying the average voltage and applying the resultant voltage to the gate terminal of the transistor whereby the transistor acts as a substantially linear resistance between its drain and source terminals.

More particularly, we provide a CMOS integrated circuit including a circuit arrangement which acts as a resistance and which comprises: a first transistor having drain, source, gate and bulk terminals; a common-mode voltage generator having inputs associated respectively with the drain and source terminals of the first transistor for generating at an output of the generator a voltage which is the average of the voltage on the drain terminal and the voltage on the source terminal; and a second transistor having a source terminal connected to the output of the common-mode voltage generator and drain and gate terminals which are coupled to the gate terminal of the first transistor.

The modified voltage applied to the gate terminal of the resistor-simulating transistor is related to the average voltage by the expression Vg = a + bVav where Vs is the modified voltage, Vav is the average voltage, a is a constant, and b is a multiplying factor dependent on the substrate voltage. With a second transistor having its drain terminal coupled to its gate terminal, i.e. acting as a diode-connected transistor, it is preferable to couple it in the circuit arrangement such that it passes a preset output from a constant current element.

The common-mode generator may comprise two pairs of transistors and a pair of constant current elements, each such constant current element being coupled to source terminals of the transistors of a respective pair. The gate terminals of one transistor of each pair of transistors is then coupled to a respective one of the drain and source terminals of the first transistor, the gate terminals of the other transistors of the pair of transistors being coupled together as well as to the drain terminals of the said other transistors to form the output of the common-mode generator. The drain terminal of the said one transistor of each pair is coupled to a voltage supply.These two current elements and the current element supplying the second (diode-connected) transistor may conveniently all generate currents of the same magnitude, and the common-mode generator output may be arranged to sink or source a current which is also of the same magnitude and is preferably the drain current of the diodeconnected transistor.

The above-mentioned transistors are preferably n-channel devices, but may be p-channel devices.

In this way, it is possible to linearize the characteristics of a single transistor and, consequently, to avoid the mismatching problem evident in the prior art.

Furthermore, all of the key components can be fabricated in a common well which means that the substrate can be connected to the appropriate voltage supply rail thereby minimising latch up and reducing the magnitude of the body effect problem. Alternatively, each differential pair of transistors of the common-mode voltage generator can be fabricated in a separate respective well to reduce the threshold voltage for these devices. The compensation or linearization is effected by applying a signal only to the gate terminal of the controlled device (i.e. the device which functions as a resistor).

The resistor can be set to a nominal value by adjusting integrated circuit process parameters at the design stage, and can be electronically adjusted by simultaneously adjusting the magnitude of the currents generated by the constant current sinks and sources.

It is possible to arrange for the circuit arrangement to act as a fully floating resistor and, since it is an individual device which is linearized, can be used to construct low distortion circuits which are single-ended, thereby avoiding the cost and complexity associated with having to use balanced structures as a means of reducing even-order distortion as in the prior art.

The invention will now be described by way of example with reference to the drawings in which: Figure 1 is a circuit diagram illustrating the principle of the invention; Figure 2 is a more detailed circuit diagram of part of an integrated circuit in accordance with the invention; Figure 3 is a circuit diagram of current sources which may be used in the circuit arrangement of Figure 2; and Figure 4 is a circuit diagram of a simulated floating resistor using p-channel transistors, instead of n-channel transistors as in Figure 2.

When the behaviour of a CMOS transistor is modelled in a simplistic manner, it can be shown that a degree of linearization can be achieved by applying to the gate terminal a voltage signal consisting of a d.c. component which biases the device into a conducting regime plus an average or common-mode voltage which is the average of the signals applied to the source and drain terminals. That is, a voltage Vg is applied to the gate terminal as defined by Vg = Vdc + 2(V1 + V2) However, this simple arrangement ignores the non-linear variation of the drain current due to the above-mentioned body effect so that, even if the common-mode voltage were generated perfectly, the resistance between the source and drain terminals of the transistor would remain significantly non-linear due to the body effect.

When the transistor, operating in the so-called linear region, is modelled with greater complexity so as to account for the body effect, it can be shown that the signal which must be applied to the gate terminal is, in fact, a scaled up version of the common-mode signal where the scaling factor is a complicated function of the biasing potentials and process parameters such as the Fermi potential ç and, more importantly, the body effect coefficient Y. Referring to Figure 1, it is possible, on the basis of this observation, to linearize a CMOS transistor M1 so that the current 1d flowing into its drain terminal and out of its source terminal varies linearly with the difference between the drain voltage and the source voltage, represented in Figure 1 by V1 and V2 respectively.A linearizing voltage V8 is applied to the gate terminal by providing a common-mode voltage generator 10 with inputs 11, 12 connected respectively to the drain and source terminals of the transistor M1 to produce at an output 13 a voltage Vav equal to (V1 + V2)/2. Coupled to the output 13 of the common-mode voltage generator 10 is a modifying device 14 which is arranged to offset and scale the average voltage Vav to produce a gate voltage Vg which may be expressed in the form Vg = a + bv g where the coefficients a and b are dependent on process and biasing parameters.

In effect, the modifying element 14 is coupled in series between the output 13 of the common-mode voltage generator and the gate terminal of the transistor Ml.

The common-mode voltage generator 10 may be formed as two pairs of CMOS transistors M2, M3 and M4, M5, the transistors of each pair having their source terminals connected together and to respective current sinks 16, 18.

The gate terminals of one transistor of each of the transistor pairs, i.e. the gate terminals of transistors M2 and MS, are connected respectively to the drain and source terminals of the resistor-simulating transistor M1, while the gate terminals of the other two transistors M3 and M4 are connected together and to the drain terminals of those transistors M3 and M4 to form the output 13 of the commonmode voltage generator bearing the average voltage Vav The drain terminals of the other two transistors M2, M5 are coupled to a positive supply rail VDD. This arrangement for generating a common-mode voltage is based on an arrangement disclosed by R.R. Torrance, T.R. Viswanathan & J.V. Hanson in "CMOS voltage to current transducers", IEEE trans. Cir.

& Sys., Vol. CAS-32, No. 11, Nov. 1985.

Referring still to Figure 2, the modifying element 14 is here constituted by a further transistor M6 which is a diode-connected transistor insofar as its gate terminal is connected to its drain terminal. The source terminal of the transistor M6 is coupled to the output 13 of the common-mode voltage generator 10.With the transistor M6 so connected, it operates in its saturation region, and it can be shown that, by forcing the drain current to be equal to the magnitude of the currents drawn by current sinks 16, 18 using a third current source 20 coupled to the drain terminal of transistor M6, the drain voltage is an offset and scaled up representation of the source voltage, the scaling factor being dependent on the source-bulk potential in such a way that when used as the gate voltage V5 of the resistor-simulating transistor M1, the non-linearity of the drain-to-source resistance characteristic of transistor M1 due to body effect can be suppressed.It will be appreciated that the connection of the transistor M6 in series between the current source 20 and the output 13 of the common-mode voltage generator 10 forces the output current at output 13 to be that of the current source 20.

In this example, all six transistors M1 to M6 are n-channel devices with their bulk terminals connected to the negative supply Vs6.

The current sinks 16, 18, and source 20 can be realised in a number of ways. One particularly convenient way makes use of five CMOS transistors, as shown in Figure 3. An nchannel transistor M7 is biased by a control potential w such that it sinks a drain current I. This potential Vc also biases identical transistors M8 and M9 which sink identical currents I. A p-channel diode-connected transistor M10 is also forced to carry a current I and assumes a source-gate potential to suit. This potential biases another p-channel transistor M11 which, therefore, sources an identical current I. In this way, three constant current elements are provided for use as sinks 16, 18, and source 20 in the circuit of Figure 2. The control voltage Va provides a convenient means of dynamically varying the value I and thus the simulated resistance between the drain and source terminals of transistor M1 (Figure 2) offering the possibility not only of adjustment between different values, but also of modulating the resistance and hence signals passing through it.

An analysis of the operation of the circuit of Figure 2 now follows.

As already stated, the average voltage Vsv at the output 13 of the common-mode voltage generator is (V1 + V2)/2.

Coupled to the output 13 of the common-mode voltage generator is the diode connector transistor M6. For a transistor in saturation, the drain current is given by the well known equation: 1d6 = - V56 - Vth)2 2(Vg6 where - kzC0xW6 L6 i.e. a constant formed by the product of the transconductance parameter and the aspect ratio, and where Vg6 is the gate potential, V36 is the source potential, and Vth is the threshold potential, given by:

rp being the Fermi potential, y the body-effect coefficient, and Vb the bulk potential, and VTo the zero-bias threshold voltage, i.e. the threshold when Vs = Vb.

It will be seen that the threshold potential Vth is a function of the source-bulk potential V36 - Vb. If the second square-rooted term is expanded in a power series, the following relationship for the threshold potential is obtained:

The higher order terms which are not shown in the above relationship can be ignored. If the first three terms, which are constants providing Vb is maintained constant, are written as VT, then substituting the expanded expression for Vth in the above equation for Id6 gives:

Solving this equation for V5 gives:

Now consider the transistor M1 in Figure 2 which is required to simulate a resistor.Providing it is biased into its so-called linear region, its drain current is given by the relationship:

where 1d is the drain current, V5, Vd, and V, are the gate, drain, and source voltages, and ss1 is, as explained above for transistor M6, a constant arising from the combination of the transconductance parameter and the aspect ratio of transistor M1. This expression for 1d is clearly a highly non-linear function of the various potentials.If the 3/2 power terms are expanded as a power series, the current through the transistor can be expressed in the alternative well-known form: 1d = al ( Vd v, Vs) + a2(Vd2 - V52) + a(V3 - V53) + where the coefficient ai are functions of the remaining potentials and process parameters, etc.. Fortunately, the cubic and higher order terms are insignificant compared to the linear and quadratic terms, and for practical purposes 1d can be simplified as the quadratic form:

The three bracketed terms following Vg have already been simplified above as VT. These terms depend only on process parameters and the bulk potential Vb and if that potential is fixed they can be regarded as a constant. A key factor in the above expression for It is the term which multiplies the quadratic terms.No previous linearization scheme has successfully accounted for this y-dependent component.

It is a simple matter to express a quadratic term as the product of the sum and difference of V, and V3 and rearrange the result as:

Now, it will be seen from Figure 2, that the drain current of the diode-connected transistor M6 is fixed by current source 20 at I, and that the gate voltage Vg6 of transistor M6 equals the gate voltage V5 of transistor M1 due to the connection between the two transistors M1, M6. It will also be seen that the source voltage V36 of transistor M6 is the average voltage Vav obtained at the output 13 of the common-mode voltage generator 10 which, in turn, equals (V1 + V2)/2. In addition, the drain and source voltages V, and V3 for transistor M1 are V1 and V2.

It follows that substituting for V5 in equation (2) above with the expression for Vg6 represented by equation (1) above results in the following simple and linear expression for Id:

Thus, the resistance R between the drain and source terminals of transistor M1 may be expressed as:

It will be recognised from equation (1) that with the bulk potential Vb on both transistors fixed at the same voltage Vss and with the source potential of the diode-connected transistor M6 made to vary as the average voltage Vav, the gate voltage V5 on the resistor-simulating transistor M1 is forced to contain a d.c. component plus a scaled commonmode term.The term

in equation (1) is the d.c. potential which is used to bias the controlled transistor M1 into its conduction region and to adjust the resistance which appears between its drain and source terminals. Since V36 in equation (1) is the common-mode or average voltage Vav, it will be seen that the last term in that equation represents the scaled commonmode voltage.

It will be now recognised that the circuit arrangement of Figure 2 has allowed the full suppression of the quadratic distortion terms associated with the body effect. The nominal resistance value can be set by adjusting either or both ssl and ss6 at the design stage. In addition, the resistance can be electronically adjusted by modulating a single independent bias potential (the control voltage V, in Figure 3) which controls the output current I from the three d.c. constant current elements 16, 18, and 20.

Since it is a single device which is being linearized, the mismatch errors associated with the multiple devices used in the prior art are eliminated.

In addition, the simulated resistor is fully floating and can be used as a "drop in" replacement wherever a linear device is required. For example, such resistors can be used in active filters as the frequency selective elements or in precision feedback amplifiers to define the feedback signal.

Since the individual device is linearized, such simulated resistors can be used to construct low distortion circuits which are single ended, thereby avoiding the cost and complexity associated with having to use balanced structures as a means for reducing even-order distortion.

Since all six transistors M1 to M6 of the circuit arrangement of Figure 2 are n-channel devices with their bulk terminals connected to the negative supply (Vss) they can all be fabricated in a common well.

It is possible to implement the invention using p-channel devices for the transistor M1 to M6, as shown in Figure 4.

This is of particular use when a higher resistance is needed, the mobility of holes in the transistor channel being generally less than that of electrons. In Figure 4, the same reference numerals have been used as in the Figure 2 diagram of the n-channel embodiment. It will be appreciated that in Figure 4 elements 16 and 18 are constant current sources while element 20 is a constant current sink.

Claims (9)

1. A CMOS integrated circuit including a circuit arrangement which acts as a resistance and which comprises: a transistor having drain, source, gate and bulk terminals; a common-mode voltage generator for generating the average of the voltage on the drain terminal and the voltage on the source terminal; and means for modifying the average voltage and applying the resultant voltage to the gate terminal of the transistor whereby the transistor acts as a substantially linear resistance between its drain and source terminals.

2. An integrated circuit according to claim 1, wherein the resultant voltage applied to the gate terminal is related to the average voltage by the expression V = a + bEav where V is the resultant voltage, Vav is the average voltage, a is a constant, and b is a multiplying factor dependent on a substrate voltage.

3. An integrated circuit according to claim 1 or claim 2, wherein the modifying means comprises a diode connected transistor coupled to pass a preset constant drain current.

4. A CMOS integrated circuit including a circuit arrangement which acts as a resistance and which comprises: a first transistor having drain, source, gate and bulk terminals; a common-mode voltage generator having inputs associated respectively with the drain and source terminals of the first transistor for generating at an output of the generator a voltage which is the average of the voltage on the drain terminal and the voltage on the source terminal; and a second transistor having a source terminal connected to the output of the common-mode voltage generator, and drain and gate terminals which are coupled to the gate terminal of the first transistor; whereby the first transistor acts as a substantially linear resistance between its drain and source terminals.

5. An integrated circuit according to claim 4, including a constant current element coupled to the second transistor for setting the drain current thereof.

6. An integrated circuit according to claim 4 or claim 5, wherein the common mode generator comprises two pairs of transistors, and a pair of constant current elements, each such constant current element being coupled to source terminals of the transistors of a respective pair, and wherein the gate terminal of one transistor of each pair of transistors is coupled to a respective one of the drain and source terminals of the first transistor, the gate terminals of the other transistors of the pair of transistors are coupled together and to the drain terminals of the said other transistors and form the output of the common-mode generator, and the drain terminal of the said one transistor of each pair is coupled to a voltage supply.

7. An integrated circuit according to claim 5 or claim 6, wherein the current element coupled to the said second transistor and the constant current elements forming part of the common-mode voltage generator are arranged to generate currents of the same magnitude.

8. An integrated circuit according to any preceding claim, wherein the first and second transistors are n channel devices.

9. A CMOS integrated circuit constructed and arranged substantially as herein described and shown in the drawings.