GB2269010A - Photon counting APD with active quench and reset - Google Patents

Abstract

APD 1 is biased to respond to single photons. Avalanche current is detected by load 15 and latchable comparator 2, which quenches the APD 1 using transistor 5 then recharges the APD 1 after a delay 8 using transistor 6. MOSFET 3 is normally on, but switches off during quench to reduce comparator overload and APD node capacitance. <IMAGE>

Description

IMPROVEMENTS IN OR RELATING TO PHOTON COUNTERS This invention relates to photon detectors or counters and more especially it relates to apparatus for counting individual photons arriving at a detector. Such photon counting is required for a large number of measurement techniques including spectroscopy and laser doppler velocimetry.

Photon counting measurements were originally and to some extent still are carried out using photomultiplier tubers. Although photomultiplier tubes afford good performance, they are expensive, bulky, fragile and require high operating voltages. Present developments in photon counting involve the use of avalanche photodiodes (APDs) operated in a Geiger avalanche mode. APDs have the advantage of being sensitive over a relatively large band-width of being small and rugged, of requiring lower bias voltages than photomultiplier tubes and of being cheaper.

In the Geiger mode, the bias voltage applied to an APD is chosen so that if a photo-electron (or dark current electron) is created, the electron avalanche created is largely self-sustaining although it will stop eventually due to slow thermal effects.

Typically, bias voltages of between 200 and 250 volts are required depending on the APD temperature. The avalanche is easily detected and since it only takes a single photo-electron to generate it, the detection of a single photon is facilitated.

Once the avalanche has been detected it must be stopped since .. . . . . ..

no further photons can be detected until this takes place. This process is known as quenching. It can be carried out by placing a large resistor, in the order of 200k ohm in series with the APD. Thus as the avalanche current builds up, the voltage across the resistor increases and conversely the voltage across the diode reduces. The voltage across the diode will fall close to or below a threshold voltage required for a self sustaining avalanche and accordingly when this point is reached the current will stop. Before the diode can detect another photon its internal capacitance must be recharged. This is done through the series resistor and this sets a limit to the reset time of the detector. For currently available diodes the reset time is about 0.5 micro secs. This in turn sets a limit to the maximum count rate possible.This basic photon counting technique is known as passive quenching.

To give greater reset speed, a faster reset technique has been developed which is known as active quenching. Active quenching involves the use of a smaller series resistor to reduce the charging time and a typical value would be about 1k ohm. As this value of resistance will not quench an avalanche once the avalanche has been initiated, external circuitry must be used to reduce the bias voltage below the threshold voltage.

An example of an active quenching circuit is disclosed in the specification accompanying patent application PCTIGB 87100837.

This circuit is a considerable improvement on previously known photon counters and in particular it avoids the use of active photodiode resets, has a well defined dead time and a substantially constant output pulse-width. It does however have the disadvantage that it tends to be temperature sensitive, it has a significant recharge time and affords little possibility for optimising circuit operation as will hereinafter be explained.

It is an object of this invention to provide a photon detector circuit in which the aforementioned disadvantages are obviated at least in part.

According to the present invention a photon detector circuit comprises an avalanche photodiode (APD), a reference voltage source, a comparator responsive to the difference between the APD voltage and that of the source for avalanche detection purposes, a quench transistor responsive to the comparator for quenching the APD after an avalanche event, a recharge transistor via which the APD is recharged after each event, and a logic circuit responsive to the comparator for providing an output signal indicative of the occurrence of an avalanche event and for controlling operation of the quench transistor and the recharge transistor.

Preferably the APD is coupled to the comparator via an isolator switch which is controlled by the logic circuit so as to isolate the APD from the comparator when the APD is quenched.

The isolator switch may be coupled to the logic circuit. via a driver amplifier.

The recharge transistor may be coupled to the logic circuit via a delay device.

The voltage source may be controllable whereby control of comparator operation is facilitated.

The logic circuit may comprise an AND/NAND gate and the delay device may be coupled to the recharge transistor via an inverter.

An embodiment of the invention will now be described by way of example only with reference to the accompanying drawing, in which; Figure 1 is a circuit diagram of a photon counter and, Figure 2 is a waveform diagram showing waveforms which relate to the circuit of Figure 1.

Referring now to Figure 1 a photon detector circuit comprises an APD 1, a comparator 2 which is used as an avalanche detector, a MOSFET isolation switch 3 operatively associated with a drive transistor 4, a quench transistor 5, a recharge transistor 6 and some drive logic which is defined by an AND/NAND gate 7 a delay device 8 and an inverter 9. A typical timing/waveform diagram pertaining to the circuit of Figure 1 is shown in Figure 2 wherein the waveforms which obtain at points N1 to N7 as shown in Figure 1 are illustrated in Figure 2. For the purpose of explanation operation of the circuit will now be considered as it relates to an avalanche event the event being divided into six time intervals to to t6 as shown in Figure 2.

Before the time to it may be assumed that the circuit is ready and waiting for a photon avalanche event to occur. In this state the MOSFET switch 3 is 'on', its associated drive transistor 4 is 'off, and both the quench transistor 5 and the recharge transistor 6 are 'off.

The APD 1 is biased by means of a regulated 240 volt dc HT supply 10 so that it is just above its breakdown voltage. Thus negligible current flows through the APD 1 whereby the voltages at the points N1 and N2 are 0 volts. An inverting input on a line 1 lea to the comparator 2 is set to a relatively small reference voltage (VREF) above 0 volts (typically 30mv) by means of a variable potentiometer resistor 12 which is connected at one end to a 5 volt supply 13, whereby an output line 14 from the comparator 2 to the AND/NAND gate 7 (point N3), is set 'low'.

At the time to, the APD 1 receives a photon which initiates an avalanche event, this causes current to flow though the APD 1 via the MOSFET switch 3 and a resistor 15 raising the voltages at the points N2 and N1.

At the time tl, the voltage at the point N2 has reached the reference voltage on the line 1 la (VREF) so that the comparator output on a line 14 (point N3) changes state. As shown in the waveform diagram of Figure 2 this occurs at the time t2 after a short delay. This change in state triggers a change in the AND/NAND gate 7 on output lines 16 and 17, which corresponded to points N5 and N4, respectively, after a gate propagation delay at the time t3.

Typically the times t2 to tl and t3 to t2 are each of the order of 1.5 micro secs.

At the time t3 as shown in Figure 2, the MOSFET isolator switch 3 is switched 'off' as the point N4 goes 'high', thus isolating the noninverting input of the comparator 2 (line llb) from the APD 1. This is necessary to protect the comparator 2 from being overloaded while the APD 1 is quenched. It also serves to speed-up the quenching process by isolating the capacitances associated with the comparator 2 and with a protection diode 18 which is arranged to shunt the resistor 15, from the APD 1 during quenching. As the signal on the line 16 (point N5) goes 'low' the quench transistor 5, which is coupled to the line 16 by the parallel combination of a diode 19 and a capacitor 20, is constrained to switch 'on'. This raises the voltage at the point N1 to 10 volts reducing the voltage across the APD 1 to below breakdown and stopping the avalanche. It can seen from Figure 1 that the line 16 is coupled to the comparator 2 at its latch enable input 21 which serves to latch the output of the comparator in the 'high' state thereby preventing the signal at the point N3 from changing before the time t5 as shown in Figure 2. Additionally, the signal on the line 16 is fed to the delay device 8 which may comprise a delay line or a multiple gate propagation delay arrangement.

At the time t4, after a delay occasioned by the delay device 8, a change of logic level at the point N5 is produced as shown in Figure 2, on an output line 22 of the delay device 9 (point N6). Since the signal at the point N6 is now low, the outputs of the AND/NAND gate 7 revert back to their original states, after the gate propagation delay, at the time ts. This causes the quench transistor 5 to switch 'off and switches the MOSFET isolator switch 3 'on'. The signal at the point N6 is also fed via a the inverter 9 and line 23 to drive the recharge transistor 6. The action of the recharge transistor 6 is to short out the resistor 15 thereby to provide a low series impedance for the APD 1 to recharge. The diode 18 and a further protection diode 24 serve to protect the comparator while the APD 1 recharges.

The diode 18 prevents the voltage at the point N2 from exceeding +0.4 of a volt and the diode 24 prevents the voltage at the point N1 from going below -0.4 of a volt. The diodes 18 and 24 are typically high speed Schottky diodes with low forward voltage drops and low capacities.

While the voltage at the point N6 is 'low', any re-triggering of the circuit is prevented and hence a well defined dead time is provided. After the delay afforded by the delay device 8 (delay T) the voltage at the point N6 reverts to its original 'high' state, rearming the circuit and switching 'off' the recharge transistor 6. The voltage at the point N1 is no longer held at -0.4 of a volt and drifts back to 0 voltage via the resistor 15.The voltage at N2 takes a signficant time to return 0 volts, while the capacitances of the transistors 5 and 6, the MOSFET switch 3, the diodes 18 and 24 and the APD 1 are charged through the resistor 15, and any photon event occurring after the time t6 as shown in Figure 2, will rapidly force the voltage at the point N1 above VREF with only a small time of arrival delay.

If a photon arrives during the period ts to t6, it will cause the circuit to be re-triggered at the time t6. Hence, although there will be a time of arrival error (of maximum value T) the circuit will detect the new photon. If the rate of photon arrival is such that the circuit saturates then the output will be a continuous square wave of period t6 to t2. In the circuit implementation used, the outputs from the comparator 2 to the AND/NAND gate 7 and the inverter 9 are arranged to be emitter coupled logic (ECL) compatible. To switch the transistors 5 and 4, the zener diode 19 and a further zener diode 25 respectively are used to level shift the ECL levels, with the capacitor 20 and a further capacitor 26 being used for decoupling purposes to reduce zener diode noise.

Using discrete logic to drive the individual sections of the circuit enables the circuit to be modified whereby performance can be optimised. Possible options include the implementation of different quench and recharge times to optimise circuit performance.

Another option is to turn the MOSFET switch 3 on between the times ts and t6 enabling the removal of the diode 18. Both of these options could be implemented with changes to the logic control arrangement as will be appreciated by those skilled in the art.

The circuit just before described has the advantage that it uses active photodiode resets and has a well defined dead time with a constant output pulse-width, but moreover however it affords the following advantages: (i) It uses active switching to isolate the inputs of the comparator during quenching to prevent the inputs being overloaded. This active switching technique has a particularly low temperature sensitivity which is an improvement over prior art arrangements.

(ii) It uses an active load to recharge the APD instead of using a fixed resistor. This greatly reduces the APD charge time reducing the circuit dead time it also enables different quench and recharge times to be used.

(iii) The comparator is used as a threshold detector and separate logic is used to drive the isolation, the quench, and the recharge devices. This enables considerably more flexibility in optimising the circuit operation than has hitherto been available and for example separate quench and recharge times may be used by the expedient of a simple logic circuit change.

Claims (7)

CLAIMS:

1. A photon detector circuit comprising an avalanche photodiode (APD), a reference voltage source, a comparator responsive to the difference between the APD voltage and that of the source for avalanche detection purposes, a quench transistor responsive to the comparator for quenching the APD after an avalanche event, a recharge transistor via which the APD is recharged after each event, and a logic circuit responsive to the comparator for providing an output signal indicative of the occurrence of an avalanche event and for controlling operation of the quench transistor and the recharge transistor.

2. A circuit as claimed 1 wherein the APD is coupled to the comparator via an isolator switch which is controlled by the logic circuit so as to isolate the APD from the comparator when the APD is quenched.

3. A circuit as claimed in claim 2 wherein the isolator switch is coupled to the logic circuit via a driver amplifier.

4. A circuit as claimed in claim 3 wherein the recharge transistor is coupled to the logic circuit via a delay device.

5. A circuit as claimed in claim 4 wherein the voltage source is controllable whereby control of comparator operation is facilitated.

6. A circuit as claimed in claim 5 wherein the logic circuit comprises an AND/NAND gate and the delay device is coupled to the recharge transistor via an inverter.

7. A photon detector circuit substantially as hereinbefore described with reference to the accompanying drawings.