GB2268604A

GB2268604A - Integer divider.

Info

Publication number: GB2268604A
Application number: GB9214179A
Authority: GB
Inventors: Avi Sarusi; Daniel Shterman; Yoav Talgam
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1992-07-02
Filing date: 1992-07-02
Publication date: 1994-01-12
Also published as: GB9214179D0

Abstract

The integer divider (20) comprises means (22) for determining the first bit of the divisor which has a value 1 and for providing an output signal P representative of the position of the first bit, means (24) for normalising the divisor in dependence on the signal p and means (26) for performing an iterative division operation for the bits of the dividend and normalised divisor. The integer divider further comprises control means (28, 30) coupled to receive the output signal p and to control the number of iterations performed by the division operation in dependence on the signal p. The control means generates a stop signal just before a fraction bit of the result is generated whereby the integer divider provides the integer result. <IMAGE>

Description

Integer Divider Field of the Invention This invention relates to integer dividers.

Background of the Invention Integer divide operations require a fixed number of clock cycles for completion. Typically, 32 bit operands may require between 20 to 40 cycles which can cause significant disruption in the processing of instructions in a microprocessor.

In high performance processors, such disruptions are cared for by assigning other executions to special concurrent execution units.

Such a solution, however, is extremely inefficient since there is normally not enough processing work to be done before the divide results are needed. Furthermore, in concurrent processors with precise exception, there may not be sufficient time to hold the information during the long divide operation whereby all the instructions are executed before the divide operation is complete.

There is therefore a significant need to provide a mechanism which shortens the average latency of the divide operation.

Summary of the Invention In accordance with the present invention there is provided an integer divider for performing an integer divide operation on a dividend having m bits by a divisor having n bits to provide an integer result, the divider comprising: means for determining the first bit of the divisor which has a value 1 and for providing an output signal representative of the position p of the determined first bit; means for normalising the divisor in dependence on the output signal p; and means for performing an iterative division operation for the bits of the dividend and normalised divisor, the integer divider being characterised by: control means coupled to receive the output signal p and to the means for performing for controlling the number of iterations performed by the division operation in dependence on the output signal p, the control means generating a stop iteration signal just before a fraction bit of the result is generated whereby the integer divider provides the integer result.

An advantage of this arrangement is that the number of cycles required for an integer operation is reduced compared to the known integer dividers since the invention avoids the need to perform all m iterations and to then discard the fractional part of the result.

In a preferred arrangement, the control means generates the stop iteration signal after m-p bits of the result are generated.

Preferably, the control means comprises a shift-left register having a control input coupled to receive the output signal p, a first input coupled to the means for performing to receive sequentially each bit resulting from each iteration of the division operation, a control output for providing the stop iteration signal to the means for performing after m-p iterations and a first output for providing the integer result. This arrangement avoids the need of using a right-barrel shifter after the iterations are completed.

Brief Description of the Drawings An integer divider in accordance with the present invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 shows a block schematic diagram of a prior art integer divider; and Figure 2 shows a block schematic diagram of a first integer divider in accordance with the present invention.

Detailed Description of a Preferred Embodiment Referring firstly to Figure 1, a known integer divider 2 comprises a find-first-set logic 4, a barrel shifter 6, a counter 8 with associated control logic 10, a division unit 14 and a results barrel shifter 12. The integer divider 2 divides a 32 bit dividend by a devisor and uses a 32 bit counter 8 to count the 32 iterations. For a 64 bit dividend a 64 bit counter is required. The counter therefore fixes the number of iterations performed by the division unit 14.

At the start of a divide operation, the divisor is normalised (left shifted) using the find-first-set logic 4 and barrel shifter 6. An indication of the number of shifts to the left required for normalisation is passed to the results barrel shifter 12. The 32 iterations are then performed using the normalised divisor in the division unit 14 under the control of the counter 8. The result from the division unit 14 comprises an integer part and a fraction part which are then passed to the results barrel shifter 12. Finally, the result is right-shifted by the results barrel shifter 12 for alignment according to the number of normalisation shifts and so as to discard the unwanted fraction bits. The output of the results barrel shifter 12 provides the integer result.

Since the integer divider performs a fixed number of iterations according to the size of the dividend, it has a fixed latency which may cause the disruption problems as described in the introduction.

Referring now to Figure 2, a first integer divider 20 in accordance with a preferred embodiment of the invention comprises a find-first-set logic 22, a barrel shifter 24, a division unit 26 and a shift-left register 28 with associated control logic 30.

The operation of the preferred embodiment will be described with respect to a 32 bit dividend so that, dividend < 232 and, 2P < divisor < 2P+1, (for a non-zero divisor) where p is the highest power in the divisor (0 < p i 31).

Therefore, dividend < d dividend 232 quotient = divisor 2P 2 2p Alternatively, quotient I So that,

where qi = 0 or 1, and p is determined from the divisor.

One q bit of the quotient is determined in each iteration performed by the division unit 26. Thus, only (32-p) iterations are required to determine the integer part of the result. In fact for the iteration (32-p+l), the first bit after the decimal point is generated: that is the beginning of the fraction part is generated.

Normalisation of the divisor is carried out by the find-first-set logic 22 and barrel shifter 24 in known manner: the bits of the divisor are left-shifted 31-p steps so that the MSB of the divisor is a '1'. The bit in position p of the shift-left register 28 is set. The division iterations are then performed using the normalised divisor in the division unit 26 until the shift-left register asserts a serialout signal (SO) via the optional control logic 30. The serial-out signal SO is connected to bit position 31 of the shift-left register 28. When bit 31 is a ' 1 ', it signifies that one more iteration is required. The control logic 30, which may be for example a D-type flip-flop, samples the SO signal (i.e. bit 31) and on sampling a 1' generates the stop iterations signal on the next cycle.

Thus, the serial-out signal is generated after (32-p) iterations so that the iterations stop exactly before the first fraction bit is formed. On each iteration the resulting bit is shifted into the LSB position of the shift-left register 28. This is repeated (32-p) shift cycles. On completion of the 32-p iterations the output of the shiftleft register provides the integer result.

The present invention therefore performs an integer divide operation for a 32 bit dividend after (32-p) iterations only, instead of completing 32 iterations and discarding the fraction part of the result as in the prior art arrangement. In this way, p iterations are saved thereby providing a significant decrease in the average latencies of the integer division instructions.

The first integer divider in accordance with the present invention also avoids the need for a final normalisation step. Hence a right barrel shifter is not required to provide the integer result.

This saves chip space and a barrel shifter delay.

The invention has been described with respect to a 32 bit dividend. In the case of a 64 bit dividend and 32 bit divisor, 32 iterations must be added to the above description: that is, the division unit must perform (64-p) iterations to provide the integer result.

The invention has been described implementing a bit by bit divide algorithm (i.e. one bit per iteration). However, the invention is not limited to this type of algorithm. Other divide algorithms where two or more bits are produced in each iteration (2, 4, 8 bits per iteration) may also be implemented in the integer divider in accordance with the present invention.

It will be appreciated that other ways of accumulating the result bits may be implemented instead of using a shift-left register.

For example, a shift-right register and another register for accumulating the result could be used.

Claims

1. An integer divider for performing an integer divide operation on a dividend having m bits by a divisor having n bits to provide an integer result, the divider comprising: means for determining the first bit of the divisor which has a value 1 and for providing an output signal representative of the position p of the determined first bit; means for normalising the divisor in dependence on the output signal p; and means for performing an iterative division operation for the bits of the dividend and normalised divisor, the integer divider being characterised by: control means coupled to receive the output signal p and to the means for performing for controlling the number of iterations performed by the division operation in dependence on the output signal p, the control means generating a stop iteration signal just before a fraction bit of the result is generated whereby the integer divider provides the integer result.

2. The integer divider according to claim 1 wherein the control means generates the stop iteration signal after m-p bits of the result are generated.

3. The integer divider according to claim 2 wherein the control means comprises a shift-left register having a control input coupled to receive the output signal p, an input coupled to the means for performing to receive sequentially each bit resulting from each iteration of the division operation, a control output for providing the stop iteration signal to the means for performing after m-p iterations and an output for providing the integer result.

4. The integer divider according to claim 3 wherein the shift-left register is a m bit register and the control means further comprises a D-type flip-flop coupled to bit m of the shift-left register, the flipflop providing the stop iteration signal in response to bit m having a value 1.

5. An integer divider substantially as hereinbefore described with reference to Figure 2.