GB2268328A - Protecting capacitors in integrated circuits - Google Patents

Abstract

An integrated circuit comprises a capacitor 10 and a protective device or circuit 12 that performs the function of limiting a voltage on the capacitor, whereby the capacitor is protected from damage when exposed to an electrostatic discharge. The protective device may be a bidirectional thyristor, a diode, a series of diodes or inverse-parallel connected diodes. The capacitor may be a MOS or MIM type. <IMAGE>

Description

A CAPACITOR wrin ELECTROSTATIC DISCHARGE PROTECTION NOTICE (C) Copyright, *M* Texas Instruments Incorporated 1992. A portion of the disclosure of this patent document contains material which is subject to copyright and mask work protection. The copyright and mask work owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright and mask work rights whatsoever.

HELD OF THE INVENTION This invention generally relates to capacitors designed to withstand electrostatic discharges.

BACKGROUND OF THE INVENTION Without limiting the scope of the invention, its background is described in connection with capacitors for use in microelectronic circuits, as an example.

Heretofore in this field semiconductor devices have been known to be susceptible to the Electrostatic Discharge (ESD) phenomenon. The best known ESD events are those generated between the human body and ground where electrostatic potentials of 4kV are not uncommon. Typically, the discharge occurs within a few tens of nanoseconds and generates peak currents in the tens of amperes. This surge of highvoltage, high-current electricity represents a major threat to both active and passive electronic components. Capacitors are particularly vulnerable because they are often used as high-frequency bypass elements at the input to semiconductor devices. Such a capacitor's viability under ESD stress is as important to the functioning of the circuit as that of active semiconductor devices like transistors.Past solutions to the protection of active semiconductor devices from ESD have typically relied on Si clamping diodes, Zener diodes, and Silicon-controlled rectifiers, or thyristors. Additionally, since the SUMMARY OF THE INVENTION Past solutions to ESD protection that rely on Si devices to protect capacitors suffer from relatively slow switching speeds because of the low mobilities of carriers in Si. Consequently, an ESD event with high frequency content or a fast-rising leading edge may damage the capacitor before the ESD protection device turns on fully.

Additionally, Si is a relatively poorly insulating semiconductor when compared to a material such as GaAs. Hence, the integration of components for operation at high frequencies is difficult because of the inadequate isolation of the Si substrate. The methods of ESD protection using passive components like shunt inductors have been shown empirically to be inadequate for the protection of components with low breakdown voltages, most likely because of a higher than expected frequency content of the ESD event. For these reasons, it is herein recognized that a need exists for a capacitor circuit capable of surviving a variety of electrostatic discharge events.

Generally, and in one form of the invention, an integrated circuit comprising a capacitor and a device or circuit that performs the function of limiting a voltage on the capacitor, whereby the capacitor is protected from damage when exposed to an electrostatic discharge, is disclosed.

An advantage of the invention is that it obviates the need for an additional die carrying ESD protection circuitry to be used in conjunction with a die for a capacitor.

This provides advantages because of the cost of the additional die or# chip and the associated labor cost of mounting an additional part In addition, an integrated capacitor and ESD device improves the reliability and robustness of the circuit by saving bond wires and chip handling. Another advantage is that the structure may be easily fabricated as a part of an integrated circuit as well as on its own semiconductor die.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a schematic diagram of a first preferred embodiment of the invention; Figure 2 is a plan view of a layout of a first preferred embodiment structure; Figure 3 is a schematic diagram of a thyristor; Figure 4 is a plot of the current-voltage characteristics of a thyristor used in the first preferred embodiment structure; Figure 5 is a cross-sectional view of an epitaxial material structure used in the fabrication of the first preferred embodiment circuit; Figure 6 is a simplification of Figure 5; Figure 7 is a perspective view of the mesas used to construct the thyristor used in the first preferred embodiment circuit; Figure 8 is a perspective view of the thyristor used in the first preferred embodiment circuit; Figure 9 is a plan view of the thyristor used in the first preferred embodiment circuit;; Figure 10a-c are schematic diagrams of versions of a second, preferred embodiment of the invention; Figure 11 is a plan view of a layout of a third preferred embodiment of the invention.

Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS In a first preferred embodiment of the invention, shown as a schematic in Figure 1, a capacitor 10 is protected from an electrostatic discharge voltage spike by a thyristor 12 connected in parallel with the capacitor. A voltage spike entering the circuit's input terminal 14 is prevented from damaging the capacitor 10 and the circuitry (not shown) that is attached to the output terminal 16. The circuit is fabricated on a GaAs substrate.

A; layout of the embodiment is shown in Figure 2. The capacitor is of metal-insulatormetal (MUM) type, with the insulator being a 2000 Angstrom layer of Si3N4. The metal top 17 and bottom 18 plates of the capacitor are substantially Au or an alloy including Au, all deposited using well-known techniques. The bottom plate 18 is connected to a ground plane on the back side of the substrate on which the circuit is fabricated through via holes 19. The thyristor, a schematic of which is shown in Figure 3, is comprised of two subcircuits; one is made up of the Q1, Q2, and R2 combinations, while the other is comprised of the Q3, Q4, and R4 elements. The Q1, Q2, and R2 subcircuit protects against positive ESD voltage transients, while the Q3, Q4, and R4 sub circuit protects against negative ESD voltage transients.When combined as shown in Figure 3, they form a bi-directional (i.e. positive or negative) ESD protection device. It should be noted that an important feature of the thyristor is that its bi-directionality applies not only to its ability to protect against Electrostatic Discharge events, but that it also allows voltage swings of either polarity up to approximately +15-25 V before it reaches its turn-on voltage. A plot of the I-V characteristics of the thyristor is shown in Figure 4.

Typical MIM capacitors have breakdown voltages of approximately 200 V.

Thus, it is evident that protection from voltage spikes that can reach 4000 V in an ESD event is essential for the capacitor to remain functional. Referring again to the I-V plot of Figure 4, one can see that the thyristor clamps a voltage to no more than about 25 V, well within the operating conditions of the capacitor. The thyristor is typically arranged with one node 20, for example, in connection with an RF or DC signal line, and the other node 22 in connection with a ground line. The embodiment is especially suited for integration in monolithic integrated circuits because of its very small size (approximately 100 pom square) and the ease of forming the device from epitaxial structures used to produce devices such as Heterojunction Bipolar Transistors (HBTs), Heterojunction Field Effect Transistors (HEETs), and Metal-semiconductor Field Effect Transistors (MESFETs).

The first preferred embodiment structure utilizes a thyristor fabricated from an epitaxial material structure, shown in Figure 5, optimized for fabricating HBTs. It consists of a substrate 50 of semi-insulating GaAs of a thickness of approximately 625 pm. An n-type GaAs subcollector layer 52 doped with Si for example to a concentration of about l.5x1018 cam~3 is then deposited to a thickness of approximately 1.0 pm. The n-type collector layer 54 of GaAs, doped with Si for example to a concentration of about 8.0x1015 cam~3, is then deposited to a thickness of approximately 0.65 pm.Next, the ptype GaAs base layer 56, doped with C for example to a concentration of about 1.5x1019 cm~3 is deposited to a thickness of approximately 0.09 pm. The emitter layer 58, AlxGa1#xAs, where x=.30, doped with Si for example to a concentration of approximately 5x1017 cm-3 is deposited to a thickness of approximately 0.1 pm. In graded layer 60, the Al mole fraction is decreased from 30% at the top edge of the emitter layer 58 to 0% within a layer thickness of approximately 0.05 pm. Doping is the same as in emitter layer 58. On top of graded layer 58 is deposited buffer layer 62, comprised of GaAs and doped with Si for example to a concentration of about 4x1018 cm~3. The buffer layer 62 thickness is approximately 0.15 pm.The next layer serves as a transition between buffer layer 62 and emitter contact layer 66. In graded layer 64 the In mole fraction is graded from 0% at the top edge of buffer layer 62 to 50% over a thickness of approximately 0.04 pm Graded layer 64 is doped with Si for example to a concentration of about 1x1019 cam~3. Finally, emitter contact layer 66 of InxGa1#xAs, where x=.50, doped with Si for example to a concentration of approximately 1x1019 cm 3 is deposited to a thickness of approximately 0.04 lun. For clarity, the epitaxial material structure of Figure 5 will be represented in simplified form, as shown in Figure 6 throughout the remainder of the description of the preferred embodiment.Layers 58,60, 62, 64, and 66 are represented by a single layer 68 in Figure 6.

In order to form the circuit of the first preferred embodiment, an alternating pattern of base and emitter mesas is required, as shown in Figure 7. Figure 7 is a projection view of the thyristor used in the first preferred embodiment circuit with all metallization removed for clarity. Provision for external contact to the circuit is provided by Au bond pads 20 and 22, or contact may be made directly to signal or DC lines incorporated as a part of an integrated circuit including the first preferred embodiment circuit. Contact to the emitter and base metallization is achieved using a standard Au airbridge process. The structure, complete with airbridges and bond pads, but with emitter and base metallization not shown for clarity, is shown in Figure 8, which corresponds to the embodiment circuit schematic shown in Figure 3.

A top view of Figure 8, with element designations used in Figure 3 is shown in Figure 9 to indicate the location and distribution of transistors and resistors on the substrate. As is evident in Figure 9, the NPN transistors are formed vertically from the emitter mesa structures. These transistors incorporate the wide-band-gap emitter layer 58, and are therefore true heterojunction transistors. The PNP transistors (Q1 and Q3), however, are formed laterally between adjacent base mesas, as denoted in Figure 9. (This choice of NPN heterojunction bipolar transistors and PNP homojunction transistors was made so that the thyristor could be fabricated with an existing microwave HBT process that happened to be optimized for NPN vertical heterojunction transistors.The opposite situation of PNP heterojunction transistors and NPN homojunction transistors could be used with the appropriate epitaxial material structure) The base-emitter shunt resistors, R2 and R4, result from the intrinsic resistance of the p+ layer 56. In the preferred embodiment R2 is approximately 250 ~, while R4 is 125 ~. The values of R2 and R4 set the point at which the initial breakdown of the device occurs. Neglecting R2 and R4 would make the breakdown occur at a lower voltage than in the thyristors used in the preferred embodiment devices.

In a second preferred embodiment, the device used for protecting the capacitor is a diode 70, the directionality of which may be reversed from that shown in Figure 10a, or string of diodes designed to have a turn-on voltage high enough (15-25 V) to prevent turn-on during normal circuit functioning, but low enough to prevent the capacitor from breaking down. The number of diodes in the string 72 (Figure 10b) is chosen to achieve a certain breakdown voltage. Diodes 74 may also be arranged for bidirectional voltage spike protection as shown in Figure 10c.

In a third preferred embodiment, a bond pad 76 connected to the capacitor bottom plate 18, shown in Figure 11, is connected to ground by a bond wire rather than by a via hole as described in the first preferred embodiment (Figure 2).

In a fourth preferred embodiment, the capacitor is of metal-oxide-semiconductor (MOS) type rather than the MIM structure described in the first preferred embodiment.

The top plate of this capacitor is a metal, Au for example, the oxide is SiO2 for example, and the bottom plate is comprised of a highly doped layer of semiconductor.

A few preferred embodiments have been described in detail hereinabove. It is to be understood that the scope of the invention also comprehends embodiments different from those described, yet within the scope of the claims.

Internal and external connections can be ohmic, capacitive, direct or indirect, via intervening circuits or otherwise. Implementation is contemplated in discrete components or fully integrated circuits in silicon, gallium arsenide, or other electronic materials families, as well as in optical-based or other technology-based forms and embodiments.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense.

Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims (13)

WHAT IS CLAIMED IS:

1. An integrated circuit comprising: a capacitor; and a device or circuit that performs the function of limiting a voltage on said capacitor, whereby said capacitor is protected from damage when exposed to an electrostatic discharge.

2. The integrated circuit of Claim 1 wherein said device or circuit that performs the function of limiting a voltage on said capacitor is at least one diode.

3. An integrated circuit comprising: a capacitor; and a thyristor.

4. The integrated circuit of Claim 3 wherein said thyristor includes a heterojunction bipolar transistor.

5. The integrated circuit of Claim 4 wherein said heterojunction bipolar transistor is comprised of layers of GaAs and AlGaAs.

6. The integrated circuit of Claim 3 wherein said thyristor includes a PNP bipolar transistor that comprises two mesas made of a highly doped p-type base layer and said mesas are connected by a lightly doped n-type collector layer lying beneath and between said mesas.

7. The integrated circuit of Claim 1 or Claim 3 wherein said capacitor has a terminal connected to a ground plane through a via in a substrate on which said capacitor is fabricated.

8. The integrated circuit of Claim 1 or Claim 3 wherein said capacitor has a terminal connected to a ground point by means of a wire.

9. The integrated circuit of Claim 1 or Claim 3 or Claim 7 or Claim 8 wherein said capacitor is of metal-insulator-metal type.

10. The integrated circuit of Claim 1 or Claim 3 or Claim 7 or Claim 8 wherein said capacitor is of metal-oxide-semiconductor type.

11. The integrated circuit as claimed in any preceding claim fabricated on a GaAs substrate.

12. The integrated circuit of Claims 1-10 fabricated on a Si substrate.

13. An integrated circuit substantially as herein described with reference to the drawings.