GB2267798A

GB2267798A - Network data flow rate detecting device

Info

Publication number: GB2267798A
Application number: GB9210573A
Authority: GB
Inventors: Chung-Wang Lee
Original assignee: DATEX SYSTEM Inc
Current assignee: DATEX SYSTEM Inc
Priority date: 1992-05-18
Filing date: 1992-05-18
Publication date: 1993-12-15
Also published as: GB9210573D0

Abstract

A network data flow rate detecting device comprising a high impedance buffer for increasing an input impedance, an integrated circuit connected to said the high impedance buffer for detecting the busy or idle condition of a network system, a pro-counter for receiving busy signals from said integrated circuit, a micro processor for calculating and recording data signals from said pre-counter, a memory for storing traffic flow rate data, a display connected to said micro processor for output data display, a key-function sub-program for selecting data to be processed or displayed, and an alarm. The network data flow rate detecting device can be directly connected to the transmission line in a network system permitting a network user or a MIS manager to check the data flow rate of the network system at any node. <IMAGE>

Description

NETWORK DATA FLOW RATE DETECTING DEVICE The present invention relates to a network flow rate detecting device. More particularly, the present invention relates to a network data flow rate detecting device which can be connected to a network system to detect the data flow rate transmitted therethrough, and then disconnected therefrom at- any time without affecting the data transmission of the network system.

The data flow rate of a network system, like the traffic flow rate in a road, is an index of the activity. thereof. Under a low data flow rate condition, data can be transmitted through a network system quickly and freely On the contrary, the speed of data transmission through a network system becomes slow or may be obstructed under a high data rate condition. Therefore, precision detection of data flow rate and its control are important in network management.

According to conventional method, a HUB or Bridge may be used in monitoring the data flow rate in a network system. A HUB or Bridge is expensive to manufacture and complicated to install. Further, a hub or bridge should be fixedly installed at a fixed location, checking the data flow rate of a network system is inconvenient.

It is therefore an object of the present invention to provide a network data flow rate detecting device which is inexpensive to manufacture, easy to install and which substantially eliminates the aforesaid disadvantages.

It is another object of the present invention to provide a network data flow rate detecting device which provides high mobility, and can be conveniently connected to any segment or node of a network system or easily disconnected therefrom.

According to the present invention there is provided a network data flow rate detecting device comprising high impedance buffer means, integrated circuit means connected with the said buffer means for detecting data signals therefrom, pre-counter means connected to receive data signals from the integrated circuit means, a microprocessor connected with pre-counter means for processing the signals counted by the pre-counter means and converting it to traffic flow rate data, memory means connected with the microprocessor for storing traffic flow rate data from the microprocessor, display means for displaying data from the microprocessor, a key function sub-program means for selecting data to be processed or displayed, and alarm means for warning when data is outside defined limits.

An embodiment of the present invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a block diagram according to the present invention; Figure 2 is a circuit diagram of the preferred embodiment of the network data flow rate detecting device of the present invention; Fig. 3 is an alternate form of the circuit diagram according to the present invention; Fig. 4 illustrates the operation of the present invention through REsY interface IC; Fig. 5 illustrates the operation of the present invention through CRS interface IC; and Fig. 6 illustrates the function of bar display of the LCD display.

Referring to Fig. 1, a network data.flow rate detecting device is generally comprised of a-high impedance buffer 1, an integrated circuit 2, a pre-counter 3, a micro processor 4, a display 5, and a key function subprogram.

Referring to Fig. 2, the Fig. 2, the high impedance buffer 1 is to increase the impedance of the device so as not to affect the signal transmission quality of a network, in which U1 is a CRS interface IC having impedance improving and integrating functions. As illustrated in Fig. 4, when a network signal entered the IC through pins 27,28 (TPI,TPI) a CRS (Caries Sense) signal is produced (turned from "0" into "1") once sufficient energy has been accumulated, causing the pre-counter 3 to start counting the amount of data that have been sent to the IC. Once the network signal disappeared, the pre-counter 3 stops its counting (the CRS signal is turned from "1" into "0"). The data of the pre-counter 3 is regularly read and calculated by the microprocessor 4, and therefore the current traffic flow rate is known.

The internal program of the microprocessor 4 counts the traffic flow rate according to the full scale of ten millions bits per second. The integrated circuit 2 is to detect the activity of a network. When no data flow is detected in a network system, the integrated circuit 2 provides a output of 11011. When the network system is busy, the integrated circuit 2 gives an output of. !'l". The pre-counter 3 is consisted of a 16-bit counting IC and used to help the micro processor 4 catch a busy signal from the integrated circuit 2. The input clock signals of the pre-counter 3 are controlled by CRS or REDY. When these signals are not in work, namely, the network is at the idle mode, the pre-counter 3 stops its counting operation.When these signals are in work, the pre-counter 3 starts counting at the transmission speed of the network system (ten millions per second in CRS, or sixteen millions per second in REDY). The microprocessor 4 reads the data of the pre counter 3 once per 1/8 second, and the pre-counter 3 is reset once per second. The micro processor 4 is to calculate the data flow rate and the data transmission utilization ratio of the network system according to the signals provided by the pre-counter, by means of the operation of the pre-stored program therein. The data of the traffic flow rate thus calculated is stored in the memory therein and the time and network signals are showed through the display 5. The display 5 is a LCD display driven by the microprocessor 4 to show the time, the traffic flow rate, or other test data.The output pins of the display 5 are controlled by the pins I14,61-80 of the microprocessor 4. The key function sub-program has functions including optional settings -for network flow rate ratio or time display, network flow rate alarm switch, time alarm switch, time setting, local peak record cleaning, current setting display or recorded data display, and LCD function test.

The aforesaid network data flow rate detecting device can be connected to any node of a network system to detect its activity, so as to know if the network system has been in a busy or at the idle status. The micro processor 4 can also calculate the data transmission utilization ratio within a unit time, and show the calculation result through the display 5.

The network data flow statistic data of a network system can be provided by the micro processor 4 to a remote user through a RS-232 interface, so that an user can clearly see the local peak and the off peak of the network system.

In the present invention REDY may be used to replace CRS. The functions of the microprocessor 4 include: (a) reading the data of the pre-counter 3; (b) calculating the flow rate and showing it through the display 5; (c) showing LCD options and their adjustment; and (d) accessing important data; in which: (a) reading the data of the pre-counter 3: The data of the pre-counter 3 is read by the microprocessor through the pins 30 through 37 and the pin 25 thereof. The microprocessor 4 comprises a 8bit main counter which matches with the pre-counter 3 in detecting the traffic flow rate of a network system.

Therefore, there are total 24-bit counters on the flow rate scale in precisely calculating the traffic flow rate of the network system.

(b) calculating the flow rate and showing it through the display 5: The pins 1 through 14 and the pins 61 through 80 of the microprocessor 4 are to control the output pins of the display 5. The functions of the display 5 include: (1) bar and digital display; (2) CRS collision display; (3) network flow rate alarm setting display; (4) network flow rate alarm display; (5) local peak display; (.6) local peak time display; (7) local peak clearance time display; (8) time display; (9) alarm time display; and (10) alarm on/off display.

(c) showing tCD options and their adjustment; The pins 28,29 of SMC6232 are for selecting functions and data input. The flow rate display, or the time display and setting are executed through these pins. The pins 43,44 are the output terminals for the buzzer. When flow rate peak value surpasses the predetermined value or the alarm setting time is up, the buzzer is triggered to buzz.

(d) accessing important data: The pins 38 through 40 and the pin 43 of the microprocessor 4 control an EEPROM of 1024bits. The data stored in the EEPROM includes: the pre-determined alarm value, alarm switch status, local peak records, local peak time, local peak clearance time, alarm time, and clock time.

The key function sub-program provides seven main functions. The functions of function selection and data input are executed through the function key.

The functions of data correction and display are executed through the "+" key. The "+tri can not execute the operation of data input. The functions of the key function sub-program are outlined hereinafter.

1. Network flow rate ratio display/time display option settings.

2. Network flow rate alarm switch on/off options: (a) network flow rate alarm value integral number adjustment; (b) network flow rate alarm value decimal adjustment.

3. Time alarm on/off options: (a) alarm time integral number adjustment; (b) alarm time decimal.

adjustment.

4. Time setting: (a) setting on year; (b) setting on month; (c) setting on date; (d) setting on hour; (e) setting on minute.

5. Network flow rate record clearance.

6. Display of current settings or recorded data. This function is effective only when the "+" is executed. The flow chart is showing below:

NETWORK FLOW RATE ALARM SETTING AND FUNCTION ON/OFF DISPLAY v ALARM TIME SETTING AND FUNCTION ON/OFF DISPLAY YEAR/MONTH/DATE/ HOUR/MINUTE DISPLAY v NETWORK PEAK DATA DISPLAY RECORDING NETWORK PEAK DATA START MONTH/DATE/HOUR/MINUTE RECORDING THE YEAR/MONTH/DATE/ HOUR/MINUTE OF NETWORK PEAK DATA 7.LCD function test sub-program: When the function key and the "+"' key are simultaneously pressed, it enters the LCD function test sub-program.

v LCD FUNCTION TEST

I TURN ON THE BUZZER AND ALL LCD NODES TURN OFF THE BUZZER AND THE LCD v TRE BND As indicated, the present invention is to provide a network data flow rate detecting device which is inexpensive to manufacture, and can be detachably connected to any node in a network system for detecting its data flow rate. Because the network data flow rate detecting device of the present invention has been structurally simplified to minimize power supply consumption, the total size and weight of the device is minimized for mobility. The network data flow rate detecting device of the present invention can be made either for horizontal or vertical installation.

Claims

WE CLAIM

1. A network data flow rate detecting device comprising high impedance buffer means, integrated circuit means connected with the said buffer means for detecting data signals therefrom, pre-counter means connected to receive data signals from the integrated circuit means, a microprocessor connected with pre-counter means for processing the signals counted by the pre-counter means and converting it to traffic flow rate data, memory means connected with the microprocessor for storing traffic flow rate data from the microprocessor, display means for displaying data from the microprocessor, a key function sub-program means for selecting data to be processed or displayed, and alarm means for warning when data is outside defined limits.

2. A device as claimed in claim 1, wherein said display means comprises a LCD display having a bar display divided into 33 grades from 0-99%.

3. A device as claimed in claim 1, wherein the network flow rate display is indicated through two integral numbers and two decimal numbers.

4. A device as claimed in claim 1, wherein the integrated circuit means includes CRS interface IC.

5. A device as claimed in claim 4, wherein the CRS interface IC is replaced by a REDY interface IC.

6. A device as claimed in anyone of the preceding claims, wherein said key function sub-program means provides functions including network flow rate ration display/time display option settings, network flow rate alarm switch on/off options, time alarm on/off options, time setting, network flow rate record clearance, display of current settings or recorded data, and LCD display function test sub-program.

7. A network data flow rate detecting device comprising a high impedance buffer, an integrated circuit, a precounter, a microprocessor, an EEPROM, a LCD display, a key function sub-program, and a buzzer wherein: said integrated circuit is a CRS interface IC; said pre-counter is a 16-bit counter controlled by the signals from said CRS interface IC; said microprocessor reads the data of said pre-counter once per 1/8 second, and resets said pre-counter once per second; said LCD display provides functions including bar and digital display, CRS collision display, network flow rate alarm setting display, network flow rate alarm display, local peak display, local peak time display, local peak clearance time display, time display, alarm time display, and alarm on/off display; said EEPROM is a memory of 1024-bit; ; said key function sub-program comprises a function key for function selection and data input, and a "+" key for data display or correction.

8. A network data flow rate detecting device substantially as hereinbefore described with reference to, or as illustrated in Figures 1, 2, 4, 5 or 6; or Figures 1, 2, 4, 5 or 6 as modified by Figure 3, of the accompanying drawings.