GB2267761A - Electrically testing a sample - Google Patents

Abstract

A method of testing a sample e.g. a MOSFET (1) comprises using the tip of a probe (6) of a scanning tunnelling microscope to form a gated inversion region (23) in the sample, and analysing the conductive characteristics of the sample with the gated region formed therein, e.g. at 0.01 DEG K. <IMAGE>

Description

A Method of electrically testing a sample DESCRIPTION This invention relates to a method of testing a sample, particularly but not exclusively, utilising a scanning tunneling microscope.

Scanning tunneling microscopy has proved to be an effective technique for mapping the topography of a substrate, on an atomic scale. A probe with a sharp tip is brought close enough to the surface that, at a convenient operating voltage from a few millivolts to a few volts, a tunneling current is measurable. The tip is scanned over the surface while the current I between it at the surface is sensed. There are two main conventional modes of operation. In a first, constant current mode, a feedback network changes the height of the tip z to keep the current constant. Since the current varies exponentially with the gap between the tip and the surface, this keeps the gap nearly constant. An image consists of a map z (x, y) of tip height z versus lateral position x, y.

Alternatively in a constant height mode, the tip can be scanned across the surface of a nearly constant height and constant voltage, while the current is monitored.

In this case, the feedback network responds only rapidly enough to keep the average current constant.

Each mode has its own advantages. A full review is given in "Scanning Tunneling Microscopy" P. K. Hansma, J. Tersoff, Journal of Applies Physics 61(2) 15th January 1987. In accordance with the present invention it has been appreciated that a probe, such as the probe used in a scanning tunneling microscope can be used to investigate electric characteristics of certain test structures such as nanofabricated electrical circuits.

Broadly stated, in accordance with the invention, there is provided a method of electrically testing a sample comprising utilising the tip of the probe to form a gated region in the sample, and analysing the conductive characteristics of the sample with the gated region formed therein.

The invention also includes electrical test apparatus comprising: a chamber to receive a sample to be tested; cryogenic cooling means for cooling the chamber to a temperature less than 10K; a probe having a pointed tip; drive means for driving the probe tip relative to the sample; and means for providing electrical connection to the probe and/or the sample to permit monitoring of electrical characteristics of the sample.

In order that the invention may be more fully understood an embodiment thereof will now be described by way of illustrative example with reference to the accompanying drawings, in which: Figure 1 is a schematic elevational view in partial section of a cryogenic dilution refrigerator and includes an STM stage in its operating chamber in accordance with the invention; Figure 2 is a schematic view in partial section of the STM stage included in the chamber of Figure 1, also showing associated control circuits; and Figure 3 is a schematic sectional view of the sample and its interaction with the STM probe tip.

Referring to Figure 1, the apparatus includes cryogenic cooling means for cooling a sample under test and the probe (described in more detail hereinafter) to sub-Kelvin temperatures, typically less than 1.00K. In the described embodiment a dilution refrigerator is utilised, which operates in a conventional manner.

Coolant gases, in liquid form are fed from a supply cabinet 1 into a Dewar flask arrangement 2, typically liquid helium and liquid nitrogen. A working chamber 3 is contained within the Dewar arrangement 2. In a conventional manner, the refrigerator may include electrical coils 4 for applying magnetic fields to samples under test. The dilution refrigerator is capable of cryogenically cooling the chamber 3 to a temperature of less than 1.00K, typically to 0.010K.

In Figure 2, the arrangement within the chamber 3 is shown in more detail. A scanning tunneling microscope (sum) head is provided in a configuration that will fit into the working chamber 3. The head consists of a probe 5, typically formed of tungsten wire, with a sharpened tip 6. A sample 7 under test is shown schematically and typically may comprise a MOSFET as will be described in more detail hereinafter. However, it is to be appreciated that the invention is not limited to solely testing MOSFETs as will become evident hereinafter.

The probe 5 is kept at a constant height above the surface of the sample 7 by means of a piezoelectric actuator 8. Also, the probe 5 is scanned across the surface of the sample 7 in an (x, y) raster scan by further piezoelectric elements (not shown).

Control circuitry for the STN head is shown within the dotted outline 9. The circuitry includes bias source 10 which applies a voltage bias between the sample 7 and the probe 5. The resulting tunneling current is detected by detector 11 and applied to a servo control circuit 12 which detects the variation of the detected tunneling current from a reference value in order to provide a feedback signal on line 13 to the piezo electric device 8, thereby maintaining the probe 5 at constant height. The level of feedback signal (which is an indication of probe height) is also applied to an image display device or image recorder 14, which also receives scan control signals from a scan generator 15 so that an image can be displayed on a TV raster scan.

Further details of the manner of operation of the STM can be ascertained from Hansma and Tersoff supra.

Thus, in accordance with the invention, the STN head may be cooled by means of the dilution refrigerator during operation. This permits, according to the invention, the STM probe to be used for novel analysis of nanofabricated circuit devices, which typically exhibit quantum conductivity characteristics at the low temperatures achievable with the dilution refrigerator.

Referring to Figure 3, this shows by way of example a NOSFET positioned under the STM's tip in the dilution refrigerator. The MOSFET device includes metal gates 16, 17 formed on an oxide layer 18, which induce local inversion layers 19, 20 in a silicon substrate 21. A channel region 22 is formed between the inversion layers 19, 20. In accordance with the invention, the STM tip 6 is placed in close proximity to the channel region 22. A bias voltage is applied between the substrate 21 and the tip 6 which induces a localised inversion layer 23 in the channel. The localised inversion layer 23 operates in the manner of a localised gate, which can be used to analyse operation of the device. The applied voltage can be used either to attract or repel electrons in the channel and by movement of the tip 6, the position of the gate can be moved within the channel.

From a simple one-dimensional electrostatic calculation, the radius of the electron cloud underneath the tip 6 is of the order of 5nm and so for a gap size of 200 nm, the electron cloud will be isolated from the gate electrodes 16, 17 and will exist as an independent quantum dot. Tunneling experiments can thus be performed into and out of the quantum dot 23 and as the dot can be moved around, a map of the impurity states in the channel of the device can be found. It will also be seen that the provision of the localised region 23 constitutes a method of creating a double tunnel junction, i.e. a first junction is formed between inversion layer 19 and the localised layer 23, and a second tunnel junction is formed between the regions 23 and 21.

It will be appreciated that similar techniques can be used in GaAs based heterojunctions.

The apparatus according to the invention can also be used to probe the electronic wave functions of charge carriers which are externally influenced by a series Qf gates deposited on the surface of a substrate. Examples of such structures are described in GB 9100136.2 and 9101624.6. Thus, by scanning the STM tip 6 over such a device, the spatial charge density distribution can be mapped directly. Thus, for example, an artificial charge density wave can be imaged directly using the apparatus.

The apparatus may also be used to image devices in order to perform tests on a device at various stages during its fabrication. To this end, the apparatus preferably includes a further chamber external to the dilution refrigerator, in which the STM can be operated at normal room temperature. The further chamber is also useful for routine maintenance and repair of the microscope and control electronics.

In conventional manner, the chamber 3 is normally operated in a vacuum and, referring to Figure 1, the cabinet 1 contains the conventional vacuum pump arrangement for this purpose. The pump may also be used to evacuate the further chamber.

However, it will be appreciated that the apparatus can be operated under any suitable temperatures and pressures, suitable for formation of the gated region in the sample. The appropriate pressures and termperatures will be dependent upon the materials and conductivity characteristics of the sample.

From the foregoing it will be appreciated that usually, the samples under test will have a surface that is either formed of semiconductor or an insulating oxide and typically, thin metal electrodes will cover the surface. The samples are not normally prepared under ultra-clean conditions and cannot undergo baking, which leads to the surfaces being relatively dirty. For the case of semiconductor surfaces, the STM will be able to image both gate and the underlying semiconductor, whereas for the case of the oxide covered devices, the STM would be able to image only the conducting metal electrodes. In order to position the tip correctly, a map of the metal electrodes is first made by the aforementioned conventional STN mapping technique.

Then, tip 6 can be positioned in the desired position by reference to the map.

In order to achieve rough positioning of the tip initially, it may desirable to include predetermined patterns in the device itself, which can be read during the initial STh scan of the surface.

Claims (18)

1. A method of electrically testing a sample comprising utilising the tip of the probe to form a gated region in the sample, and analysing the conductive characteristics of the sample with the gated region formed therein.

2. A method according to claim 1 wherein the sample includes at least one conductive region therein, and including analysing the conductive interaction of the gated region and the conductive region.

3. A method according to claim 1 or 2 including moving the probe over the sample and mapping an impurity concentration therein.

4. A method according to any preceding claim wherein the sample includes a spatially varying charge distribution, and including detecting said distribution with the probe.

5. A method according to claim 4 wherein said charge distribution comprises a charge density wave.

6. A method according to any preceding claim including mapping the topography of the sample with the probe.

7. A method according to any preceding claim wherein the sample comprises a nanofabricated circuit structure.

8. A method according to any preceding claim including using the tip of a STN as said probe.

9. A method according to any preceding claim wherein the probe is used to form said gated region at a temperature of less than 10K.

10. A method of testing a sample substantially as hereinbefore described with reference to the accompanying drawings.

11. Electrical test apparatus comprising: a chamber to receive a sample to be tested; cryogenic cooling means for cooling the chamber to a temperature less than 10K; a probe having a pointed tip; drive means for driving the probe tip relative to the sample; and means for providing electrical connection to the probe and/or the sample to permit monitoring of electrical characteristics of the sample.

12. Apparatus according to claim 11 wherein the probe comprises the probe of a scanning tunneling microscope.

13. Apparatus according to claim 11 or 12 wherein the cooling means is operable to cool the chamber to 0.01 K.

14. Apparatus according to any one of claims 11 to 13 wherein the drive means includes piezoelectric elements for scanning the probe over the sample.

15. Apparatus according to any one of claims 11 to 14 including a further chamber to receive the sample and the probe at room temperature.

16. Apparatus according to any preceding claim including means for evacuating the or each said chamber.

17. Apparatus according to any one of claims 11 to 16 wherein said cryogenic cooling means comprises a dilution refrigerator or a helium -3 system.

18. Electrical test apparatus substantially as hereinbefore described with reference to the accompanying drawings.