GB2267611A

GB2267611A - Phase locked loop

Info

Publication number: GB2267611A
Application number: GB9311616A
Authority: GB
Inventors: Visuri Pauli
Original assignee: Nokia Mobile Phones Ltd
Current assignee: Nokia Oyj
Priority date: 1992-06-05
Filing date: 1993-06-04
Publication date: 1993-12-08
Anticipated expiration: 2013-06-04
Also published as: GB9311616D0; FI922603A0; FI91578B; GB2267611B; FI922603A; FI91578C

Abstract

A phase-locked loop comprises a loop filter (6), the loop filter having a by-pass circuit to by-pass a resistance element, of high value, during the setting phase of the loop. The by-pass circuit comprise at least one diode (D1) and a second smaller resistance element. The filter enables the bypassing of the resistance element during set up of the loop which increases the filters cut off frequency or speeds up the setting of the loop. The smaller resistance element may itself be bypassed by a series combination of a further diode and a resistance element of smaller value. Frequency dividers under control of system processor may be included in the paths of loop reference, oscillator signals. <IMAGE>

Description

A phase-locked loop The present invention relates to a phase-locked loop.

In particular the invention related to a phase-locked loop having a loop filter.

Conflicting requirements arise when a phase-locked loop is used e.g. in frequency synthesis with a voltage controlled oscillator being frequency modulated. When a rapid setting time is desired for the loop, e.g. during the start-up phase or when changing from one channel to another, then the cut-off frequency of the loop must be as high as possible. On the other hand, the cut-off frequency should be low so that the loop does not emphasize nor attenuate the modulation, or to be more precise, the cut-off frequency should be substantially lower than the lowest modulating frequency. A low cut-off frequency provides a further advantage in that the residual modulation decreases and a higher attenuation is obtained at the phase comparison frequency.

In order to meet these conflicting requirements in a satisfactory way it is known to arrange different switching means, such as switch transistors. During the moment of channel change-over or at start-up of the loop the switching means are used to by-pass, with resistors of lower values, a resistor of a relatively high value which determines the cut-off frequency of the loop filter. One such configuration comprising a transistor switch is disclosed e.g. in the US patent 4,482,869, in which the transistors are controlled by separate control pulses.

However, said controlled switches also cause certain disadvantages. Of course they substantially increase the number of components required and the subsequent costs involved. They can also cause a momentary jump in the control voltage of the voltage controlled oscillator at the moment when the loop is connected. In radio telephones, in which a phase-locked loop of this kind is quite common, such a momentary jump in the control voltage is an inconvenience.

Another means to speed up the loop at the moment of channel change-over or at start-up is disclosed e.g. in the patent application FI-870982, the means being based on the fact that the voltage of the pulses obtained from the phase comparator is increased for a moment. This configuration also requires a plurality of extra components and a separate voltage control.

According to the invention there is provided a phase-locked loop comprising a loop-filter having a by-pass circuit to by-pass a first resistance means of high value, wherein said by-pass circuit comprises a first circuit connected in parallel with the first resistance means, the circuit comprising a first diode (D1) and a second resistance means of lower value than the first resistance means, the by-pass circuit enabling an increase in the cut off frequency of the loop filter during start up of the phase-locked loop.

According to a preferred embodiment of the invention there is provided a phase-locked loop which comprises a comparator having a first and a second input the first input being a reference frequency connection, a loop filter, and a voltage controlled oscillator, from which a feedback branch is coupled to the second input of the phase comparator, whereby the loop amplifier comprises a by-pass circuit to by-pass a first resistance means of high value, wherein said by-pass circuit comprises at least one circuit connected in parallel with the first resistance means the circuit comprising a diode and a second resistance means, of a lower value than the first resistance means.

An advantage of the present invention is the provision of a simple solution to the aforementioned problems.

The invention involves the resistor of a relatively high resistance in the loop filter being by-passed by a simple series connection comprising a diode and a resistor of a lower resistance.

The invention is based on the realization that even such a simple by-pass circuit is sufficient, because the phase comparator in front of the filter during start-up provides broad pulses, i.e. pulses which are long in time, which easily pass through the diode and the series resistor to charge the capacitor. Also when the loop is set up the phase comparator provides very short pulses, which only practically pass through the series connection of the diode and the resistor. This in turn is due to the fact that the diode itself has a low capacitance, which in combination with the resistor will prevent the passage of these short pulses.

An embodiment of the present invention will be described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows the basic configuration of the phase-locked loop in the form of a block diagram; Figure 2 shows the loop filter of the phase-locked loop realized in accordance with the invention; and Figures 3 to 5 show curves illustrating the setting time and reference frequency for each circuit.

With reference to Figure 1, three signals, a clock signal (Clk), a data signal (Ds) and an enable signal (En), are supplied to the system processor 1. A reference signal obtained from a stable crystal oscillator 2 (TXCO) is divided in the divider 3 (ReC) by a factor, R, and is supplied to the phase comparator 5. A second signal provided by the closed loop feedback branch and being at the same time the output signal (Out) of the loop, is supplied to the phase comparator 5 via the predivider 4 (PrC) which divides the frequency by a factor, N.

The signal obtained from the phase comparator is supplied via the loop filter 6 (LpF) to the voltage controlled oscillator 7 (VCO). This voltage controlled oscillator also receives a modulated signal. The function of a configuration of this kind is well known to a person skilled in the art, and we can refer e.g. to the above mentioned patent application FI-870982 and to the US patent 4,482,869.

Figure 2 shows a loop filter or the block 6 in figure 1 realized according to the invention.

Normally the cut-off frequency of this filter realized as a low-pass filter is determined by the larger resistor 100kQ and by the capacitor 22 pF. According to the invention the 100k Q resistor voltage is now by-passed by a simple series connection formed by the diode D1 and the smaller resistor 4k Q.

Further it is recommendable to add another series connection of this kind which according to the figure comprises the diode D2 and a smaller resistor 470Q and connected from the point between the first diode D1 and the 4kQ resistor to the mid-point between the components in the transverse branch, or between the 2kQ resistor and the 22 pF capacitor.

Figure 3 shows the setting times of the loop when the loop filter 6 has no diodes D1 and D2 nor their series resistors. The figure shows curve 1 reference frequency 25 kHz, setting time 3800 ms; curve 2 reference frequency 100 kHz, setting time 3200 ms.

Figures 4 and 5 show the corresponding cases when the by-pass diodes D1 and D2 in accordance with the invention are connected to the filter according to Figure 2. The figures show: Figure 4 reference frequency 25 kHz, setting time 140 milliseconds; Figure 5 reference frequency 100 kHz, setting time 80 milliseconds.

In the figures we thus see that the by-pass circuit in accordance with the invention realized with diodes provide a substantial improvement in the setting time of the loop.

No controlled switches are required, and thus we can avoid the disturbance and extra costs they involve. As noted above, the phase comparator after the setting of the loop provides very short pulses, which are not passed by the diode, whereby the filter again operates as if the by-pass circuit is not connected.

In view of the foregoing it will be clear to a person skilled in the art that modifications may be incorporated without departing from the scope of the present invention.

Claims

1. A phase-locked loop comprising a loop-filter having a by-pass circuit to by-pass a first resistance means of high value, wherein said by-pass circuit comprises a first circuit connected in parallel with the first resistance means, the circuit comprising a first diode (D1) and a second resistance means of lower value than the first resistance means, the by-pass circuit enabling an increase in the cut off frequency of the loop filter during start up of the phase-locked loop.

2. A phase locked loop as claimed in claim 1, wherein the first resistance means is located in a longitudinal branch of the loop filter and that after the first resistance means there is located a transverse branch comprising a third resistance means and a capacitor.

3. A phase-locked loop as claimed in claim 1 or wherein the by-pass circuit comprises a second circuit having a second diode (D2) and a fourth resistance means the said circuit being connected from the point between the first diode (D1) and the second resistance means in the first circuit and a point between the third resistance means and the capacitor in the transverse branch.

4. A phase-locked loop as claimed in any previous claim, wherein the first, second, third, and fourth resistance means are resistors.

5. A phase-locked loop as claimed in any previous claim, wherein the first resistance means is a 100kn resistor.

6. A phase-locked loop as claimed in any previous claim, wherein the second resistance means is a 4kD resistor.

7. A phase locked loop as claimed in any previous claim, wherein the third resistance means is a 2kQ resistor.

8. A phase-locked loop as claimed in any previous claim, wherein the fourth resistance means is a 470D resistor.

9. A phase-locked loop which comprises a comparator (5) having a first and a second input the first input being a reference frequency connection, a loop filter (6), and a voltage controlled oscillator (7) from which a feedback branch is coupled to the second input of the phase comparator (5), whereby the loop amplifier comprises a bypass circuit to by-pass a first resistance means of high value, wherein said by-pass circuit comprises at least one circuit connected in parallel with the first resistance means the circuit comprising a diode (D1) and a second resistance means, of a lower value than the first resistance means.