GB2261783A - Reducing rounding errors in a digital filter using dither - Google Patents

Abstract

In a digital filter, where quantization at various stages leads to rounding up or down, dither signals are added to input signals, so that filter output signals may be produced without losing information contained in micro signals. <IMAGE>

Description

DIGITAL FILTER This invention relates to a digital filter, and more particularly which reduces drop of information of micro signals as small as possible.

As shown in Fig. 1 of the accompanying drawings, heretofore there has been proposed as a digital filter 1 a filter having a filtering circuit 2, an internal processing circuit 3 and an output processing circuit 4 built in an LSI (large scale integrated circuit) chip, for example. In the filtering circuit 2, data input signals SIN are inputted to a primary stage shift register of stages of shift registers 11 to 18, eight stages, for example, through an input terminal 20, the data input signals SIN having been produced by sampling analog audio signals, for example, at a predetermined sampling frequency.

The shift registers 11 to 18 perform shift operations according to a clock signal having the same frequency as the sampling frequency of the data input signals SIN. Delayed outputs S1 to S8 which are obtained at output terminals of respective shift registers 11 to 18 are therefore multiplied by filter factors hl to h8 at filter factor multiplying circuits 21 to 28.

The multiplied output S11 to S18 of the filter factor multiplying circuits 21 to 28 are quantized in quantizing circuits 31 to 38, and then provided to an accumulator 39. The accumulator 39 sequentially adds quantized data S21 to S28 of the quantizing circuits 31 to 38 in addition circuits 41 to 47 thereof, and thereby an added output S31 of the addition circuit 47 is sent out as a filter output of the filtering circuit 2 to the internal processing circuit 3.

Thus, the filtering circuit 2 forms an FIR digital filter, which produces output time series data Yi by convolution of input time series data Xi-j with impulse response as expressed by

where hj (j = O to 7) indicates filter factors, N is the number of taps (in Fig. 1 N = 8).

In the conventional digital filter 1 of Fig. 1, quantized data is however limited in word length at need when practically the digital filter 1 is built in a chip of an LSI, the quantized data having been obtained by quantization processing according to a functional configuration shown in Fig. 2.

More specifically, in the filtering circuit 2 multiplication result data or product data D(Sl1 to S18) which has been obtained by multiplying the input data D(S1 to S8) with the factor data D(hl to h8) in the filter factor multipliers MLT(21 to 28) is quantized in the quantizing circuits QNT1(31 to 38), and is then added in accumulative fashion in the accumulators ACM(41 to 47).

The resulting accumulative addition result data D(S31) is quantized in a quantizing circuits QNT2 of the internal processing circuit 3, and is then sent to an internal bus INB. An output data D(OUT) which has been produced through the internal bus INB is quantized in a quantizing circuits QNT3 of the output processing circuit 4, and is then transmitted to an external hardware OHW.

Here, quantizing circuits QNTl(31 to 38), QNT2 and QNT3 conduct word length limitation processing to adapt the number of bits of the product data D(Sll to S18), the accumulative addition result data D(S31) and the output data D(OUT) to a allowable number of bits of a processing circuit of the later stage, respectively.

For example, the first quantizing circuits QNT1(31 to 38) perform an operation to produce an outcome of a number of bits larger than the allowable number of input bits of the accumulators ACM(41 to 47) so that a high accuracy data as the product data D(S11 to S18) may be obtained. Furthermore, in the quantizing circuit QNT1 word length limitation to adapt the outcome to the allowable number of input bits of the accumulators ACM(41 to 47) is carried out by conducting round-off (i.e. counting fractions of 5 and over as an unit and disregard the result) or round-down (i.e.

emission of fraction) on a predetermined number of least significant bits.

These accumulators ACM(41 to 47) perform accumulative addition operation on a great number of input signals, and as a result the number of bits of the accumulative addition result data D(S31) becomes larger than the allowable number of input bits of the internal bus INB. The second quantizing circuits QNT2 apply word length limitation to the allowable number of input bits of the internal bus INB by conducting roundoff or round-down on predetermined number of least significant bits of the accumulative addition result data D(S31).

When the number of bits of the output data D(OUT) which has been obtained through the internal bus INB becomes larger than the allowable number of bits of the external hardware OHW, the third quantizing circuits QNT3 apply word length limitation to the allowable number of bits of the external hardware OHW by conducting round-off or round-down processing on predetermined number of least significant bits of output data D(OUT).

In the case where conventional digital filters are built in an LSI in such a fashion, it is necessary to round quantized data by rounding off or down data in each of the quantizing circuits QNT1, QNT2 and QNT3 at need, and therefore there is a problem in that information of micro signals is lost due to the rounding for each quantization processing in the quantizing circuits QNT1, QNT2 and QNT3.

For example, suppose that the accumulative addition result data D(S31) of the accumulators ACM(41 to 47) is a micro sinusoidal signal having 24 bit word length as shown in Fig. 3. This sinusoidal signal is limited in word length to 20 bits to adapt to the allowable number of bits of the internal bus INB in quantization in the quantizing circuits QNT2 The quantized data D(QNT2)1 varies in rectangular wave shape with a period of the accumulative addition result data D(S31) and with a center of "0" level, as indicated by the broken line, by rounding off the quantization levels L1 and L2.

On the other hand, by performing round-down in the quantizing circuits QNT2 the quantized data D(QNT2)2 of the quantizing circuits QNT2 varies in rectangular wave offsetting the center thereof to a signal level below "O" level as shown by the solid line.

When in conventional digital filters word length limitation is made by rounding off or down data in quantizing the data, as previously described there is produced a problem in deterioration of reproductivity such that by dropping information contained in unquantized micro signals having a substantially sinusoidal shape, the waveform becomes a rectangular wave or a level shift takes place.

In view of the foregoing, an object of this invention is to provide a digital filter which is capable of fairly reducing drop of information of micro signals caused by word length limitation.

The foregoing object and other objects of the invention have been achieved by the provision of a digital filter 51 in which: in multiplying circuits 21 to 28 a delayed output S1 to S8, obtained from each stage of the shift registers 11 to 18 on the basis of data input signals D(S1 to S8), is multiplied by a filter factor hl to h8; then quantization and word length limitation are conducted in a quantizing circuit 31 to 38; and a filter output S31 is obtained by conducting accumulative addition in an accumulative addition circuit 39; dither addition circuits 61 to 68 are provided at later stages of the multiplying circuits 21 to 28; dither signals DZ1 are added to the multiplication output of the dither addition circuits 61 to 68; and the addition output S41 to S48 is provided to the quantizing circuits 31 to 38.

In quantization in quantizing circuits 31 to 38, dither signals DZ1 are added by dither addition circuits 61 to 68, and thereby micro information contained in micro signals of input signals may be left in the quantized data even if after dither signals DZ1 are quantized, round-down or round-off of a predetermined number of least significant bits is made.

The present invention is therefore is capable of realizing a digital filter which is excellent in reproductivity.

According to the present invention, dither signals are previously added in quantization of input data, and thereby micro information may not be lost also in the case where word length limitation is conducted by rounding down a predetermined number of least significant bits in quantization. The present invention is therefore capable of realizing a digital filter which is remarkably excellent in reproductivity.

The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters.

Preferred embodiments of this invention will be described with reference to the accompanying drawings: Fig. 1 is a connection diagram illustrating the conventional digital filter; Fig. 2 is a schematic flow chart showing in detail the function of each unit of Fig. 1; Fig. 3 is a signal waveform diagram for illustrating the case of the processing of quantization and rounding-down of the micro signals according to the configuration of Fig. 2; Fig. 4 is a connection diagram illustrating the digital filter according to the present invention; Fig. 5 is signal waveform diagram showing dither signals; Fig. 6 is a schematic flow diagram showing a function of each unit of Fig. 4; Fig. 7 is a signal waveform diagram illustrating the waveform of data which is obtained as a result of conducting the coding and lower bit rounding-down processing of dither signals;; Fig. 8 is a signal waveform diagram illustrating addition output which is produced by adding dither signals to micro sinusoidal signals; and Fig. 9 is a signal waveform diagram showing the result of the processing of quantization and roundingdown of the signals of Fig. 8.

Preferred embodiments of this invention will be described with reference to the accompanying drawings: In Fig. 4, in which parts corresponding to parts of Fig. 1 are allotted the same reference characters, a digital filter 51 includes a configuration having a filter processing circuit 52, an internal processing circuit 53, and an output processing circuit 54 sequentially cascade connected.

The filter processing circuit 52 has a similar configuration in which dither addition circuits 61 to 68 are inserted at output terminals of the filter factor multiplying circuits 21 to 28 of the filtering circuit 2 of Fig. 1. This enables dither data DZ1 to be added to audio input data of the filtering circuit 2.

The internal processing circuit 53 and the output processing circuit 54 are provided with dither addition circuits 71 and 72, respectively, and thereby dither data DZ2 and DZ3 are added to input data of the internal processing circuit 53 and the output processing circuit 54, respectively.

Here, as shown in Fig. 5 the dither data DZ1 to DZ3 consist of noises which have frequencies within a predetermined frequency range and predetermined amplitudes as compared to input data of dither addition circuits 61 to 68, 71 and 72, for example maximum amplitude corresponding to least significant 4 bits.

The noises furthermore randomly change in amplitude and frequency distribution.

The digital filter 51 of Fig. 4 carries out processing as shown in Fig. 6 in the filter processing circuit 52, the internal processing circuit 53 and the output processing circuit 54.

The filter processing circuit 52 multiplies 16 bit input data D(S1 to S8) by factor data D(hl to h8) in the multipliers MLT(21 to 28).

In such a manner, product data D(S11 to S18) is obtained, and in the dither addition circuits ADD1(61 to 68) 4 bit dither data DZ1 is added to this data for supplying to quantizing circuits QNT1.

Here, the quantizing circuits QNT1 provide an accumulators ACM(41 to 47) with quantized data D(QNT1) of which least significant 4 bits have been rounded down on the basis of the accumulators ACM(41 to 47) having a predetermined the number of bits of word length.

When the value of the input data D(S1 to S8) is zero (that is, there is no signal), only dither data DZ1 is supplied from the dither addition circuits ADD1(61 to 68) to the quantizing circuits QNT1. Since the dither data DZl has the maximum amplitude at least significant 4 bits as described with Fig. 5, in this event as shown in Fig. 7 in the quantizing circuits QNT1 offset takes place in rounding down least significant 4 bits, so that noises of one bit width of the least significant bit are provided to the accumulators ACM(41 to 47).

When in this state, 100 FHzl sinusoidal signals of a magnitude from the full scale to -115 FdBl are supplied as input data D(S1 to S8) as previously described with Fig. 3, at output terminals of the dither addition circuits ADD1(61 to 68) there are however obtained a waveform similar to that of the dither data DZ1 modulated by micro sinusoidal signals as shown in Fig. 8.

The quantizing circuits QNT1 round down least significant 4 bits by quantizing such a waveform, and as a result quantized data D(QNT1) illustrated in Fig.

9 is obtained.

Here, the quantized data D(QNT1) shown in Fig. 9 has a waveform such that in the case where the multiplication data D(S11 to S18) has no signal (zero data), least significant one bit noise (Fig. 7) is modulated by the micro sinusoidal wave (Fig. 3), and the quantized data is different from a data in the case where simply rounding down of the least significant 4 bits is carried out.

Comparing this waveform with the waveform of Fig.

3, the data of this waveform becomes data which varies with one bit width so that quantized data hold the quantizing level between them since the addition output data D(S41 to S48) of the dither addition circuits ADD1(61 to 68) has been added with dither data DZ1 in crossing the quantizing level. The quantized data is based on the dither data varying at one bit width.

Also in the case where quantized data of micro sinusoidal signals undergoes the quantization processing while least significant 4 bits thereof are rounded down, signal components are superposed on the micro sinusoidal signals, the signal components relatively finely varying in data level on the basis of dither signals at respective signal levels which follow variations of the micro sinusoidal signals. Therefore, the used signals are supplied to accumulators ACM(41 to 47) without losing information thereof due to the least significant 4 bits round-down processing.

The foregoing configuration is capable of filtering audio input signals with a good reproductivity, and thereby providing a digital filter further excellent in sound quality.

The quantization operation which accompanies 4 bits round-down processing on the outcome of the dither data addition circuits 71 and 72 as described about Figs. 6 to 9 is similarly conducted also on addition output data of dither addition circuits 71 and 72 of the internal processing circuit 53 and the output processing circuit 54. Also in these cases quantization processing such that word length limitation is performed by rounding down least significant 4 bits without losing micro information can be carried out.

Although in the embodiment previously described dither data having an amplitude of 4 bits at maximum is used, the number of bits may be selected at need. It is essential to set the amplitude of dither data to the number of bits to be rounded down in quantization.

In the previously described embodiment, it is stated that word length limitation is made by rounding down quantized data of a predetermined number of least significant bits in quantization. Alternatively, the present invention may be widely applied to a case where word length limitation is conducted by rounding off quantized data of a predetermined number of least significant bits.

While there has been described in connection with the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention, and it is aimed, therefore, to cover in the appended claims all such changes and modifications as fall within the true scope of the invention as defined by the claims.

Claims (8)

1. A digital filter in which in multiplying circuits a delayed output which is obtained from each stage of shift registers on the basis of data input signals, is multiplied by a filter factor, then quantization and word length limitation are conducted in a quantizing circuit, and a filter output is obtained by conducting accumulative addition in an accumulative addition circuit, wherein: first dither addition circuits are provided at later stages of said multiplying circuits; in said first dither addition circuit dither signals are added to the multiplication output of the multiplying circuits; and the addition output is provided to the quantizing circuits.

2. The digital filter according to Claim 1, wherein: second dither addition circuits are provided at later stages of said accumulative addition circuit; in said second dither addition circuits second dither signals are added to the accumulative addition output of the accumulative addition circuit; and said second dither signals are then quantized and limited in word length in second quantizing circuits for supply to a internal bus.

3. The digital filter according to Claim 2, wherein: in third dither addition circuits third dither signals are added to output data obtained from the internal bus; and said third dither signals are then subjected to quantization and word length limitation in third quantizing circuits for sending out as output data.

4. The digital filter according to claim 1, 2 or 3, wherein: said first, second and/or third dither signal consist of noises which have frequencies within a predetermined frequency range and a maximum amplitude corresponding to least significant bits of data to be processed, amplitude and frequency distribution of said noises varying randomly; and a number of bits of said word length limitation in said first, second or third quantizing circuit is selected the same value as said maximum amplitude.

5. The digital filter according to claim 4, wherein: said maximum amplitude of said first, second and/or third dither signal is selected least significant four bits of data to be processed.

6. The digital filter according to claim 4, wherein: said first, second or third quantizing circuit conducts emission of fractions on least significant predetermined bits to limit said word length.

7. The digital filter according to claim 4, wherein: said first, second or third quantizing circuit counts fractions of 5 and over as an unit and disregards the rest for least significant predetermined bits to limit said word length.

8. A digital filter constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in Figures 4 to 9 of the accompanying drawings.