GB2261293A - Surge counter - Google Patents

Abstract

A surge counter includes a plurality of surge absorbing elements (C1, C2, C3) of different impulse discharge starting voltages connected in parallel to power lines (A, A'), the elements comprising series connections of gap type discharge tubes (a1, a2, a3) and nonlinear resistors (b1, b2, b3). Light receiving elements (d1, d2, d3) detect light emitted by the tubes (a1, a2, a3) and counter circuits (e1, e2, e3) count detected signals of the light receiving elements. Surge current values are thus accurately sorted and counted. <IMAGE>

Description

SURGE COUNTER BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION The present invention relates to a surge counter provided on various supply lines such as power supply lines and communication lines. More, particularly, the invention is concerned with a surge counter for counting the number of times invading surges occur and invade into these lines.

2. DESCRIPTION OF THE RELATED ART If surges invade power supply lines for communication equipment such as telephone sets, facsimiles, telephone switching boards, modems and the like, then electronic circuits forming part of the communication equipment are damaged by a fire. Therefore, conventionally, surge absorbers are provided on input lines of the power supply line, the communication line and the like for communication equipment which are installed in a region where the surges tend to generate.

In order to protect the communication equipment from the surges securely by means of the surge absorber, specifications of the surge absorbers must be determined based on the results of a statistical investigation of the generating times and the current value of the surges around the area where the communication equipment is to be installed.

Conventionally, for example, as a surge counter for recording the number of times of invading surges, the following surge counter has been disclosed in Unexamined Published Japanese Patent Application No.59-211984. This surge counter comprises: a surge absorbing element which is connected to the line capable of being invaded by a surge and which is formed by connecting a gap type glass sealed discharge tube and a nonlinear resistor in series; a light receiving element for detecting a light emission of the discharge tube; and a counter circuit for counting the detected signals of the light receiving element. In this surge counter, the surge input circuit and the surge detecting circuit are independent so that there is no possibility for surge inputs to be detected by the detecting circuit, and besides, the advantage for the design of the detecting circuit to be done easily exists.

Surge counters for recording both the number of times that invading surges occur and the surge current value have been disclosed in, for example, Unexamined Published Japanese Patent Application No.60-9081, Unexamined Published Japanese Utility Model Application No.61-117484, and Unexamined Published Japanese Patent Application No.62193075.

The surge counter of Unexamined Published Japanese Patent Application No.60-9081 comprises, a full-wave rectifier circuit for a discharge current for an arrester connected across the earthing terminal of arrester and the earth, and a plurality of discharge current measuring counter circuits connected in parallel with each other and connected to the full-wave rectifier respectively through potential dividing resistor elements. In this counter, the discharge current of the arrester is sorted into every specified current range by plural voltage dividing resistor elements.

The surge counter of Unexamined Published Japanese Utility Model Application No.61-117484 comprises a nonlinear resistor for conducting a discharge current flowing in the arrester, one or more capacitors connected in parallel with the nonlinear resistor, a plurality of sets of linear resistors and a counter driving coil which are connected to the capacitors so that they distribute the charging energy of the capacitor. This surge counter detects a discharge current within a specified range at every current value without a driving power supply by setting resistance values of each set of linear resistors at optional different values.

Further, the surge counter of Unexamined Published Japanese Patent Application No.62-193075 comprises a discharge gap with a shunt resistor provided on the earthing side of an arrester, a photosensor for converting a discharge light from the discharging gap into a current corresponding to the quantity of the light, and a counter section for counting the operations in response to a detected current value of the photosensor. This surge counter can accurately check the operational frequency by the intensity of currents of an arrester without using complicated electric circuitry.

However, the surge counter of Unexamined Published Japanese Patent Application No.59-211984 has a disadvantage in that it only records the number of times or occurrences of the invading surges, but it does not record the surge current value.

The surge counters of Unexamined Published Japanese Patent Application No.60-9081 and Unexamined Published Japanese Utility Model Application No.61-117484 have a reliability disadvantage, even though they can record the surge current values; but, since the surge input circuit and the surge detecting circuit are electrically connected with each other, there still has been a possibility of a surge invasion of the surge detecting circuit.

The surge counter of Unexamined Published Japanese Patent Application No.62-193075, while it seems to solve the foregoing problems, has its own problem in that the light emitted from the single discharge gap is detected by the single photosensor and the surge current values are sorted with each extent of the detected currents.

Accordingly, there is a disadvantage that a highly sensitive photosensor and a complicated detecting circuit are required for accurately sorting the surge current values.

SUMMARY OF THE INVENTION An object of the invention is to provide a surge counter capable of accurately sorting surge current values with a simplified circuit construction without using a highly sensitive photosensor and capable of counting the number or occurrences of times of invading surges.

Another object of the invention is to provide a highly reliable surge counter capable of preventing invasion of surges to a surge detecting circuit.

A surge counter according to the invention, as shown in the single Figure is constructed so that a plurality of surge absorbing elements, each having different impulse discharge starting voltages, are connected in parallel with each other to surge invading lines. Surge absorbing elements are provided which are connected with gap type discharge tubes and nonlinear resistors respectively in series with each other. Light receiving elements for detecting discharge lights are provided confronting or facing the discharge tubes for detecting light discharged therefrom, and counter circuits are connected with the light receiving elements for counting signals detected by the light receiving elements.

In this disclosure, by definition, an impulse discharge starting voltage means a voltage at which a surge absorbing element starts a discharge when a pseudo surge is applied to the surge absorbing element as a specimen.

Surge current values are accurately sorted and the number of invading surges are counted using the simplified circuit constructions. There is no fear of invasion of surge invading surges to the surge detecting circuits and reliability is high.

BRIEF DESCRIPTION OF THE DRAWING The foregoing and other objects of this invention together with the advantage of the invention will become more readily apparent from the description of the preferred embodiment thereof with reference to the accompanying drawing.

The single Figure is a block diagram of a surge counter according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT A gap type discharge tube according to the invention includes an air gap type discharge tube, a gas sealed discharge tube, a micro-gap type glass sealed discharge tube or the like. A nonlinear resistor for the gap type discharge tube uses a zinc oxide varistor, a silicon carbide varistor or the like. In particular, the zinc oxide varistor which has both a large nonlinear factor and a large varistor-effect is suitable. For a light receiving element, a photoconductive element which contains a polycrystal such as CdS, CdSe, PbS etc., as a main component is utilized.

In the Figure, for simplicity of explanation only, three sets of surge absorbing elements, three sets of light receiving elements and three counter circuits are illustrated. The number of sets to be used in accordance with the teachings of the invention is not limited to three sets, but, any number of sets may be employed, depending upon the particular situation.

Surge absorbing elements cl, c2, and c3 are connected in parallel with each other to lines A and A' which may be invaded by surges and for simplicity, are referred to as surge invading lines. Each of the surge absorbing elements c1, c2, and c3 consists of a gap type glass sealed discharge tube a1, a2, and a3, respectively, and a nonlinear resistor b1, b2, and b3, respectively, in series.

While not shown, in the same manner, if a fourth surge absorbing element c4 is used, it would consist of a discharge tube a4 and a nonlinear resistor b4 connected in series, and the surge absorbing element cn would consist of a discharge tube an and a nonlinear resistor b n connected in series, etc. The nonlinear resistors b1 to b3 are provided for preventing the generation of a follow current in discharge tubes a1 to a3 because the lines A and A' are always connected to a power supply voltage. The term "follow current" means the current at power frequency that passes through a discharge path after a high-voltage surge has started the discharge.

A light receiving element d1 is provided for discharge tube a1, in light receiving relationship, therewith to receive the light discharge from discharge tube a1. When there is a detected output from the light receiving element dl, the light receiving element d1 is connected to a counter circuit e1. In a similar manner, light receiving elements d2 and d3 are provided which are respectively connected to counter circuits e2 and e3 when receiving elements d2 and d3 detect a light discharge from discharge tubes a2 and a3, respectively. The discharge tube a1 and the light receiving element d1 are placed into a dark box f1 so as to prevent interference from extraneous outer light. In the same way, dark boxes f2 and f3 are also provided.

When V1, V2, and V3 are made as impulse discharge starting voltages of the surge absorbing elements c11 c2, and c3 respectively, discharge starting voltages of the discharge tubes a1 to a3 and varistor voltages of the varistors b1 to b3 are selected to satisfy the relationship V1 < V2 < V3.

While not shown, when the impulse discharge starting voltages of V1, V2, V3 ... V are provided for the n surge absorbing elements c1, c2, C3 . . .

respectively, then the discharge starting voltages of the discharge tubes a1, a2, a3 ... an and the varistor voltages of the varistors b1, b2, b3 ... bn are selected to satisfy the relationship V1 < V2 < V3 < ... Vn.

n A difference between V2 and V1 and a difference between V3 and V2 are set as in the following manner.

Namely, when I1, 12, and I3 are made as setting current values of the surge absorbing elements c1, c2, and c3 respectively, and il, i2, and i3 are made as current values actually flowing into the surge absorbing elements c1, c2, and c3 respectively, voltage V2 is set so that the surge absorbing element c2 responds by an imposed voltage across points B1 and B1' as shown in the single Figure when the current value i1 is larger than the setting current I1. In other words, assuming that "i" represents a surge current value invaded across lines A and A', V2 is set so that if i < the thenthe surge absorbing element c2 does not respond, if i > I1, then the surge absorbing element c2 responds.

If the surge current "i" is larger than I1 (i > I1), then the surge current "i" is distributed to the surge absorbing elements c1 and c2 with the current values of i and i2, respectively. Here, V3 is set so that, if i < 12, then the surge absorbing element c3 does not respond, but if i > 12, then the surge absorbing element C3 responds.

When additional units are used if i > In-1, then the surge absorbing element cn responds. If cn is C4, then 1n-1 is 13 A principle that the surge absorbing element c3 responds in the foregoing process is due to the fact that voltage is generated across points B3 and B3, by the surge currents i1 and i2 as is the case of the element c2.

In case of "n" sets of the surge absorbing element, the light receiving element and the counter circuit are provided, impulse discharge starting voltage Vn is set relative to a setting current value 1n-l in the same way.

In operation, when the surge voltage is applied across the lines A and A' to firstly cause a response of the surge absorbing element cl having the discharge starting voltage V1 which is a minimum value among the voltages V1, V2, and V3, and the surge current i1 thus flows into the surge absorbing element cl, a voltage corresponding to a product of an impedance of the element c1 and the current value i c1 is generated between the points B1 and B1'. At this time, a light discharge from the discharge tube a1 enters the light receiving element dl to operate the counter circuit e1 by means of a signal detected from the light receiving element dl.

When the surge current value "i" which invades across the lines A and A' is smaller than the setting current value I1 (i < I1), then only the surge absorbing element c1 responds and the elements c2 and c3 do not respond, and accordingly, only the counter circuit e1 operates. If I1 < i < 12, then the surge absorbing elements c1 and c2 operate, and the element c3 does not operate. Accordingly, the counter circuits e1 and d2 operate, but d3 does not operate. Further if I2 < i, then the surge absorbing elements cl, c2, and c3 all respond, so that the counter circuits e1, e2, and e3 all operate.

Table 1 illustrates operations both of the surge current value "i" invaded across the lines A and A' and the operating station of counter circuits e1, e2, and e3. The number of times of invading surges and the current values thereof both can be recorded by the count numbers of these circuits el, e2, and e3.

Table 1 Surge Current (A) Counter Circuit to be Operated i < I1 el I1 < i < I2 el, e2 I2 # i e1, e2, e3 The surge counter according to the invention is capable of both recording the surge current values as well as counting the number of times of invading surges. In particular, if the impulse discharge starting voltages of the surge absorbing elements are set in various ways, the surge currents which range from a very small current to an extremely large current can be recorded.

Further, by arranging a plurality of surge absorbing elements, the surge current can be distributed into this plurality of surge absorbing elements, a high durability for surges can be obtained compared to the conventional single surge absorbing element.

An embodiment of the invention will hereinafter be described, however, the embodiment described hereinafter is only one example, and the invention is not limited to this embodiment.

As shown in the single Figure, the micro-gap type glass sealed discharge tube was used for the gap type discharge tubes a1 to a3, a zinc oxide varistor was used for the nonlinear resistors b1 to b3, and CdS was used for the light receiving elements d1 to d3. The light receiving elements d1 to d3 confronts or faces the discharge tubes a1 to a3, respectively.

In this embodiment, the direct-current discharge starting voltages of the discharge tubes were ones which were specified in 300 V for al, similarly 500 V for a2, and 700 V for a3. The varistor voltages of the varistors were ones which were specified in 220 V for b1, and similarly 270 V for both of b2 and b3. As a result, when the impulse discharge starting voltages of the surge absorbing elements c1, c2, and C3 were measured, the average values were V1 = 700V, V2 = 900V, and V3 = llOOV, respectively.

Therefore, when a surge voltage of 700 V or more was applied across the lines A and A', then the surge absorbing element c1 responded, and a detected signal was fed out from the light receiving element dl by the discharge light from the discharge tube a1, and the counter circuit e operated. When a current flowing across the lines A and A' reached 1000 A, a terminal voltage of the element c exceeded 900 v. Hence, the elements c1 and c2 responded, similarly the counter circuits e1 and e2 operated. When the current increased and reached a value of 2500 A, then the terminal voltage of the element c2 exceeded 1100 V, and the elements c1, c2, andc3 responded, and the counter circuits e1, e2, and e3 also operated.

When the operation of the counter circuit was checked by varying the surge current, the results shown in Table 2 were obtained. From the station of the operating counter circuit in Table 2, not only the number of times of the invading surges but also the frequency distribution of the surge currents could be recorded.

Table 2 Surge Current (A) Counter Circuit to be Operated O < i < 1000 el 1000 S i < 2500 e1, e2 2500 < i e11 e2, e3 While there has been shown and disclosed what is considered to be the preferred embodiment of the invention, various changes and modifications may be made therein without departing from the scope of the invention.

Claims (10)

WHAT IS CLAIMED IS

1. A surge counter comprising: a plurality of surge absorbing elements (cl, c2, C3) each having different impulse discharge starting voltages (V1, V2, V3) respectively, and each being connected in parallel with each other to surge invading lines (A, A'), each of said surge absorbing elements (c1, c2, c3) including a gap type discharge tube (a1, a2, a3) and a nonlinear resistor (b1, b2, b3) connected in series; a like plurality of light receiving elements (d1, d2, d3), one for each said discharge tube (a1, a2, a3) in light receiving relationship therewith for detecting light discharged therefrom; and a plurality of counter circuits (e1, e2, e3), one for each said light receiving element for counting signals detected by said light receiving elements (d1, d2, d3).

2. The surge counter as claimed in claim 1, wherein the gap type discharge tube is an air gap type discharge tube, a gas filled discharge tube or a micro-gap type glass sealed discharge tube.

3. The surge counter as claimed in claim 1, wherein the nonlinear resistors are a zinc oxide varistor.

4. The surge counter as claimed in claim 1, wherein said non-linear resistors are a silicon carbide varistor.

5. The surge counter as claimed in claim 1, wherein the light receiving element is a photoconductive element containing a polycrystal as a main component, said polycrystal being CdS, CdSe or Pbs.

6. A surge counter comprising: at least two surge absorbing means (c1, c2 ... cn) each having a different impulse starting voltage (VI, V2 Vn)connected to surge invading lines and in parallel with each other; Each of said surge absorbing means (c1, c2 ... cn) including gap type discharge tube means and non-linear resistor means (b1, b2 ... bn) connected in series with each other; light receiving means (d1, d2 ... dn) arranged in a light receiving transmitting path with said discharge tube means for receiving therefrom light transmitted thereby for detecting light signals transmitted therefrom; and counter circuit means (e1, e2 ... en) for each said light receiving means for counting the light signals detected by said respective light receiving means, and wherein the impulse starting voltages of the surge absorbing means are selected to satisfy the relationship V1C V2 V3 < ... Vn.

7. The surge counter as claimed in claim 6, wherein the gap type discharge tube means is an air gap type discharge tube, a gas filled discharge tube or a micro-gap type glass sealed discharge tube.

8. The surge counter as claimed in claim 6, wherein the nonlinear resistor means is a zinc oxide varistor.

9. The surge counter as claimed in claim 6, wherein said non-linear resistor means is a silicon carbide varistor.

10. The surge counter as claimed in claim 7, wherein the light receiving means is a photoconductive element containing a polycrystal as a main component, said polycrystal being CdS, CdSe or PbS.