GB2258545A

GB2258545A - Correlation processors

Info

Publication number: GB2258545A
Application number: GB8319209A
Authority: GB
Inventors: Christopher John Tucker
Original assignee: GEC Avionics Ltd; Marconi Avionics Ltd
Current assignee: Allard Way Holdings Ltd
Priority date: 1983-07-15
Filing date: 1983-07-15
Publication date: 1993-02-10
Anticipated expiration: 2003-07-15
Also published as: IT8567439A0; IT1236503B; DE3447929C1; NL8415003A; GB8319209D0; GB2258545B

Abstract

The correlation processor typically forms part of a system in which two large sets of data are rapidly compared with each other so as to determine the degree of similarity between them. The processor is able to handle data in two different formats, in the described example the first format consists of 6-bit digital words and the second format consists of 1-bit digital words. The processor is organised as a plurality of cells, and when data of the second format is being processed, it is recirculated through the cells six times to ensure that all data points in both sets are fully correlated with each other. The organisation of the processors enables it to respond in a versatile way to input data of different bit lengths, and to process the shorter bit lengths correspondingly more rapidly than the set having the longer bit lengths.

Description

Improveents in or Relating to Correlation Processors.

This invention relates to correlation processors and seeks to provide such a processor which is capable of handling large amounts of data at relatively high speed.

In general, the process of correlation consists of determining the degree of similarity between two or more separate sets of data or selected portions of them.

Correlation is an operation used in many signal processing systems, and one of its main uses is as a filter which optimises the detection of signals in noise. Simple processors are available which can receive, as inputs, two streams of data and can provide an indication of the short term correlation between them.

Severe practical difficulties arise in attempting to compare large amounts of data to determine the degree of similarity between them. For example, it is often required to determine the degree of similarity between two, twodimensional arrays of data which may be representative of viewed images or surface areas; a large area forming a field of view may be scanned to determine whether a portion of it corresponds with a relatively small reference area whose characteristics are already known. In this context, the process of correlation consists of comparing each possible region of the viewed scene with the reference area and determining which of all possible positions gives the best match. As a viewed scene may consist of an extremely large number of individual picture points, the amount of processing required is extremely large.If a scene is being viewed in real time the data may be changing rapidly so that any useful correlation must be carried out extremely quickly. These requirements can be very difficult to satisfy, and situations in which large quantities of data are to be rapidly correlated are not confined by any means to the foregoing example.

This invention seeks to provide an improved method of correlation, and a processor for performing the method.

According to one aspect of this invention, a method of digital data correlation includes the steps of applying reference data, and a larger amount of signal data to a plurality of correlation cells in digital blocks, each of which has a predetermined number of bits; the same reference data being applied to each cell concurrently and the signal data being applied sequentially to each cell in turn to correlate signal data with reference data; and recycling signal data having a digital format of fewer than said predetermined number of bits through said cells to correlate on subsequent cycles signal data which is not correlated on a preceding cycle.

In some systems, it is preferred to recycle signal data having a digital word format of fewer than said predetermined number of bits through said cells until all signal data has been correlated with said reference data.

The invention is particularly suitable for correlating two sets of digital data having different word lengths (i.e. different numbers of digital bits). Typically, the shorter word length comprises just a single bitr whereas the larger word length can consist of many more bits, e.g.

six bits. Data patterns represented by variable amplitudes may require as many as six bits to give a sufficiently accurate indication of absolute values, and thus require fairly complex correlation structures if large quantities of data are to be correlated rapidly with a reference block of data which is quantised to the same number of bits.

Generally, such a structure processes binary data in a very inefficient manner as its handling capacity is greatly under utilised. It is, however, expensive and inconvenient to provide separate dedicated correlators to cater for each digit word length in which data might be presented, and it is quite impracticable to programme a general purpose computer to perform such a function in a reasonable time scale, as the process of correlation often involves the handling of very large quantities of data.

The correlation processor of this invention enables the correlation rate (or time taken to correlate) to be directly traded against data word length, so that binary data consisting of single bits (i.e. l's and 0's) can be processed n times more quickly than data presented in the n-bit digital word format.

According to a second aspect of this invention, a correlation processor is provided with a structure arranged to implement the above method of correlation.

The processor is designed to handle words having a maximum predetermined bit size. In the following example the maximum word length is 6-bits and the structure is thus arranged to handle data in the form of 6-bit digital words, and binary data. For binary data, each correlation cell correlates six binary bits of signal data against six bits of reference data simultaneously.

The invention is further described by way of example with reference to the accompanying drawings in which: Figure 1 represents two data fields which are to be correlated with each other; Figure 2 shows a conventional element of a correlation processor; Figure 3 shows a correlation processor in accordance with this invention, in block diagramatic form, and Figure 4 shows part of the correlation processor in greater detail.

Correlation is a fundamental operation in many signal processing systems. One of its main uses is in the implementation of matched filters, as filters of this kind can be shown to optimise the detection of signals in noise, and as such can be used extensively in processing signals in applications such as radar, acoustics, etc. In the following example, correlation is used to achieve the recognition of a reference pattern within a larger two-dimensional array of data. The data can be binary in nature, or consist of multilevel digital words.

The correlation process involves the comparison of reference data with incoming signal data and the computation of a series of scores which describes the similarity of the reference data with that portion of the signal data which is currently being processed.

Subsequently, the highest score is used to identify that portion of the signal data which corresponds most closely with the reference data.

Referring to Figure 1, there is shown therein a relatively small reference area 1, represented by the indicated solid line block, consisting of data arranged, for the purpose of illustration and explanation, as a two-dimensional array of data. As such, it represents a known area which is stored within the correlation system. A relatively large field of signal data 2 represents information which is generated, typically by an imaging system, and stored, possibly after some pre-processing, in a form in which it can be readily accessed for correlation.

In practice, the nature of the data 2 will ehange with time, and if it represents a video signal or the like it can change rapidly. The object of the correlation process is to determine which portion of the area 2 corresponds most closely with the reference area 1. When the reference 2 has a significant size, the number of operations required to correlate it with the larger area 2 can be very large indeed. For example, if the reference area 1 consists of a two-dimensional data array of 64 x 64 points and the larger area consists of 256 x 256 points, the minimum number of operations required to correlate is about 2 x 108. Correlation at each possible position gives rise to a score which described the similarity with the reference.

The reference data area 1 initially has the position shown in Figure 1, relative to the signal data area 2, and its 64 x 64 points are in principle correlated with those points of the data area 2 which it overlies (both areas 1 and 2 are bounded by solid lines). In this example, ten correlation cells are linked together to constitute a correlator. The number of correlation cells need not be 64, as the choice depends on the required correlation speed. In practice, the number of line correlators is chosen with the correlation speed requirement in mind, and this generally will be indicated by the rate at which the signal data is being altered and/ or updated.

All ten correlation cells work simultaneously, each calculating successive correlation scores for the complete overlap of the 64 x 64 reference with the scene.

Subsequently, the data area 1 is moved on by ten points at a time (e.g. to position 41, broken line) and at each position the next ten total correlation scores are calculated.

When the end of the first line is reached a complete line of the correlation surface has been generated. The date area 1 is then placed at the start of the next line of the scene (e.g. at position 42, chain line) and the process is repeated to generate the next line of correlation scores.

This process continues until every possible position of the reference data area 1 relative to the signal data area 2 has been correlated. For each point, the correlation process generates a 'score' which is a measure of the similarity, and the highest score is assumed to give the best correlation, i.e. the localised area of data area 2 which is most like the reference data area 1.

Figure 2 shows one example of an operation or function provided by a single correlation cell in which an incoming reference signal 3 is correlated with a stored 4-bit signal 4, and is used to illustrate the principle of correlation. Corresponding reference data and signal data elements are multiplied by individual multipliers 5 and the result summed in a summation device 6 to give a score. Strictly speaking, it is necessary to normalise the score by dividing the sum of the squares of the signal elements but this is not in practice always done. By transferring the incoming signal data 3 through a clocked shift register 7, all possible points of the incoming signal data are compared in turn with the stored reference data 4.

As multiplication is more time consuming to implements in hardware than, say, addition, it is possible to provide comparison algorithms based on simpler operations. Examples of such algorithms are given below: (a) the least square algorithm correlation score, S

(signal - reference)2 Reference signal (b) the absolute difference algorithm

(c) the least cubes algorithm

(d) binary correlation

Signal 2 Reference Reference Signal where 2 = AND or EX-NOR The correlation processor described in Figures 3 and 4 is able to perform any of these algorithms, but it does not actually perform these calculations; it accesses a look-up table where the appropriate results are stored.

Figure 3 shows in block diagramatic form the ten point correlation processor in accordance with the invention. It has two inputs 10 and 11 at which the reference data and signal data inputs are received.

These data streams are assembled into respective random access memories (R A M) 12 and 13. It is not necessary that the capacity of the R A M 13 be sufficient to hold the entire signal data base at any one time as the signal information can be fed in progressively as the above reference data area 1, (with reference to figure 1), scans over the signal area 2. Data from the two memories 12 and 13 is fed out under the control of the control and clock circuit 14 to the correlator 15. The nature of the correlator 15 is described subsequently in greater detail with reference to Figure 4. The correlator 15 acts to compare the two inputs which it receives and to provide an output when each correlation score has been calculated. Each output represents the effective score or similarity for each correlation position.

With reference to Figure 4, the correlator 15 consists of a number of identical cells 19. In this example, for sake of simplicity, only three cells 19, 24, 25 are illustrated, but in practice the number of cells would be determined by the required correlation speed, and in this example would be ten, as previously indicated, so as to permit the correlation of ten points to proceed simultaneously. Corresponding signal data and reference data which have been digitised to six-bits are extracted from the R A M's 12 and 13 of Figure 3 and used as the address fields of a further R A M 20. In practice, this R A M is a 4K x 12-bit device. The R A M 20 acts as a look-up table to implement the required correlation algorithm.It is thus pre-programmed to provide the required answer to all possible combination of valid input signals., The result is output from the R A M 20 and added to the contents of a twentyfour-bit accumulator 21. When all corresponding reference and signal elements have been processed in this manner, the total accumulation represents the correlation score and is provided at an output terminal 22.

The same reference data is simultaneously applied to the remaining cells 24 and 25. The signal data received by the subsequent cells is derived via a sixbit latch 26 which serves to delay the signal as compared with the reference so that the subsequent cells 24 and 25 provide a different correlation position.

In this example it is assumed that each digital word has six-bits, hence the latch 26 has a six-bit capacity.

Each of the cells also provides an output indicative of its score.

So far, the operation of the correlator has been described with reference to data words having the maximum length, i.e. 6-bits. When binary data is to be correlated, it is entered into the R A M's 12 and 13, and fed in "groups" of 6-bits to the correlation cells to address the R A M 20. Each group of 6-bits represents six binary words (i.e. l's or 0's). They are processed in exactly the same way as previously described, except that the R A M 20 now contains at each address location the result of performing and accumulating these six binary correlations.

However, since binary data occurring within one group of 6-bits of reference data is not correlated with binary data of other groups of signal data, it is necessary to re-cycle the reference data and signal data through the chain of correlator cells, five more times to achieve the effect of full cross-correlation for the binary data, which has been explained with reference to Figure 2 for 6-bits data. In practice, the binary data is simply read out from the R A M's 12 and 13 in all of six sequential occasions, with relative positions of the two data streams being shifted by one bit position each time.

This operation is equivalent to physically re-cycling the data, and can be implemented by shifting the outputs of the R A M's 12 or 13 by one word length, i.e. 1 bit on each occasion.

Thus, six times as many binary data points are correlated in the six cycles of the correlator operation.

However, since the size of the reference data is six times smaller as it, too, is binary as compared to 6-bit words, this is equivalent to correlating six points of the data areas 1 and 2. Overall, then, a given number of binary data points can be correlated six times more rapidly than can multi-level digital words each having 6-bits.

However, in some systems it may not be necessary, or even desirable, to recycle all the signal data the five additional occasions. On the first occasion that the signal data is correlated, only every 6th point in the correlation function is produced, but it may be possible to identify from this the probable location of the correlation peak. Thus, only intermediate points in the area of that location need to be obtained by re-cycling the signal data. This approach could considerably reduce the time needed to complete the correlation process.

Although the invention has, for the sake of clarity, been described with reference to the correlation of reference data and signal data organised as two-dimensional arrays, this is clearly not necessary, as the data may occur in, or-represent, any convenient format.

The correlator processor is extremely versatile as it is merely necessary to enter new data into the stores 20 to perform different comparison algorithms. Furthermore, if a number of algorithms are available, the algorithm being used can be dynamically changed so that the best algorithm for the current purpose can be selected. As the control of each cell in the multi-cell arrangement is identical, extra cells can easily be added or switched into circuit as the need arises.

Claims

1. A method of digital correlation including the steps of applying reference data, and a larger amount of signal data to a plurality of correlation cells in digital blocks, each of which has a predetermined number of bits; the same reference data being applied sequentially to each cell in turn to correlate signal data with reference data; and recycling signal data having a digital word format of fewer than said predetermined number of bits through said cells to correlate on subsequent cycles signal data which is not correlated on a preceding cycle until all signal data has been correlated with said reference data.

2. A method as claimed in claim 1 and wherein signal data having a digital word format of fewer than said predetermined number of bits is recycled until all signal data has been correlated with said reference data.

3. A method as claimed in claim 1 or 2 and wherein on each occasion that the signal data is recycled, it is shifted relative to the reference data by an amount equivalent to one digital word.

4. A method as claimed in claim 1, 2 or 3 and wherein in each cell, the reference data and the signal data are used to access the stored results of algorithms corresponding to predetermined correlation processes.

5. A correlation processor including a plurality of cascaded correlation cells; means for applying reference data and signal data to the cells so that each of the cascaded cells receives the same reference data simultaneously, whilst the signal data is applied sequentially to each cell in turn to correlate signal data with reference data, the data being in the form of digital blocks each of which has a predetermined number of bits; and means for recycling data having a digital word format of fewer than said predetermined number of bits through said cells until all signal data has been correlated with said reference data.

6. A processor as claimed in claim 5, and wherein each cell contains a stored look-up table containing the results of performing a specified correlation algorithm, and said reference data and said signal data together constitute an address field for said table, at which address is stored the results of performing said algorithm on said reference and signal data.

7. A processor as claimed in claim 6, and wherein each cell includes an accumulator to which is fed the contents of the addressed location of said table.

8. A correlation processor substantially as illustrated in and described with reference to Figures 3 and 4 of the accompanying drawings.

8. A processor as claimed in claim 7, and wherein each cell includes a latch for temporarily storing each digital block of signal data fed to the cell; and means for passing the digital block on to the next correlation cell.

9. A correlation processor substantially as illustrated in and described with reference to Figures 3 and 4 of the accompanying drawings.

Americknents to the ciakns have been fled as fo.ows 1. A method of digital correlation including the steps of applying reference data, and a larger amount of signal data to a plurality of correlation cells in digital blocks, each of which has a predetermined number of bits; the same reference data being applied to each cell concurrently and the signal data being applied sequentially to each cell in turn to correlate signal data with reference data; and recycling signal data having a digital word format of fewer than said predetermined number of bits through said cells to correlate on subsequent cycles signal data which is not correlated on a preceding cycle until all signal data has been correlated with said reference data.

2. A method as claimed in claim 1 and wherein on each occasion that the signal data is recycled, it is shifted relative to the reference data by an amount equivalent to one digital word.

3. A method as claimed in claim 1, and wherein in each cell, the reference data and the signal data are used to access the stored results of algorithms corresponding to predetermined correlation processes.

4. A correlation processor including a plurality of cascaded correlation cells; means (12,13,14) for applying reference data and signal data to the cells (A,B,C) so that each of the cascaded cells receives the same reference data simultaneously, whilst the signal data is applied sequentially to each cell in turn to correlate signal data with reference data, the data being in the form of digital blocks each of which has a predetermined number of bits; and means (12,13,14) for recycling data having a digital word format of fewer than said predetermined number of bits through said cells until all signal data has been correlated with said reference data.

5. A processor as claimed in claim 4, and wherein each cell contains a stored look-up table containing the resultssof performing a specified correlation algorithm, and said reference data and said signal data together constitute an address field for said table, at which address is stored the result sof performing said algorithm on said reference and signal data.

6. A processor as claimed in claim 5, and wherein each cell includes an accumulator to which is fed the contents of the addressed location of said table.

7. A processor as claimed in claim 6, and wherein each cell includes a latch for temporarily storing each individual block of signal data fed to the cell; and means for passing the digital block on to the next correlation cell.