GB2258371A - A proximity data transfer method and device - Google Patents

Abstract

Digital data is transferred by inductive or capacitive proximity between two systems A and B, e.g. a handheld portable data carrier or card 3 and a card reader 1, with transmission of a data bit occurring by suppression of one in a group of three clock pulses, by lowering the reactive impedance in one of the systems and synchronization of the triple pulse cycles occurs automatically by transmission of the first data bit. <IMAGE>

Description

A PROXIMITY DATA TRANSFER METHOD AND DEVICE The subject matter of this invention relates to the art of transferring data between two objects or systems by inductive or capacitive proximity, more specifically from a portable data carrier to an external data receiver, or in the reverse direction. Where data are held in digital form, it would be most convenient to arrange their transfer in the form of binary pulses or spikes but this has to reckon with the adverse influence of noise spikes which may have amplitudes of the same order as the regular data. If this difficulty could be overcome, the general simplicity of transferring and retrieving data by proximity pulse transfer would make its application to handheld portable data carriers or cards very attractive.

Accordingly, the task to be solved is how to configure pulse transference so as to eliminate the known disadvantages and to maximize data transfer speed.

A beginning to resolve the problem has been made in the published patent GB 1,314,021 by the author but residual difficulties in applying the concepts to synchronous data transmission remained.

The theory is as follows: If a data bit is represented by a quenched (suppressed) clock pulse, and the data signal and the quenching signal occupy a definite synchronously defined period within a cyclically repeated pulse group, the quenching effect would not merely apply to the pulse the elimination of which represents the data bit but also to any noise spike within the said period. On the other hand, a zero data bit position may have plenty of noise spikes in addition to the clock spike; however, this would in no way alter the zero data bit into a "1" data bit. However, in synchronous data transfer, a noise spike can affect the synchronism and bring it out of step by adding further clocking spikes in the dependent system which were not supplied by the primary system.The present invention answers this problem by providing automatic restoration of synchronism with every high data bit transferred . The method for achieving this is characterized in claim 1 and four subsidiery claims. The essential features of a circuit for implementing the new method are given in claims 6 to 13.

The invention will Row be explained with the aid of drawings in which Fig. 1 shows a card with two embedded capacitive antennas and the signal retriever circuit connected to them.

Fig. 2 shows a survey of voltages occuring at 12 points of the circuit Fig. 3 shows merely those elements of the card reader unit circuitry which are not fully identical to those shown in Fig. 1 for the card.

Fig. 4 indicates the modifications of Fig.1 circuitry when in place of the capacitor antenna a flat spiral coil is laid into the reader disk and card disc.

Fig. 5 is an equivalent circuit to explain the data transfer method.

To begin with, fig. 3 shows the approximate mutual position of the Reader plate 1 and chip card plate 3 during the read/write process Accordingly, the capacitor disks 2d and 46 are separated by about one to three centimetres. The same applies to the capacitor discs 2 ss and 4 , The clock pulse supply arm &alpha; is 1800 out of phase with that of the# ffi arm.

The voltages which the reader terminal applies to the electrodes 24..

and < of Fig. 3, are graphically illustrated on rows 1 and 2 0f the voltage-time diagram in Figure 2. The voltages that arise from the reactive transfer in the metal plates~40 &alpha; and respectively would be similar to those shown in rows 1 and 2 respectively, if the impe dances measured against a quasi ground level were very high, for exampl 50 Mfl.At lower bleeder resistance, say at 5 Mfl , the differentiator effect comes into play and the potential of the embedded plate 4# would show the picture shown in row 3 at a given clock frequency. The exact shape is not critical since these pulses are used to trigger bistables into alternate states, and even very short spikes would be admissible to this end.

Before dis#issing the functions of the circuit of Figure 1, here follows a brief review of components. 4 amd 4 are field effect transistors with a Tow leakage current when the gate is at ground levels and drops to a low resistance when the voltage exceeds the voltage drop across the diode## dw These transistors are instrumental in conveying to the circuit of Fig. 1 standard logic level data spikes and clock spikes. Similarly, field effect transistors and and a are instrumental in sending to the Reader Terminal data, and Ta can be used for stopping the terminal from sending clock pulses in order that the card electronics gets extra time for processing some of the data.

Each data digit is embedded in three clock pulses; more accurately it is embedded in the second one of three clock pulses. If a number contains many binary zeros, the monotonous flow of clock pulses continues unchanged.But the clock pulses occur in groups of three pulses due to the use of a count three counter counting steps a, b, c, a b c and so on.A data bit can only appear during the period 'b'.

The basis of synchronization is the two-bit counter using two D-type bistables III and IV. Similiar bistables (I and II)are used to differentiate a high data bit from a low data bit.

In the example given the repetitive count is given by the states 1,2,3; the O-state is skipped,using AND gate 6 for this purpose.

A high data bit to be transfered from the card circuit 100 to the Reader must pass through the AND gate 9 which is enabled only during the 'b' period (count 2) of the counter. If the data to be transferred are held in a shift register the shift clock is obtained as an output from NAND gate 7 at the beginning of each 'b'period. The high output from AND gate 9 is applied to the con trolgate ot-ansnsvor l, , which then virtually shortens the capacitor stor plate < to ground. As a consequence there is a low resistance path from the plate#to the counterphase plate 4/3 which amounts to a drastic reduction of impedance to the supply line of the 2 G pulses.As a consequence, there will be a major increase in the load current across the resistor Rm in the Reader unit. This is detected by a sensor elementd A and used in the further circuitry to present a logic "1" level to the Reader computer.

The data transfer in the opposite direction, from the Reader to the card, is done as follows: As can be seen from Figure 3, a high data bit is applied to the gate of transistorjmwhich virtually eliminateslduring time period "b" the clock pulse potential on the capacitor antenna#.As a .As a consequence, in Figure 1, this eliminates any voltage on gate G < , so that the reset potential of input point R remains high and the already set bistable I remains set with QI being high. These conditions can be followed through also on the voltage-time curves of Figure 2. On row 4 the gate G suddenly does not receive the regular spike, nor does the negative going reset spike develop on row 5 (CK ~. The bistable output QI (row 7) changes from square pulses t-remain high over two such pulses. This also affects the next bistable II, row~9.Strobed by clock pulses CKss 2 QII goes now high shortly after the beginning of time period 'b' and remains so until shortly after the end of period'b'. To obtain a data output which is cleanly cut off at the end of period 'b' one would have to provide extra gating but this is in practice not needed.

The small overlap is not of any consequence.The output of AND gate 5 represent a strobing spike roughly in the middle of each time sector (a,b,c), and therefore, the downstream circuit (the data card circuit) can use this spike for clocking the data into its register.

Finally, if the computer normally enters a reset signal to ensure that all registers and bistable are cleared before passing on a command etc., this can also be done by means of the present interface circuit. In this case, after the first data bit is sent in time sector 'b', another data bit is sent immediately following, in time sector 'c' This keeps the data output on line 9 of figure 2 high over the time periods 'b' and 'c'. The CK spike during the middle of period 'c' is a unique pulse useable by the downstream circuitry as a reset pulse. It is obtained as an output from the four-input AND gate 10 in Figure 1.

Figure 4 shows essentially the same circuitry when in place of a capacitor plate an inductive coil (2 2 /4 ,2 g/4 IJ) is used.

Such coils are preferably configured as spiral coils on printed film. When a logic "1" is to be sent from the Reader to the card, the crock pulse in time sector 'b' is simply stopped by the tran sistor/of the PNP type while the/transistor T8 shortens the coil to ground to ensure that no noise spike gets through during period 'b'.

Figure 5 makes clear how a data pulse is transferred.

High frequency clock pulses are applied in opposite phases to terminals and g . When the switch is open the load is 3 Megaohm, when closed it drops to a few hundred ohm. The capacitor plate on the left having been atnormal logical level of alternating voltages, now drops to near zero.

It remains to describe the manner by which the Reader circuit which is essentially identical to the card circuit of Figure 1 synchronizes its counter with that of the card, and vize versa.

It is already understood that the terminal and the data card send out a data bit only in the time bit sector 'b' of its own counter circuit It is now assumed that the receiving party's counter circuit is at that moment not in the 'b' period but in the 'c' period of its triple cycle. A high data bit received in Figure 1 will cause, as explained, the bistable II to go high,virtually at the beginning of time section 'b' in the sending circuit but arrives, according to the present assumption in time period 'c' of the counter in figure 1. What happens is simply this: g of bistable II, having previously been high goes low,applies a low-going pulse to capacitor#,and thus does the same to the setting input of counter bistable IV and the resetting input of the counter bistable III. This putS the counter immediately back into its time period 'b'. The same happens if a data bit is sent out to the Reader circuit and its counter is not synchronized; the very sending out of a data bit is therefore the synchronizing agent.

Claims (13)

1. A method for transferring digital data in serial form between a system "A" and a system "B" by proximity wherein system "A" generates a continuous chain of clock pulses which reappear in "B" as more or less differentiated spikes, characterized in that the transmission of a data bit occurs by the suppression of one in a group of three clock pulses by lowering the reactive transfer impedance either in system "A" or in system 1,B" dependent on the direction of transfer, and that the synchronization of the triple pulse cycles in "A" and "B" occurs automatically by the transmission of the first data bit.

2. A method for transfering digital data in serial form between a system "A" and a system "B" by proximity as in claim 1 wherein the reactive coupling means may be either inductive or capacitive ones.

3. A method for transferring digital data in serial form between a system "A" and a system "B" as in claims 1 and 2 characterized by an enhanced immunity to noise, firstly on account of the energy absorption coincident with the transmission of a data bit causing also the energy level of a noise signal to collapse or to be reduced below an effective threshold, and secondly when a noise spike shifts the coupling state from synchronization, this/immediately corrected with the transmission of the next high data bit.

4. A method as in Claim 1 characterized by using the time sector of the middle pulse of the triple pulse cycle for transmitting or receiving a data bit in system "A" or system "B", and wherein the transmission of a 'reset' signal fromsystem "A" to "B" or from system "B" to system "A" occurs only in the time sector of the third pulse of the said synchronized triple pulse cycle.

5. A method for transfering digital data in serial form between a system "A" and a system 'B" as in claims 1 - 4 wherein system "A" can impose on itself and on system "B", and vize versa, an interrupt command by freezing the transfer of clock signals in order to attend to the execution of processing steps within its own system and resume the data transfer after completion of the internal processing steps by unfreezing the clock pulse transmission.

6. An electrical circuit in systems "A" and "B" for implemen a ting the method according to claims 1 - 5, using/capacitor plate (2d ) or a spiral inductor (24) ) as reactive transmitter of clock pulses of one phase, and a second capacitor plate (2)3 ) or spiral inductor (24 ) as a reactive transmitter of clock pulses of opposite phase, both embedded in an insulating medium and essentially having the shape of a rectangular plate (1), furthermore in system "B" a self-contained data carrying component essentially a plate (3) of similar size as the transmitter plate (1) and wherein two separate metal plates (4#,4 ss ), or spiral inductors (4 < , 4 it ) receive the pulse field energies and pass them on to a data retrieval circuit which in accordance with claim 1 comprises a synchronizing and coordinating counter circuit whose states are limited to three states (a,b,c) and which, with the aid of a presetting circuit (capacitor C2 and conductor lines 50, 60, and 70) sets the said counter to its second count step ('b') by setting one of its bistables (IV ) and re-setting the other bistable (III) whenever the data recovering bistable (11) is triggered into its high state.

7. An electrical circuit in the system "A" which resembles the electrical data retrieval circuit in system "B" (the chip card), and wherein a current sensor element or a voltage drop element (dA) is provided to detect a percentage change in current charging the capacitor antenna (2 i) with clock pulses.

8. A data retrieval circuit as in Claim 6 connected to capacitor plates (4 and 4 ss ) comprising: a differentiator circuit (4c( ,R1), a differentiator amplifier (T1) having a low-going output (CKZ ) applied to a reset input (R) of a first D-type bistable (I), a second differentiator circuit (4/3 , R4) producing low-going output spike (CK/3l) applied to the clock input (CK) of said first bistable (I) with its on-state output (QI) being connected to the D-input of a second bistable (II), a third differentiator circuit (442,R5) by its amplifier transistor (T5) producing a third,high-going, clock spike (CK ss 2) applied in inverted form to the clock input (CK) of said second bistable (II) which normally fails to trigger the said bistable to set at its high output: (QII) except when the first bistable is n o t reset by a low-going pulse, i.e.

when said pulse (CK 4 ) is missing.

9. A data retrieval circuit as in Claim 8 which further comprises: a data strobing pulse made available to the downstream data storage registers of the card circuit (100) to sample the level of the data output line (QII) in the middle of the count period 'b'.

10. A data retrieval circuit as in Claim 8 which offers a 'reset' signal spike (CK ss 1) to the down-stream data storage registers of the card circuit (100) and which is gated to appear only in the time period 'c' of the triple clock cycle (a,b,c), but which to be effective must be preceded by a logic "1" data pulse.

11. A data retrieval circuit as in Claim8 and 10 wherein the downstream circuit of the card has the possibility of sending a high data bit upstream to the system "A" by applying a high logic level to the AND gate (9) whose other input (QV) is high during the period 'b' of the triple clock cycle, and, during that period,reaches the control gate of a transistor (T3) which shortens a high-ohmic resistor (R1) whereby the impedance of the pulse transfer (4#/24) is substantially lowered.

12. A data retrieval circuit as in claims 8 to 11 w h e r e i n the capacitor plates (4# and 4 ss ) are replaced by embedded flat spiral coils (5 , 4j3 , figure 4).

13. A data retrieval system as in Claim 8 to 12 wherein the circuit also contains a clock pulse emulator source whereby the steady supply of timing pulses would remain assured, thereby making the injection of anti-phase clockpulses ( p ) unnecssary.

TO THE CLAIMS HAVE BEEN FLED AS FOLLOWS 1. A method for transferring digital data in serial form between a system "A" and a system "B" by proximity wherein system "A" qenerates a continuous chain of clock pulses which reappear

in more or less #ifferentiated'spikesr# " ~ - characterized in that the transmission of a data bit occurs by the suppression of one in a group of three clock pulses by lowering the reactive transfer impedance either in system "A" or in system "B" dependent on the direction of transfer, and that the synchronization of the triple pulse cycles in "A" and "B" occurs automatically by the transmission of the first data bit.