GB2258066A

GB2258066A - Semiconductor memory redunduncy

Info

Publication number: GB2258066A
Application number: GB9123485A
Authority: GB
Inventors: Hyeon-Soon Jang
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1991-07-26
Filing date: 1991-11-05
Publication date: 1993-01-27
Also published as: FR2679692A1; JPH0528794A; ITMI912849A1; DE4132298A1; KR930003164A; GB9123485D0; ITMI912849A0; IT1251445B

Abstract

A redundancy device increases redundancy efficiency in a semiconductor memory device. Block select signals BLS each determined by a row address are applied to a fuse circuit MFB which also receives column addresses and generates redundancy signals REN. These are passed via selector circuits RS to redundant column decoders RCD, and to a circuit NDC for controlling normal column decoders NCD. Use of both a row address and column address for column redundancy control permits a decrease in the area of redundant cell array as well as an increase in the efficiency of the redundancy operation. <IMAGE>

Description

SEMICONDUCTOR MEMORY REDUNDANCY The present invention relates to semiconductor memory devices, and has application to redundancy devices of dynamic random access memories (DRAM).

Generally, a semiconductor memory device has a redundancy device, which repairs defects of normal cells with spare cells (redundant cells) by decoding a row address corresponding to defective normal cells, when several normal cells have defects. Also such a semiconductor memory device is typically provided with a plurality of decoders for decoding the addresses corresponding to the defective normal cells and for selecting the redundant cells. The spare cell array arranged with a plurality of spare cells (redundant cell array) is disposed near the normal cell array. A known decoding method for redundancy is such that, when normal cells in one of several blocks making up normal cell arrays have defects, the block including the defective normal cells is replaced with a redundancy cell block corresponding thereto.

A generally known redundant method will now be described with reference to Figure 1 of the accompanying diagrammatic drawings. The memory cell array of Figure 1 has a normal cell array with m X n and the redundant cell array with m x k (m, n and k are all positive integers).

Sensing signals ~REN1 to ~RENK for detecting whether or not a received address from the exterior is the address of a defective normal cell, are applied to normal column decoders NCD1 to NCDN through a normal decoder control circuit NCD. Each normal column decoder commonly controls a plurality of input/output gates each connected to each normal cell array, the normal cell arrays being disposed in the column direction of each normal column decoder.

In other words, for example, the normal column decoder NCDI simultaneously controls the input/output gates connected to normal cell arrays NCA11 to NCAMl through a common column select line(not shown), and in the same way, the normal column decoder NCDN simultaneously controls the input/output gates connected to normal cell arrays NCA1N to NCAMN through a common column select line (not shown).

Each of redundant sensing signals ~REN1 to ~RENK, produced from a plurality of fuse boxes FBl to FBK, is supplied to each of redundant column decoders RCD1 to RCDK. The connections between the redundant column decoders RCD1 to RCDK and redundant cell arrays RCA11 to RCAmk are the same as those between normal column decoders NCD1 to NCDK and the normal cell arrays NCA11 to NCAMK. In the above construction, if the address corresponding to one normal cell NCA1 1, has a defect, the input/output gates IOll to IOMI connected thereto are all disabled, and the input/output gates RIO11 to RIOT1 connected to redundant column decoder RCD1 are all enabled. Thereby, a repairing operation is carried out.Here, the input/output lines are shared by both the normal cell array and the redundant cell array.

Figure 1(A) of the accompanying diagrammatic drawings illustrates generation of the redundancy sensing signal ~RENK. The fuse box FBK has three fuse decoders 10a, 10b and 10c, and a gate control circuit 10 controlling a plurality of transmission gates 13 to 18 in the fuse decoders 10a, 10b and 10c. If a main fuse 11 of gate control circuit 10 is disconnected, the transmission gates 13 to 18 transfer column addresses A1 to Ag to sub-fuses 19 to 24. Here, six sub-fuses make three pairs, and by disconnecting one of three pairs, the combination of defective addresses is determined.Only when the combination of column addresses Al to Ag received from the exterior is matched with that of sub-fuses 19 to 24, the output of a NAND gate 28 goes to logic "LOW" state. In the same way, an output of logic "LOW" state is produced from the other fuse decoders 10b and 10c.Thereby the output of a NOR gate 29 generating the redundant sensing signal ~RENK is in logic "HIGH" state, to generate the redundant sensing signal ~RENK. Then a redundant column select signal RCSLK, i.e. output of the redundant column decoder RCDK of Figure 1(B) of the accompanying diagrammatic drawings, goes to logic "HIGH" state, and output DAIJ of the normal decoder control circuit NCD of Figure 1(C) of the accompanying diagrammatic drawings goes to logic "LOW" state. The redundant sensing signals of "HIGH" state and outputs DAIJ of logic "LOW" state are applied to redundant column decoders and normal column decoders, thus enabling the redundant column decoders and disabling the normal column decoders, respectively.The normal bit lines, corresponding to normal cell arrays, connected to normal input/output gates controlled by normal column decoder NCDN (n is a positive integer), are substituted with the redundant bit lines, corresponding to redundant cell arrays, the redundant bit lines being connected to redundant input/output gates controlled by redundant column decoder NCDK (k is a positive integer). That is, one normal array block comprised of one normal column decoder and normal cell arrays connected thereto is replaced with one redundant array block comprised of one redundant column decoder and redundant cell arrays connected thereto, at the rate 1:1.

Accordingly, since the greater is the number of the defective normal array blocks, the greater is the number of redundant array blocks replacing the defective normal array blocks, so that an increase of memory array area is inevitable. Furthermore, non-defective normal memory cells of one normal cell array block are replaced with redundant cells, resulting in poor redundancy efficiency.

Preferred embodiments of the present invention aim to provide a device capable of increasing redundancy efficiency.

According to a first aspect of the present invention, there is provided a redundancy device for replacing a defective normal cell with a spare cell in a semiconductor memory device, said semiconductor memory device having a normal column decoder and a redundant column decoder, said redundancy device comprising: a block selection means arranged to receive a row address and to generate therefrom a block select signal; a fuse means for receiving both a column address and said block select signal, to produce thereby a redundant sensing signal; a redundant selection means for receiving said redundant sensing signal and generating therefrom a redundant select signal; and a normal decoder controller connected to receive said redundant select signal, for controlling said normal column decoder.

Preferably, said normal column decoder is connected to receive an output of said normal decoder controller, and said redundant column decoder is connected to receive said redundant select signal.

Preferably, said block selection means comprises a plurality of logic gates or fuses.

Preferably, said fuse means comprises a main fuse, a plurality of sub fuses, and a plurality of logic gates receiving a signal indicative of a disconnection of said main fuse and receiving said block select signal.

According to another aspect of the present invention, there is provided a redundancy device of a semiconductor memory device having a plurality of normal memory cells and spare memory cells, the redundancy device comprising: a plurality of normal column decoders; a plurality of redundant column decoders; a plurality of block selection means each arranged to receive a plurality of row addresses and to generate therefrom a plurality of block select signals; a plurality of fuse means each for receiving a plurality of column addresses, and for receiving said block select signals from each block selection means, to produce thereby a plurality of redundant sensing signals;; a plurality of redundant selection means each for receiving said redundant sensing signals from each fuse means, to generate thereby a plurality of redundant select signals, each redundant select signal being applied to each redundant column decoder; and a normal decoder controller for receiving said redundant select signals and controlling said normal column decoders.

Preferably, each said block selection means comprises a plurality of fuses or logic gates receiving said row addresses.

Preferably, each said fuse means comprises a main fuse, a plurality of sub fuses, and a plurality of logic gates receiving a signal indicative of a disconnection of said main fuse and receiving said block select signal.

Preferably, said sub fuses are connected to receive said column addresses respectively.

According to a further aspect of the present invention, there is provided a redundancy device replacing a defective normal memory cell with a spare memory cell by using a fuse in a semiconductor memory device, said semiconductor memory device having a plurality of normal column decoders and redundant column decoders, said redundancy device comprising: a plurality of block selection means each for receiving a plurality of row addresses and thereby generating a plurality of block select signals; and a plurality of fuse means each having sub fuses of a given number connected to receive column addresses of the given number, a main fuse, and a plurality of logic gates receiving a signal indicative of a disconnection of said main fuse and receiving said block select signals, so that said fuse means produce a plurality of redundant sensing signals.

Such a device may further comprise a plurality of redundant selection means each for receiving said redundant sensing signals and producing therefrom a redundant select signal, and a normal decoder controller for receiving said redundant select signals thereby to control said normal column decoders.

Preferably, each said block selection mean comprises a plurality of logic gates or fuses.

The invention extends to a semiconductor device provided with a redundancy device according to any of the preceding aspects of the invention.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2 to 5 of the accompanying diagrammatic drawings, in which: Figure 2 is a block diagram illustrating one example of a memory array embodying the present invention; Figure 3 illustrates an example of the internal construction of a fuse box of Figure 2; Figure 3(A) shows one example of an embodiment of means for producing a block select signal of Figure 3; Figure 3(B) shows another example of an embodiment of means for producing the block select signal of Figure 3; Fig.4 illustrates an example of the internal construction of a main decoder control circuit of Figure 2; and Figure 5 illustrates an example of the internal construction of a redundant selector and redundant column decoder of Figure 2.

In the redundancy device of Figure 2 memory cell arrays (normal cell array and redundant cell array) are constituted as shown in Figure 1, in which like reference numerals designate like or corresponding parts. The redundant sensing signals ~RENll to ~RENKI of Figure 2 are indirectly applied to the normal decoder control circuit NCD controlling the normal column decoders due to redundant select circuits RS1 to RSK disposed between main fuse boxes and normal decoder control circuit NDC, while in Figure 1 the redundant sensing signals ~RENl to ~RENK from the fuse boxes are directly applied to the normal decoder control circuit NCD. Each redundant select circuit is connected to each main fuse box, the main fuse box having k fuse boxes (k is a positive integer).Hence, for example, a first redundant select circuit RS1 receives a plurality of redundant sensing signals from a first main fuse box MFB1. If any redundant sensing signals indicating a detected redundant state are received, the redundant column decoders provided with redundant select signals indicating a detected redundant state are enabled.

Fuse boxes in each main fuse box receive block select signals ~BLS from block select boxes BLS determined by the row address. As shown in Fig.2, the difference of the illustrated inventive memory array, in contrast with the conventional one of Figure 1, is to apply the block select signals ~BLS generated by the row address to the fuse boxes, and the construction for producing the redundant select signals ~RS from the fuse boxes.

Arrangement sizes of the normal array and of the redundant array are respectively m x n and m x k (m, n and k are positive integers). As shown in Figure 2, the illustrated embodiment of the invention employs m row decoders, n normal column decoders, k redundant column decoders, one normal decoder control signal ~NCD, k redundant select signals, k main fuse boxes, k x i fuse boxes and redundant sensing signals, and k x i block select signals each applied to each fuse box. The row decoders receive the output of address buffer (or row address buffer), that is row addresses whose part is applied to the block select circuit.Thus the information concerning the block selected by the combination of row addresses is transferred to the fuse boxes, the block being cell array group NCA11 to NCAlN and RCA11 to RCAlK corresponding to one row decoder RDI.

Referring to Figure 3 illustrating an example of the internal construction of fuse box FBKI in Figure 2, the block select signal ~BLSKI is applied to the fuse box through NAND gate 52. Thus, though the main fuse is disconnected in redundant mode, if the block select signal ~BLSKI is disabled, i.e. at logic "LOW" state, the redundant sensing signal ~RENKI of the fuse box FBKI, produced through the NOR gate 54, is at logic "LOW" state. The internal construction of the blocks 10a, 10b and 10c receiving the column addresses Al to Ag is the same as that of Figure 1. The column addresses Al to Ag can select the bit lines of the defective normal memory cells.

Figures 3(A) and 3(B) illustrate examples of generating the block select signal ~BLSKI which is applied to either one input terminal of the NAND gate 52. The examples of Figure 3(A) and Figure 3(B) respectively use NAND gate 55 and NOR gate 57, and fuses F1 to F6, to combine row addresses RA7 to RA 10. The symbols ~FP and ~PE stand for pre-charge and enable signals, respectively.

Figure 4 and Figure 5 illustrate one example of the normal decoder control circuit NDC and the internal construction of the redundant select circuit RSK, and the redundant column decoder RCDk used in the embodiment of Figure 2, respectively. Here, the redundant select signal ~RSK from the redundant select circuit RSK comprised of the NOR gate 65 is simultaneously supplied to both the redundant column decoder RCDK and the normal decoder control circuit NCD.

An example of the operation of the above described embodiment of the invention will now be explained in detail, with reference to the above mentioned construction.

Disconnection of the main fuse 51 indicates a redundant mode state, resulting in a logic "LOW" state of voltage level of node 53. However, if the block select signal ORSK, that is the input of the NAND gate 52, is at logic "LOW" state (disable state), the output of the NAND gate 52 is always logic "HIGH" state, so that the redundant sensing signal ~RENKI from the fuse box FBKI is at logic "LOW" state. The above fact is described in more detail referring to Figure 1(A).

When the output of NAND gate 52 is at logic "LOW", the transmission gates 13 to 18 are turned on. Thereby the address signals A1, A2 and A3 are applied to NAND gate 28, and simultaneously N type MOS transistors 25, 26 and 27, connected to a ground voltage terminal Vss, are turned off. In disconnecting the main fuse, one of three pairs of fuses, each connected to each address Ai(i is a integer of 1 to 9), is disconnected. Thus, if the combination of input addresses accords with the address of the defective memory cell, the NAND gate 28 is furnished with all input signals of logic "HIGH" state, and produces an output of logic "LOW" state. As a result, the redundant sensing signal ~RENKI from the NOR gate 54 is at logic "HIGH" state.The redundant sensing signal of logic "HIGH" state goes to logic "LOW" state through the redundant sense circuit RSK, and the signal ~RSK of logic "LOW" state is applied to the normal decoder control circuit NCDK.

Thereby, the normal decoder control signal ~NCDIJ shows logic "LOW" state, disabling the normal decoder. Also, the redundant column select signal RCSLK becomes logic "HIGH" state, to drive the corresponding redundant array block. The redundant sensing signal ~RENKI implies the block select signal OBLSK generated by the row address, as well as the column (or bit line) of the defective normal memory cell.

In the above-described embodiments of the present invention, the block select signal produced by receiving the row address is applied to the column redundant fuse box. Thus the effective redundancy operation is achieved.

Furthermore, since the normal columns can correspond to the redundant columns at i: 1 (i is a positive integer greater than 1), it is possible to suppress the needless increase of area of the redundant cell array.

While preferred embodiments of the present invention have been particularly shown and described, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing form the spirit and scope of the invention.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A redundancy device for replacing a defective normal cell with a spare cell in a semiconductor memory device, said semiconductor memory device having a normal column decoder and a redundant column decoder, said redundancy device comprising: a block selection means arranged to receive a row address and to generate therefrom a block select signal; a fuse means for receiving both a column address and said block select signal, to produce thereby a redundant sensing signal; a redundant selection means for receiving said redundant sensing signal and generating therefrom a redundant select signal; and a normal decoder controller connected to receive said redundant select signal, for controlling said normal column decoder.

2. A redundancy device according to Claim 1, wherein said normal column decoder is connected to receive an output of said normal decoder controller, and said redundant column decoder is connected to receive said redundant select signal.

3. A redundancy device according to Claim 1 or 2, wherein said block selection means comprises a plurality of logic gates or fuses.

4. A redundancy device according to Claim 1, 2 or 3, wherein said fuse means comprises a main fuse, a plurality of sub fuses, and a plurality of logic gates receiving a signal indicative of a disconnection of said main fuse and receiving said block select signal.

5. A redundancy device of a semiconductor memory device having a plurality of normal memory cells and spare memory cells, the redundancy device comprising: a plurality of normal column decoders; a plurality of redundant column decoders; a plurality of block selection means each arranged to receive a plurality of row addresses and to generate therefrom a plurality of block select signals; a plurality of fuse means each for receiving a plurality of column addresses, and for receiving said block select signals from each block selection means, to produce thereby a plurality of redundant sensing signals; a plurality of redundant selection means each for receiving said redundant sensing signals from each fuse means, to generate thereby a plurality of redundant select signals, each redundant select signal being applied to each redundant column decoder; and a normal decoder controller for receiving said redundant select signals and controlling said normal column decoders.

6. A redundancy device according to Claim 5, wherein each said block selection means comprises a plurality of fuses or logic gates receiving said row addresses.

7. A redundancy device according to Claim 5 or 6, wherein each said fuse means comprises a main fuse, a plurality of sub fuses, and a plurality of logic gates receiving a signal indicative of a disconnection of said main fuse and receiving said block select signal.

8. A redundancy device according to Claim 7, wherein said sub fuses are connected to receive said column addresses respectively.

9. A redundancy device replacing a defective normal memory cell with a spare memory cell by using a fuse in a semiconductor memory device, said semiconductor memory device having a plurality of normal column decoders and redundant column decoders, said redundancy device comprising: a plurality of block selection means each for receiving a plurality of row addresses and thereby generating a plurality of block select signals; and a plurality of fuse means each having sub fuses of a given number connected to receive column addresses of the given number, a main fuse, and a plurality of logic gates receiving a signal indicative of a disconnection of said main fuse and receiving said block select signals, so that said fuse means produce a plurality of redundant sensing signals.

10. A redundancy device according to Claim 9, further comprising a plurality of redundant selection means each for receiving said redundant sensing signals and producing therefrom a redundant select signal, and a normal decoder controller for receiving said redundant select signals thereby to control said normal column decoders.

11. A redundancy device according to Claim 9 or 10, wherein each said block selection mean comprises a plurality of logic gates or fuses.

12. A redundancy device substantially as hereinbefore described with reference to Figure 2, optionally together with any of Figures 3 to 5, of the accompanying drawings.

13. A semiconductor device provided with a redundancy device according to any of the preceding claims.