GB2257550A

GB2257550A - Monitoring program execution.

Info

Publication number: GB2257550A
Application number: GB9207531A
Authority: GB
Inventors: David Paul Meare
Original assignee: Fujitsu Services Ltd
Current assignee: Fujitsu Services Ltd
Priority date: 1991-07-11
Filing date: 1992-04-07
Publication date: 1993-01-13
Anticipated expiration: 2012-04-07
Also published as: GB9207531D0; GB9114975D0; GB2257550B

Abstract

A computer system has a dedicated I/O port for connection to a multi-channel logic analyser. Software components of interest are caused to set and clear bits of the I/O port on entry and exit. The I/O port, and other signals such as interrupts, are monitored by the logic analyser to produce a graphic representation of the behaviour of the system and the interaction between the components. <IMAGE>

Description

MONITORING A COMPUTER SYSTEM Background to the Invention This invention relates to computer systems and, more particularly, is concerned with an apparatus and method for monitoring a computer system.

In complex computer systems, functions are generally carried out by a mixture of independent and interdependent software subsystems. Monitoring such a system can be very complex.

In particular, it is extremely difficult to assess which subsystems are participating at any given time and, more importantly, to determine the chronology of the interactions between the various subsystems. This complexity is increased if it is also desired to associate these interactions with observed phenomena in the hardware of the computer, such as interrupt signals, or other types of control signals.

The object of the present invention is to provide a way of identifying the chronological and causal relationships between the functional behaviour of such computer systems hardware and the code being executed within them.

Summary of the Invention According the invention there is provided a method of monitoring a computer system comprising: causing the system to set and reset bits of an I/O port at predetermined points in its internal operation, and monitoring said I/O port by means of a multi-channel logic analyser to display a graphical representation of the behaviour of the computer system Brief Description of the Drawings Figure 1 is a block diagram of a computer system embodying the invention.

Figure 2 is a block diagram illustrating various software components in the computer system.

Figure 3 is a timing diagram illustrating the operation of the system.

Description of an Embodiment of the Invention One computer system embodying the invention will now be described by way of example with reference to the accompanying drawings.

Referring to Figure 1, the system comprises a microprocessor 10, connected to an interrupt controller 12 which receives interrupt signals INT1, INT2 etc. from other parts of the system.

The microprocessor is also connected to an 8-bit input/output (I/O) port 14. This port is dedicated for use in monitoring the internal behaviour of the system, as will be described, and is not used for conventional I/O operations.

The microprocessor 10, under software control, can independently set or reset individual bits of the I/O port 14. The port is connected to a set of eight external test points 16.

The operation of the computer system is analysed using a conventional multi-channel logic analyser 18. Some of the channels of the logic analyser may be connected to selected bits of the I/O port 14, while other inputs may be connected to other test points of interest, such as the interrupt lines.

Referring now to Figure 2, this shows, by way of example, some of the software components in the system In this example, it is assumed that it is desired to monitor the way the system responds to a particular interrupt signal (INT2). It is also assumed that, in response to this interrupt, an interrupt service routine (ISR) 20 is activated. This ISR calls and passes information to a task manager routine 22. The task manager, in turn, causes a lower level task 24 to run a number of times. Meanwhile, the operating system may receive and respond to a higher priority interrupt (INT1).

In order to monitor the behaviour of this system, the first two channels (channels 1 and 2) of the logic analyser 18 are connected to receive the interrupt signals INT1 and INT2, and channels 3-5 are connected to receive bits 0-2 from the I/O port 14.

The ISR 20 associated with INT2 is modified, by including extra code which causes it to set bit 0 of the I/O port to logic 1 on entry, and to reset this bit to logic 0 on exit.

Similarly, the task manager 22 is modified so as to cause it to set bit 1 of the I/O port to logic 1 on entry and to reset this bit to logic 0 on exit.

Similarly, the sub-task 24 is modified so as to cause it to set bit 2 of the I/O port to logic 1 on entry and to reset this bit to logic 0 on exit.

Referring now to Figure 3, this shows a typical display which might be obtained from the logic analyser in this example.

It can be seen that channels 1 and 2 display a short pulse whenever an interrupt INT1 or INT2 occurs. Channel 3 displays a signal which rises on entry to the ISR, and falls on exit. Channel 4 displays a signal which rises on entry to the task manager, and falls on exit. Channel 5 displays a series of signals which coincide with the individual activations of the sub-task.

From this display, it is possible in this example to deduce that INT1 is apparently interfering with the handling of INT2 in some way, as can be seen from the gap in channel 5whenever a pulse occurs in channel 1. Thus, the monitoring arrangement has provided useful information about the interactions between different subsystems.

In summary , it can be seen that small additions are made to the software, to cause it to turn specific I/O bits on or off at key points in the code. For example, a particular bit may be turned on at the start of a particular activity which it is desired to "highlight" and to be turned off at the end of this activity. Then, by observing the states of these bits by means of a logic analyser, a graphical representation of the activities of interest can be viewed and directly associated with any other signals which may be monitored by the logic analyser.

Claims

1. A method of monitoring a computer system comprising: causing the system to set and reset bits of an I/O port at predetermined points in its internal operation, and monitoring said I/O port by means of a multi-channel logic analyser to display a graphical representation of the behaviour of the computer system.

2. A method according to claim 1 wherein the bits are set and reset at predetermined points of particular software components.

3. A method according to Claim 2 wherein the bits are set and reset on entry and exit from particular software components.

4. A method according to any preceding claim wherein the logic analyser simultaneously monitors other signals in the system, such as interrupt signals.

5. A method according to any preceding claim wherein said I/O port is dedicated to monitoring the system.

6. A method of monitoring a computer system substantially as hereinbefore described with reference to the accompanying drawings.