GB2256967A - Method of depositing a pecvd teos oxide film - Google Patents

Method of depositing a pecvd teos oxide film Download PDF

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Publication number
GB2256967A
GB2256967A GB9212661A GB9212661A GB2256967A GB 2256967 A GB2256967 A GB 2256967A GB 9212661 A GB9212661 A GB 9212661A GB 9212661 A GB9212661 A GB 9212661A GB 2256967 A GB2256967 A GB 2256967A
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oxide film
teos oxide
pecvd teos
film
stress
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GB9212661A
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GB9212661D0 (en
GB2256967B (en
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Arvid C Carlson
Tung Hai Tom Wu
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Motorola Solutions Inc
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Motorola Inc
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

In a method of depositing PECVD TEOS oxide film (12) for a semiconductor device positive charge in the film is reduced by controlling the stress of the TEOS oxide film as-deposited. The positive charge in the PECVD TEOS oxide film (12) can be reduced by forming a film having a tensile stress as-deposited followed by an annealing step at 900 DEG C in oxygen and hydrogen chloride. The tensile stress in the film is obtained by controlling the amount of low frequency RF in the reactor or by reducing the RF power to reduce ion bombardment. <IMAGE>

Description

METHOD OF DEPOSITING A PECVD TEOS OXIDE FILM Background of the Invention This invention relates, in general, to semiconductor devices, and more particularly, to a method of forming a plasma enhanced chemical vapor deposited TEOS oxide.
Plasma enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide is used in the manufacture of semiconductor devices. PECVD TEOS oxide demonstrates superior step coverage, gap filling, planarizing capability, and good electrical properties, thus can be widely used in applications for trench isolation, interlayer dielectric films, and oxide spacers.
Despite the favorable characteristics of a PECVD TEOS oxide film, it has been recognized that these films exhibit a positive oxide charge under certain conditions.
If nitrogen is used to anneal the film, a charge may not be apparent. If an oxygen and hydrogen chloride (02/HC1) anneal is used, the film exhibits a positive oxide charge. It is more desirable to use an 02/HC1 anneal because they are commonly used in semiconductor processing. In addition, because 02/HC1 anneals are commonly used, they can not be avoided.
This positive oxide charge is undesirable because it can create, for example, a current leakage around an isolation trench when PECVD TEOS is used in trench refill isolation applications. Although this oxide charging problem has been recognized, no effective or practical solutions have been offered to date. It was suggested that increasing the 02/TEOS ratio during deposition might reduce the oxide charge, however, the change was only marginally effective and unacceptable oxide uniformity resulted.
Low pressure chemical vapor deposited (LPCVD) TEOS oxide does not exhibit a positive oxide charge, however, PECVD TEOS oxide offers better isolation trench refill characteristics than LPCVD TEOS oxide does. Therefore, it would be more desirable to reduce or eliminate the positive oxide charge in PECVD TEOS oxide films used for this application. Reducing or eliminating the positive oxide charge would simplify the trench isolation process because thick liner oxides or additional high concentration channel-stop doping would not be required.
In other applications it may be desirable to provide for a controlled amount of PECVD TEOS oxide film charge rather than eliminating it totally.
Summary of the Invention A method of depositing PECVD TEOS oxide film comprising the step of controlling positive charge in a PECVD TEOS oxide film by controlling the film stress of the PECVD TEOS oxide film as-deposited.
Brief Description of the Drawings FIG. 1 illustrates an enlarged, cross-sectional view of an embodiment of the present invention; and FIG. 2 illustrates a graph showing the relationship between the as-deposited film stress and negative flatband voltage for two reactors.
Detailed Description of the Drawings FIG. 1 illustrates an enlarged, cross-sectional view of a semiconductor device 10 having a PECVD TEOS oxide film 12 formed thereon. As noted earlier, PECVD TEOS oxide film 12 may be used as an interlayer dielectric, a trench refill isolation oxide, as well as for other interdielectric applications. Semiconductor device 10 is shown generally to cover these applications and, specifically a trench refill application. Trench 11 formed in semiconductor device 10 is filled by PECVD TEOS oxide film 12. The formation of PECVD oxide film 12 will be further described with reference to the remaining figures.
FIG. 2 illustrates a graph of the relationship between the as-deposited or as-formed film stress and negative flatband voltage (-Vfb) of a PECVD TEOS oxide film after anneal. A lower negative flatband voltage corresponds to a lower positive oxide charge. On x-axis 20 the film stress is plotted, while on the y-axis 22 the flatband voltage is plotted for a PECVD TEOS oxide film formed in either of two reactors as described below. The curve for experimental data taken for a PECVD TEOS oxide film formed in a Novellus Concept-1 reactor is shown by line 32, while the curve for experimental data taken for a PECVD TEOS oxide film formed in an Applied Materials CVD-5000 reactor is shown by line 30.
The relationship between positive oxide charge and as-deposited film stress was discovered during experimentation. Line 24 exhibits the state where asdeposited film stress is equal to zero. To the right of line 24, the as-deposited film stress is tensile, while to the left of line 24, the as-deposited film stress is compressive. As can be seen by the graph, the positive oxide charge in a PECVD TEOS oxide film may be controlled by controlling the film stress of that film as-deposited.
A method of reducing the positive charge in a PECVD TEOS oxide film comprises forming the PECVD TEOS oxide film to have an as-deposited tensile stress or a less compressive stress. A PECVD TEOS oxide film which exhibits asdeposited tensile stress can also be said to have a lower density than a film exhibiting as-deposited compressive stress.
Those skilled in the art do not desire to form tensile stress films because films having a tensile stress tend to absorb moisture and are less stable. Due to the poor quality and nature of tensile films, it is general practice to avoid forming films having tensile stress in favor of forming compressive stress films. In the present invention, an annealing is performed subsequent to depositing the PECVD TEOS oxide film with a tensile stress to produce a compressive film with lower or no oxide charge. In a preferred embodiment, the anneal is carried out at a temperature of approximately 900 0C in an ambient preferably comprised of oxygen and hydrogen chloride for approximately 30 minutes. The sequence of depositing and then annealing overcomes the undesirable qualities of forming tensile stress films.
The general relationship, i.e. the reduction of positive oxide charge by forming a PECVD TEOS oxide film with a lower as-deposited compressive stress or an asdeposited tensile stress, is independent of the PECVD deposition machine type. However, controlling the film stress in different reactors may be different. For example, in an Applied Materials CVD-5000 reactor, the film stress is controlled by the total applied RF power.
To achieve a less compressive film or a tensile film, the RF power is reduced. A low-power deposition results in less compressive or tensile film due to less ion bombardment.
In a Novellus Concept-l reactor, the method of deposition to achieve a tensile stress or low oxide charge film is different than for the Applied Materials' reactor. In the Novellus reactor the film stress is controlled by the percent of low frequency RF power applied during the deposition. A low percentage of low frequency RF creates less ion bombardment which results in a less compressive or tensile film. In either case, however, a PECVD TEOS oxide film having a low oxide charge can be obtained by depositing a tensile stress film.
As can be readily seen, a method of controlling the charge in a PECVD TEOS oxide film has been provided. The charge may be controlled by controlling the as-deposited film stress of the PECVD TEOS oxide film. An asdeposited tensile stress PECVD TEOS oxide film exhibits low or no oxide charge after a 9000C anneal.

Claims (13)

1. A method of depositing PECVD TEOS oxide film comprising the step of: controlling positive charge in a PECVD TEOS oxide film by controlling the film stress of the PECVD TEOS oxide film as-deposited.
2. The method of claim 1 wherein controlling the film stress entails depositing the PECVD TEOS oxide film having an as-deposited tensile stress.
3. The method of claim 2 wherein controlling the film stress of the PECVD TEOS oxide film entails controlling the ion bombardment during deposition.
4. The method of claim 2 wherein controlling the film stress of the PECVD TEOS oxide film is accomplished by lowering the total RF power during the deposition.
5. The method of claim 2 wherein controlling the film stress of the PECVD TEOS oxide film is accomplished by decreasing the percent low frequency RF power during deposition.
6. A method depositing a PECVD TEOS oxide film comprising the step of reducing charge in a PECVD TEOS oxide film by forming the PECVD TEOS oxide film to have a low compressive stress or a tensile stress as-formed.
7. The method of claim 6 wherein forming the PECVD TEOS oxide film to have a low compressive stress or a tensile stress as-formed entails reducing the ion bombardment during deposition.
8. The method of claim 6 wherein forming the PECVD TEOS oxide film to have a low compressive stress or a tensile stress as-formed is accomplished by lowering the total RF power during the deposition.
9. The method of claim 6 wherein forming the PECVD TEOS oxide film to have a low compressive stress or a tensile stress as-formed is accomplished by decreasing the percent low frequency RF power during deposition.
10. The method of claim 1 or 6 further comprising the step of annealing the PECVD TEOS oxide film.
11. The method of claim 10 wherein the annealing takes place in an ambient comprised of oxygen and hydrogen chloride at a temperature of approximately 900 OC.
12. A method of depositing a PECVD TEOS oxide film, comprising the step of forming the PECVD TEOS oxide film to have a tensile stress as-formed to reduce charge in a PECVD TEOS oxide film; and annealing the PECVD TEOS oxide film in an ambient comprised of oxygen and hydrogen chloride at a temperature of approximately 900 OC.
13. A method substantially as hereinbefore described with reference to the accompanying drawings.
GB9212661A 1991-06-17 1992-06-15 Method of depositing a pecvd teos oxide film Expired - Fee Related GB2256967B (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2717307A1 (en) * 1994-03-11 1995-09-15 Paoli Maryse Method for isolating active areas of a semiconductor substrate by almost flat shallow trenches, and corresponding device.
EP0759481A1 (en) * 1995-06-23 1997-02-26 Novellus Systems, Inc. Method of depositing a stable fluorinated TEOS film
EP0893824A3 (en) * 1997-07-25 1999-05-12 Samsung Electronics Co., Ltd. Method of forming a trench isolation structure utilizing composite oxide films
US6080263A (en) * 1997-05-30 2000-06-27 Lintec Corporation Method and apparatus for applying a protecting film to a semiconductor wafer
US6271100B1 (en) 2000-02-24 2001-08-07 International Business Machines Corporation Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
WO2014183675A1 (en) * 2013-05-17 2014-11-20 无锡华润上华半导体有限公司 Filling structure of deep groove in semiconductor device, and filling method therefor
WO2022073176A1 (en) * 2020-10-09 2022-04-14 Applied Materials, Inc. Plasma-enhanced chemical vapor deposition processes for depositing passivation films on microelectronic structures

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
CN113517217A (en) * 2021-06-29 2021-10-19 上海华力集成电路制造有限公司 Method for forming HARP film

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4892753A (en) * 1986-12-19 1990-01-09 Applied Materials, Inc. Process for PECVD of silicon oxide using TEOS decomposition

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4892753A (en) * 1986-12-19 1990-01-09 Applied Materials, Inc. Process for PECVD of silicon oxide using TEOS decomposition

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Research disclosure on WPI,July 1991,32719,high conformalityhigh quality films by thermal CVD/RTP *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2717307A1 (en) * 1994-03-11 1995-09-15 Paoli Maryse Method for isolating active areas of a semiconductor substrate by almost flat shallow trenches, and corresponding device.
EP0673062A1 (en) * 1994-03-11 1995-09-20 France Telecom Isolation process for active zones of a semiconductor substrate using shallow planarised trenches, and device comprising such trenches
US5604149A (en) * 1994-03-11 1997-02-18 France Telecom Method of and device for isolating active areas of a semiconducor substrate by quasi-plane shallow trenches
EP0759481A1 (en) * 1995-06-23 1997-02-26 Novellus Systems, Inc. Method of depositing a stable fluorinated TEOS film
US6080263A (en) * 1997-05-30 2000-06-27 Lintec Corporation Method and apparatus for applying a protecting film to a semiconductor wafer
US6258198B1 (en) 1997-05-30 2001-07-10 Lintec Corporation Method and apparatus for applying a protecting film to a semiconductor wafer
EP0893824A3 (en) * 1997-07-25 1999-05-12 Samsung Electronics Co., Ltd. Method of forming a trench isolation structure utilizing composite oxide films
US6037237A (en) * 1997-07-25 2000-03-14 Samsung Electronics Co., Ltd. Trench isolation methods utilizing composite oxide films
US6271100B1 (en) 2000-02-24 2001-08-07 International Business Machines Corporation Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
WO2014183675A1 (en) * 2013-05-17 2014-11-20 无锡华润上华半导体有限公司 Filling structure of deep groove in semiconductor device, and filling method therefor
WO2022073176A1 (en) * 2020-10-09 2022-04-14 Applied Materials, Inc. Plasma-enhanced chemical vapor deposition processes for depositing passivation films on microelectronic structures

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Publication number Publication date
GB9212661D0 (en) 1992-07-29
GB2256967B (en) 1995-03-29

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Effective date: 19990615