GB2256767A - Television receiver - Google Patents

Abstract

An interface circuit is shown for a television signal receiver which includes decoding means for decoding scrambled or encrypted signals. An input interface circuit supplies the demodulated base-band video signal to the video de-scrambler and an output interface circuit supplies the de-scrambled signal to a video output port. The functions of the interface circuits are very similar in that they both provide, essentially, low pass filtering, the first to remove audio signals above the video base- band and the second to remove spurious signals produced by the de-scrambling process. The low pass filters are designed to provide optimum amplitude response over the video band and the resulting phase delays are compensated by a delay compensating circuit. <IMAGE>

Description

TELEVISION RECEIVER The present invention relates to an interface circuit in a television signal receiver, said receiver including decoding means for decoding scrambled or encrypted signals, wherein said interface circuit processes signals supplied between said decoding means and the remaining conventional parts of said receiver.

Television signals are scrambled or encrypted as a means of preventing unauthorised viewers from gaining access to particular channels. Usually, access to said scrambled channels is made available to anyone who is prepared to pay a subscription to receive the encoded programmes and in such cases the sophistication of the scrambling does not have to match the levels used in, for example, military applications. However, given that viewers are paying an additional premium for receiving what would be considered higher quality programmes, it is essential that the scrambling and de-scrambling process does not significantly degrade the signal quality and, furthermore, the viewer should not be put to any inconvenience once payment has been made.

Encrypted television signals are transmitted to a wide area of Western Europe from the Astra satellite and, for pay channels, a standard method of encryption is used and decoding circuits are available, under licence, from the organisation responsible for developing the encryption process. Said process, which may be referred to as de-scrambling or de-encryption, involves digitising a base band video signal, performing arithmetic manipulations on said digitised samples and, subsequently, re-converting said de-scrambled samples back into an analogue video waveform. In this context, the term base band video is used to identify an analogue video signal occupying a band width between dc and 5.5 MHz, with audio sub-carriers removed therefrom.

Typically, the signal is digitised at a rate of 14 MHz with an amplitude resolution of eight bits, therefore, to prevent aliasing, the base band video signal should be applied to a low pass filter providing rejection down to fifty dB at 7 Mhz, while passing signals up to 5.5 Mhz. In particular, it is important that the chrominance sub-carrier at 4.43 MHz should not be significantly attenuated by the low pass filter, to ensure that colour information is not lost.

A problem with known techniques is that, in order to achieve the required level of attenuation at 7 MHz without attenuating the chrominance sub-carrier, it is necessary to use high order filters which introduce significant levels of group delay. That is to say, although it is possible to obtain the required levels of attenuation at 4.43 MHz and at 7 MHz, this will result in the chrominance being shifted out of phase with respect to the luminance information.Such a shift not only creates problems with respect to the decryption process, delays of this type also undermine the conventional colour television decoding process, that is to say the generation of colour difference signals from the chrominance information and this latter effect is particularly important in the PAL system, in which the phase relationship of the chrominance signal is an important aspect of the colour decoding process.

It is an object of the present invention to provide an improved interface circuit for a television signal receiver having means for decoding scrambled signals.

According to a first aspect of the present invention, there is provided, in a television signal receiver including decoding means for decoding scrambled or encrypted signals, an interface circuit for processing signals supplied between said decoding means and the remaining conventional parts of said receiver, said interface circuit comprising a low pass filter and a delay compensating circuit for compensating group delays introduced by said low pass filter.

The present invention overcomes the problem associated with designing a filter in which a compromise must be reached between the attenuation gradient and group delay. In accordance with said first aspect, the filter is designed to provide the required level of attenuation and group delay is compensated by a delay compensating circuit.

In a preferred embodiment, the delay compensating circuit ensures that the delay between the chrominance and the luminance components of the base band video signal is less than 60 nanosecond. Preferably, the delay compensating circuit has a substantially flat gain response with respect to input frequency and a varying phase response with respect to input frequency, which compensates for the phase response of the low pass filter.

In a preferred embodiment, the compensating phase response is produced by inductance and capacitance and the gain of the phase compensating circuit is maintained substantially flat by means of negative feedback, generated by transformer-type coupling. Preferably, when modelled as a frequency transform, the inductance and capacitance introduce resonant poles which are mirrored by zeros introduced by said transformer-type coupling. Preferably, the transformer-type coupling behaves as a substantially ideal transformer over the operating frequency.

The invention will now be described by way of example only, with reference to the accompanying drawings, in which: Figure 1 shows a receiver for television signals transmitted by satellite, including a video de-scrambler, an input interface for said de-scrambler and an output interface for said de-scrambler; Figure 2 details the input interface shown in Figure 1, having a low pass filter and a delay compensating circuit; Figure 3A shows a graph of gain against frequency for the low pass filter shown in Figure 2; Figure 3B shows a graph of group delay against frequency for said low pass filter; Figure 3C shows a model of the delay compensating circuit shown in Figure 2; Figure 4 details the output interface circuit shown in Figure 2; and, In Europe, most scrambled or encrypted signals are transmitted by direct broadcasting by satellite.For example, high value films and high value sports events are transmitted in this way and subscribers must pay to use descrambling equipment, so that the scrambled programmes may be viewed in the usual way. However, scrambling techniques are also employed in tree and branch-type cabled networks and used for terrestrial broadcasting.

A receiver for a satellite television system is shown in Figure 1 in which a modulated signal from a satellite dish and its associated circuitry, is supplied to a tuner 15, arranged to de-modulate the video signal to base-band level. The base-band video signal is supplied to a filtering circuit 16 which, in addition to including filters, also includes circuits for providing deemphasis, gain and clamping. The base-band signal from tuner 15 also includes at least one audio component, the first conventional audio component being conveyed by frequency modulation on a carrier at, typically, 6.5 MHz, and additional audio signals may be conveyed at higher sub-carriers. The required audio signal is tuned and demodulated by an audio tuner 17 providing a base-band audio output at a port 18. Similarly, filter 16 provides a baseband video signal to a video base-band port 19, while a conventional UHF video and audio composite signal is available at UHF output port 20 by supplying the outputs from filter 16 and the audio tuner 17 to a UHF modulator 21.

The outputs from filter 16 and tuner 17 are supplied to ports 19 and 18 respectively via a respective video switch 22 and a respective audio switch 23.

When receiving conventional, non-scrambled, video signals, switches 22 and 23 are placed in the upper position, however, on receiving a scrambled signal of a form recognisable to the in-built video de-scrambler, switches 22 and 23 are automatically placed in the lower position, as shown in Figure 1.

The receiver includes a video de-scrambler 25, of proprietary type and consistent with the type of scrambling being employed for the encoded signals being detected. Proprietary video de-scramblers must be used in accordance with licensors specifications, which ensures that no degradation occurs to the video signal which may be perceived as being caused by the nature of the scrambling and de-scrambling process. Consequently, the base-band video signal from filter 16 is supplied to the video de-scrambler via an input interface circuit 26 and the output from said video de-scrambler 25 is supplied to video output port 19 and modulator 21 via an output interface circuit 27.

The input interface circuit 26 is shown in Figure 2, in which the filtered video base-band signal from switch 22 is supplied to an input port 31, which presents a high input impedance by means of transistor 32 arranged in an emitter-follower configuration. The signal supplied to port 31 is a baseband video signal having a level of one volt peak to peak and a video bandwidth of dc to 5.5 MHz, although an attenuated version of the sound carrier at 6.5 MHz may also be present. The video de-scrambler 25 digitises the video signal at 14 MHz and, with an amplitude quantisation resolution of eight bits, the video signal should be attenuated down to 40 decibel at 7 MHz before being supplied to the video de-scrambler 25.The output from the emitter-follower transistor 32 is, therefore, supplied to a low pass filter 33, arranged to provide the required level of attenuation above the previously identified pass band. It should be appreciated that the low pass filter shown in Figure 2 is designed to be complimentary with low pass filtering provided in filter 16 and in some situations further levels of filtering may be required within the input interface 26. The low pass filter 33 shown in Figure 2 is a third order Caur-type filter, alternatively identified as an elliptic-type filter and the frequency response of filter 33, in combination with filtering provided by filter 16, is shown in Figure 3A, in which gain or attenuation is plotted against frequency.As can be seen, the filter rolls off at 5.5 MHz, thereby not affecting the chrominance information at 4.43 MHz while providing fifty decibels of attenuation at 7 MHz. It should be noted, as shown in Figure 3A, that even greater attenuation is provided at 6.5 MHz, thereby further attenuating the audio sub-carrier which, in known filters, is usually dissipated to ground by a series resonance trap. In the output interface, in addition to providing the required level of attenuation at 7 MHz, particular attention is also paid to the level of attenuation at 9.57 MHz and at 14 MHz, which are frequencies at which noise is created by the operation of the video descrambler.

The topology of filter 33 is shown clearly in Figure 2 and procedures for calculating specific component values are known to those skilled in the art. However, an important aspect of the caur filter 33 is the provision of capacitor 34 which, placed across inductor 35, pads out the interwinding capacitance of said inductor and forms a similar function in relation to stray printed circuit board capacitance. Furthermore, the value of capacitor 34 may be selected to provide a useful zero in the filter transfer function.

As shown in Figure 3A, the caur filter has a good roll-off response but the resulting group delay characteristic is shown in Figure 3B, resulting in a peak around the position of the chrominance sub-carrier in the video signal.

Thus, although the filter 33 provides the desired level of attenuation, it also introduces a group (envelope) delay of the chrominance information with reference to the luminance information. Such a phase shift introduces two significant problems which, in previous designs, have resulted in compromises being made to the nature of the design of the filter itself, resulting in aliasing and picture degradation. The interface circuit shown in Figure 2 overcomes this problem by providing a group delay compensating circuit 36, arranged to provide maximum delay compensation at 4.43 MHz thus, rather than designing a filter which has minimum group delay at the level of a chrominance sub-carrier, the interface circuit shown in Figure 2 employs a group delay compensating circuit with maximum compensation at the frequency of the chrominance sub-carrier.

Referring to Figure 2, filter 33 is isolated by means of a transistor 37 arranged in an emitter-follower configuration. The nature of the compensating circuit itself is clear to anyone of ordinary skill with reference to the circuitry shown in Figure 2 although, to assist in understanding the operation of this circuit a simplified model is shown in Figure 3C. Circuit 36 includes a centre tapped inductor 38 and this is shown as two coupled inductors 51A and 51B in Figure 3C. An input is supplied to an input port 52 of the model shown in Figure 3C and an output is derived from port 53. Signal paths from said input port 52 to said output port 53 are provided via a capacitor 54 in series with an inductor 55, a single capacitor 56 and via the coupled pair of inductors 51A, 51B.However, it is important to note that the coupled pair of inductors 51A and 51B behave as a substantially ideal transformer over the operating frequency thus, in addition to the electrical connection from the bottom of 51A to the bottom of 51B, a magnetic connection between these two devices also exists thereby providing an additional transmission path.

Considering the operation of the circuit model shown in Figure 3C, the only path for dc is the electrical path via inductors 51A and 51B. As the frequency of the input signal increases the impedance of inductors 51 increases and the amount of current to pass through capacitor 56 increases.

However, as frequency increases, current may flow through the capacitor 56 to ground via inductor 51B and a resistor 57. The transmission of current through winding .51B which, co-operating with resistor 51, behaves in a transformer-like fashion and induces a current in winding 51A resulting in negative feedback. This mechanism specifically comes into play at resonant frequencies, which must exist due to the combination of capacitors and inductors, such that increasing current flow due to resonance results in increasing feedback current, giving a flat amplitude characteristic overall but with dramatic phase changes in the output signal relative to the input signal.

Furthermore, the amount of phase change occurring is selected by adjusting the value of resistor 57, which may be referred to as the damping factor.

For the phase compensation circuit 36 to operate satisfactorily, it is important that the transformer-type operation is as near to perfect as possible, that is to say, the transformer should operate as a substantially ideal transformer over the operating range of frequencies. Put another way, the coupling between the windings 51A and 51B must be extremely tight thereby ensuring that the resonant poles of the transfer function are mirrored by zeros introduced by the operation of the transformer. The delay in compensating circuit 36 should ensure that, irrespective of the degree of delay introduced by the low pass filter 33, the degree of delay between the chrominance and luminance signals should not exceed 50 nanosecond. The output from the delay compensating circuit is supplied to a high impedance amplifier to compensate for six db loss introduced by the first stage of the caur filter, it being noted that no significant loss is introduced by the delay compensating circuit 36. The high impedance amplifier is configured from a pair of cooperating transistors 39 and 40, in which negative feedback is introduced to extend the operating bandwidth of said transistors. It should be noted that the collector of transistor 39 is a floating current source and the feedback mechanism from the collector of transistor 40 is also a floating current source, thereby effectively isolating the positive supply rail 41, such that voltage variation occurring on said rail does not result in noise injection at the amplifier stage, the gain being determined by the relationship of resistors 42 and 43.Resistor 46 should have a relatively low resistance value which maintains stability.

After the filtering stage, consisting of the low pass filter 33, the phase compensation circuit 36 and the high impedance amplifier, the video signal is supplied to a clamping circuit 47 via a coupling capacitor 48. The clamping circuit 48 includes a MOSFET switch 49, controlled by a clamp signal which occurs at the end of the synchronisation period. A black reference level is supplied to a port 50 and a circuit 47 is arranged to clamp the video signal to said reference signal.

As previously stated, the input interface circuit 26 provides low pass filtering of the base-band video signal to prevent signals having a frequency above 7 MHz aliasing as lower frequency signals after analogue digital conversion at a sampling frequency of 14 MHz within the video de-scrambler 25. Within the de-scrambler 25, the de-scrambling process results in signals derived from the zero to 5.5 MHz base-band signal occurring at plus and minus 5.5 MHz about the sampling frequency of 14 MHz. If supplied to a conventional television monitor in this form or conventional television receiver via modulator 21, these additional frequencies will appear as noise, therefore a further stage of low pass filtering is required within the output interface 27.

The output interface circuit 27 is shown in Figure 4 and consists of a filter stage 61, a phase compensation stage 62 and a gain stage 63. The circuit design is substantially similar to the design of the input interface circuit and, after being buffered by a transistor 64, configured as an emitter-follower, the de-scrambled video signal is supplied to the low pass filter section, configured in the form of a seventh order caur filter, providing a very sharp cut-off.

Furthermore, in addition to providing the required level of attenuation at 7 MHz, particular attention is paid to the level of attenuation at 9.57 MHz and at 14 MHz, which are frequencies particularly pertinent to the operation of the video de-scramhler.

The phase compensation circuit 62 is substantially similar to circuit 36 in Figure 2 and may be analysed as detailed previously with reference to Figure 3C.

The gain stage 63 compensates for attenuation induced by the filter stage, thereby providing a base-band signal suitable for supplying to the video output port 19 or to the video modulator 21.

To check that subscribers have made the necessary payment to view programmes on an encoded channel, arrangements are often made for them to purchase a device containing an electrically erasable programmable read only memory device, configured to be of substantially similar shape to a credit card and, due to its on-board artificial intelligence, often referred to as a smart card. Unfortunately, the transmission of spurious electrical signals to said card may result in accidental erasure or re-programming of the card and for this reason, the way in which power is supplied to all portions of the video de-scrambler must be controlled very carefully. Consequently, delay circuitry must be introduced into the power supply for the de-scrambling module 25.

Thus, on receiving a request for power to be supplied to said interface circuits, the power supply unit first of all ensures that the video de-scrambler 25 itself has been powered-up correctly before connecting said interface circuits to their twelve volt supply rails.

Claims (6)

1. In a television signal receiver including decoding means for decoding scrambled or encrypted signals, an interface circuit for processing signals supplied between said decoding means and the remaining conventional parts of said receiver, said interface circuit comprising a low pass filter and a delay compensating circuit for compensating group delay introduced by said low pass filter.

2. An interface circuit according to Claim 1, wherein said delay compensating circuit ensures that delay between the chrominance and luminance is less than 60 nanosecond.

3. An interface circuit according to Claim 1 or Claim 2, wherein said delay compensating circuit has a substantially flat gain response and a compensating phase response with respect to input frequency.

4. An interface circuit according to any of Claims 1 to 3, wherein the compensating phase response is produced by inductance and capacitance and the gain of said circuit is maintained flat by negative feedback generated by transformer-type couplings.

5. An interface circuit according to Claim 4 such that, when modelled as a frequency transform, the inductance and capacitance introduce resonant poles which are mirrored by zeros introduced by said transformer-type couplings.

6. An interface circuit according to Claim 4 or Claim 5, wherein said transformer-type coupling behaves as a substantially ideal transformer over the operating frequency.