GB2253086A - Double-deck recording/reproducing apparatus - Google Patents

Abstract

A double-deck servo system controlling method for generically controlling each of two servo systems included in a double-deck recording and/or reproducing apparatus comprises the steps of determining which one of various signals obtained from individual decks is applied to a controller, e.g. a CPU, determining which one of the decks the applied signal comes from, processing the applied signal, and transmitting a switching pulse or control pulse to the deck where a drum phase signal has been produced. The signals distinguished are the drum frequency generator (DFG), the drum phase generator (DPG) and the capstan frequency generator (CFG). <IMAGE>

Description

2 2 5 J3.0 S 6 DOUBLE-DECK RECORDING/REPRODUCING APPARATUS This invention

relates to recording/reproducing apparatus, and is concerned particularly, although not exclusively, with methods of controlling 5 a servo system included in a double-type deck.

In a double-deck recording/reproducing apparatus provided with two decks, copying and/or editing of information stored on a recording medium is made possible, which enhances a user's convenience. A servo system in such a recording/reproducing apparatus generally includes a capstan servo serving as the transport control of a recording medium, e.g. a tape, a drum servo for adjusting the phase and revolutions per minute (rpm) of drum heads, and a back tension servo for controlling the back tension of the recording medium, wherein the back tension servo is a mechanical servo.

Conventional double-deck recording/reproducing apparatuses have been integrally formed of two recording/reproducing devices. Therefore, in order to control independently a corresponding servo system included in each deck, a pair of independent servo system controlling units are required.

Preferred embodiments of the present invention aim to provide a doubledeck servo system controlling method in which the servo system included in each deck of a double-deck recording/reproducing apparatus can generically be controlled.

According to a first aspect of the present invention, there is provided a method of generically controlling two servo systems in a double-deck recording/reproducing apparatus provided with first and second decks, the method comprising the steps of.

(a) distinguishing which signal among DFG, DPG, and CFG signals is 5 applied to a CPU built in a microcomputer:

(b) determining whether said applied signal comes from said first deck or said second deck; (c) processing said applied signal; (d) determining when a switching pulse is output with the lapse of a predetermined delay time if said applied signal is the DPG signal; (e) determining when a control pulse is output with the lapse of a predetermined delay time after the switching pulse was output; (f) determining whether the output signal is transmitted to said first deck or said second deck, based on where the DPG signal is produced; and (g) facilitating the transmission of the output signal to the determined deck.

Preferably, said steps (b) and (c) are carried out again after 25 discriminating whether not or the control pulse is applied to said CPU.

According to another aspect of the present invention, there is provided a method of controlling a recording and/or reproducing apparatus provided with first and second decks having respective servo systems, the method comprising the steps of receiving a signal from one of said decks, determining whether said signal comes from said first deck or said second deck, processing said signal, and controlling at least one of said servo systems in 5 response to said signal.

Such a method may further comprise any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.

The invention also extends to a double-deck recording and/or reproducing apparatus adapted to operate in accordance with a method according to any of the preceding aspects of the invention.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:

Figure I is a schematic block diagram of one example of a double-deck servo system controlling apparatus to which a method according to the present invention is applied; Figure 2 is a circuit diagram of one example of a built-in timer unit in the apparatus of Figure 1; and Figure 3 is a flowchart for explaining an example of a method according to the present invention.

In the double-deck servo system controlling apparatus of Figure 1, reference numerals 100 and 110 designate first and second decks, 120 designates a microcomputer (hereunder referred to as "MICOM"), 130 designates a key matrix, 10 1, 102, 111 and 112 designate first through fourth drum heads, 103 and 113 designate first and second audio control heads, 104 and 114 designate first and second drums, 105 and 115 designate first and second capstans, 106 and 116 are first and second audio video signal processing units, 107 and 117 designate first and second capstan drivers, and 108 and 118 are first and second drum drivers.

The first capstan 105 enables a tape loaded thereon to be transported, and the first and second drum heads 101 and 102 mounted on the first drum 104 at an angular separation of 1800 alternately come into contact with the tape by the rotation of first drum 104, thereby reading out the stored video information from the tape. Further, these drum heads 101 and 102 are enabled either to transmit read-out image information from the tape to the first video signal processing unit 106, or to record the processed video information onto the tape. By processing the video information received through an input/output (1/0) line 5, first video signal processing unit 106 alternately supplies the processed video information to first and second drum heads 101 and 102, and receives the read-out video information from the tape via the drum heads. The selection of either first or second drum head 101 or 102 is fulfilled in accordance with the logic state of a switching pulse obtained from the MICOM 120. That is, first drum head 101 is selected when the logic state of the switching pulse is High and second drum head 102 is selected when it is Low.

A motor and a motor driver are built within the first capstan driver 107, which can control or adjust the rotation speed of first capstan 105 in accordance with a first control signal generated from MICOM 120, which is pulse width modulated (hereinafter referred to as "PWM"). Moreover, the first capstan driver 107 produces and then delivers a capstan frequency generator (hereinafter referred abbreviately to as "CF&') signal to MICOM 120. This signal contains information stipulating the revolving speed of capstan 105. While adjusting the rotation speed of the first drum 104 in accordance with a second PWM control signal produced from MICOM 120, the first drum driver 108 generates and then furnishes MICOM 120 with both a drum frequency generator (hereunder referred simply to as "DFG") signal which is the rotation speed data of first drum 104, and a drum phase generator (hereinafter referred to as "DPG") signal which represents the position data of first and second drum heads 101 and 102 mounted on first drum 104. During recording, first audio control head 103 which is positioned between first capstan 105 and first drum 104 records a control pulse train obtained from MICOM 120 onto the control track of the tape, and during reproducing, reads out the recorded control pulse train from the control track and supplies it to MICOM 120.

In conjunction with the foregoing description, first and second drum heads 101 and 102, first audio control head 103, first capstan 105, first drum 104, first video signal processing unit 106, first capstan driver 107 and first drum driver 108 constitute the first deck 100.

The second deck 110 includes third and fourth drum head 111 and 112, second audio control head 113, second drum 114, second capstan 115, second video signal processing unit 116, second capstan driver 117, and second drum driver 118. These elements perform the same functions as corresponding elements of first deck 100.

Via first and second built-in timer units 121 and 122, MICOM 120 receives the control pulse, the CFG signal, the DFG signal, and the DPG signal obtained respectively from first audio control head 103, first capstan driver 107, and first drum driver 108. Further, MICOM 120 produces through first and second timer units 121 and 122 the switching pulse train, and first and second PWM control signals, for respective capstan and drum drivings. The key matrix 130 converts a user-designated operation control command into key data in the form of a binary logic value, and in turn supplies it to MICOM 120.

Figure 2 shows a detailed circuit diagram of either first or second timer unit 121 or 122 built in the MICOM 120 in the circuit of Figure 1. Here, only the operation of first timer unit 121 is explained since first and second timer units 121 and 122 have the same structure.

In Figure 2, reference numeral 200 indicates a counter, 211 to 216 time capture modules, 231 to 235 module control registers, 236 a comparator, 241 to 245 Schmitt trigger circuits, and 251 to 253 frequency-dividers.

By counting a system clock train from an external oscillator (not shown) via a first input line 261 connected thereto, counter 200 furnishes counted 16-bit time data to time capture modules 211 to 216 at a predetermined time. A second input line 262 is connected to first capstan driver 107 to receive the CFG signal from first capstan driver 107. First Schmitt trigger circuit 241 is connected to second input line 262 and waveshapes the received CFG signal. First frequency-divider 251 divides the waveshaped CFG signal obtained from first Schmitt trigger circuit 241 into a predetermined frequency ratio, and then supplies it to first time capture module 211.

A third input line 263 is connected to first drum driver 108 to receive the DFG signal, and supplies the received DFG signal to second Schmitt trigger circuit 242. After waveshaping, second Schmitt trigger circuit 242 delivers the waveshaped DFG signal to second frequency-divider 252 which performs frequency-dividing to the waveshaped DFG signal to be transmitted to second time capture module 212. Also, a fourth input line 264 is connected to first drum driver 108 to receive the DPG signal. Third Schmitt trigger circuit 243 waveshapes the DPG signal having passed through fourth input line 264 and provides the waveshaped DPG signal to third time capture module 213. A fifth input line 265 is connected to first audio control head 103 to receive control pulses. After successively waveshaping and frequencydividing the received control pulses, fourth Schmitt trigger circuit 244 and third frequency-divider 253 pass them to fourth time capture modules 214. A sixth input line 266 and fifth Schmitt trigger circuit 245 are not used in this example.

Each of the first through sixth time capture modules 211 to 216 is provided with an internal interrupt terminal, an internal control terminal, an internal input port, and an internal output port. The internal control terminals of modules 211 to 215 are connected to the corresponding second through sixth input lines 262 to 266 via the Schmitt trigger circuits 241 to 245 and frequency-dividers 251 to 253. Module 216 is selectively connected to lines 267, 268 and 269 by respective switches SW1, SW2 and SW3. Time capture modules 211 to 216 capture counted 16-bit time data from counter 200 at the moment when any signal obtained from the first deck 100 is applied to the control terminals, thereafter enabling the counted 16-bit time data to be latched at their internal output ports. Simultaneously time capture modules 211 to 216 produce an interrupt signal at their internal interrupt terminals and in turn supply the same signal to the internal CPU via an interrupt transfer line 271. Further, the internal input ports of the time capture modules are coupled to counter 200 through a time data transfer path 270, and the internal output ports are coupled via an input/output (1/0) transfer bus 27_2 to CPU.

In more detail, first through fourth time capture modules 211 to 214 capture time data from counter 200 at the moment when the waveshaped and frequency-divided CFG and DFG signals and control pulse, and the waveshaped DPG signal are applied to their corresponding control terminal.

That is, they receive the counted 16 bit time data from counter 200, via time data transfer path 270 and their corresponding input port, for the purpose of transmitting the counted time data which is temporarily latched at their corresponding output port to the CPU via 1/0 transfer bus 271. Simultaneously, the interrupt signal is generated from their corresponding interrupt terminal and supplied to the CPU through interrupt transfer line 272.

First through fifth module control registers 231 to 235 are connected to the corresponding first through fifth time capture modules 211 to 215, and set up a capture time so that the time capture modules 211 to 215 read from the counter 200 a time data counted at the moment when any part, such as rising edge, falling edge, etc., of the corresponding one of CFG, DFG, and DPG signals and control pulse produced from the first deck 100 is received at their corresponding control terminal.

Comparator 236 is connected to the sixth time capture module 216, for storing time data received from the CPU and comparing their stored data with time data from counter 200 via the sixth time capture module 216. If both the compared data are the same, comparator 236 generates a predetermined logic signal. In accordance with the predetermined logic signal, switching operation is implemented in one of switches SW1, SW2 and SW3. Accordingly, the PWM first control signal for drum driving, second control signal for capstan driving, and switching pulse appear at first through third output lines 267 to 269 connected to the respective corresponding switches SW1, SW2 and SW3.

The first output line 267 is connected to the first drum driver 108 to provide the first control signal for driving the drum thereto, and the second output line 268 is connected to the first capstan driver 107 for transmitting the second control signal thereto. In addition, the third output line 269 is connected to the first image processing unit 106 for the purpose of feeding the switching pulse thereto.

Figure 3 shows an example of a flowchart of a program processed by MICOM 120 of Figure 1, and more particularly the operation of the timer unit shown in Figure 2. Figure 3A shows the process wherein a predetermined data stored onto a tape is read out, and Figure 3B shows the process wherein data is stored onto the tape.

Referring to Figure 3, MICOM 120 has the built-in CPU which executes the program shown in Figure 3 each time that the interrupt signal from timer units 121 and 122 of Figure 2 is applied to the CPU. If the operation of the program is started by the interrupt signal, the CPU first distinguishes which signal among DFG, DPG, and CFG signals is applied thereto via 1/0 transfer bus 271 (steps 300, 400 and 500). When no one of -10these signals is applied to the CPU, the CPU determines whether doubledeck recording/reproducing apparatus remains at play mode or record mode (step 600). If double-deck recording/reproducing apparatus remains at play mode, the CPU discriminates whether control pulse CP is applied thereto (step 610). In steps 310, 410, 510, and 620, the CPU judges whether the applied signal or pulse comes from the first deck 100 or the second deck 200.

If the determination of steps 310, 410, 510, and 620 is affirmative, the progress of the program goes to the corresponding steps 320, 420, 520, and 620 so as to process the applied signal or pulse. That is, DFG, DPG, and CFG signals are compensated in error value to adjust the rotation speed or phase of the drum or capstan.

In step 700 of Figure 3B, it is determined whether the apparatus is in recording mode. If the DPG signal has been applied to the CPU, the CPU determines whether a switching pulse SP will be output with the lapse of a predetermined delay time after the application of the DPG signal (step 800). In record mode, the CPU determines whether a control pulse CP will be output with the lapse of a predetermined delay time after the switching pulse production (step 710). Depending on whether the applied DPG signal came from the first deck 100 or the second deck 200 (step 810), the CPU determines whether the switching pulse will be transmitted to first deck 100 or the second deck 200 (step 820) if the determination of step 800 is affirmative.

Similarly, the CPU determines whether the control pulse CP will be transmitted to the first deck 100 or the second deck 200 (steps 720, 730). Successively, the control or switching pulse is transmitted to the first deck 100 - 11 or the second deck 200 in accordance with the determination of steps 730 and 820.

According to the above-described embodiment of the invention, the double type servo system controlling apparatus simultaneously controls both decks by the additional provision of a timer unit built in a microprocessor, thereby simplifying the circuit structure and lowering the manufacturing cost thereof.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any 5 novel combination, of the steps of any method or process so disclosed.

Claims (7)

1. A method of generically controlling two servo systems in a double-deck recording/reproducing apparatus provided with first and second decks, the 5 method comprising the steps of- (a) distinguishing which signal among DFG, DPG, and CFG signals is applied to a CPU built in a microcomputer:

(b) determining whether said applied signal comes from said first deck or said second deck; (c) processing said applied signal; is (d) determining when a switching pulse is output with the lapse of a predetermined delay time if said applied signal is the DPG signal; (e) determining when a control pulse is output with the lapse of a predetermined delay time after the switching pulse was output; (f) determining whether the output signal is transmitted to said first deck or said second deck, based on where the DPG signal is produced; and (g) facilitating the transmission of the output signal to the determined deck.

2. A method as claimed as claim 1, wherein said steps (b) and (c) are carried out again after discriminating whether not or the control pulse is applied to said CPU.

3. A double-deck servo system controlling method substantially as hereinbefore described with reference to Figure 3 of the accompanying drawings.

4. A method of controlling a recording and/or reproducing apparatus provided with first and second decks having respective servo systems, the method comprising the steps of receiving a signal from one of said decks, determining whether said signal comes from said first deck or said second deck, processing said signal, and controlling at least one of said servo systems in response to said signal.

5. A method according to claim 4, further comprising any one or more of the features disclosed in the accompanying specification, claims, abstract and/or drawings, in any combination.

6. A double-deck recording and/or reproducing apparatus adapted to operate in accordance with a method according to any of the preceding claims.

7. A double-deck recording and/or reproducing apparatus substantially as hereinbefore described with reference to Figures 1 to 3 of the accompanying drawings.

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